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netlist: improve syntax of generic device descriptors. (nw)

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This commit is contained in:
couriersud 2020-05-18 00:20:09 +02:00
parent 40628bc269
commit 11af744ef3
3 changed files with 81 additions and 76 deletions
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2
src/lib/netlist/devices/nld_74125.cpp
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@ -76,7 +76,7 @@ namespace netlist
nld_power_pins m_power_pins;
};
struct desc_74125
struct desc_74125 : public desc_base
{
using invert_g = desc_const<1>;
using ts_off_on = time_ns<11>;

56
src/lib/netlist/devices/nld_roms.cpp
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@ -31,17 +31,18 @@ namespace netlist
NETLIB_CONSTRUCTOR(generic_prom)
, m_enabled(*this, "m_enabled", true)
, m_A(*this, 0, "A{}", NETLIB_DELEGATE(generic_prom, addr))
, m_CEQ(*this, 1, D::chip_enable_mask ^ static_cast<size_t>(0xffff), pstring("CE{}"),
, m_CEQ(*this, 1,
D::chip_enable_mask::value ^ static_cast<size_t>(0xffff), pstring("CE{}"),
std::array<nldelegate, 3>{ NETLIB_DELEGATE(generic_prom, ce<0>),
NETLIB_DELEGATE(generic_prom, ce<1>),
NETLIB_DELEGATE(generic_prom, ce<2>)})
, m_O(*this, D::data_name_offset, "O{}")
, m_O(*this, D::data_name_offset::value, "O{}")
, m_ROM(*this, "ROM")
, m_power_pins(*this)
{
}
using data_type = typename plib::least_type_for_bits<D::data_width>::type;
using data_type = typename plib::least_type_for_bits<D::data_width::value>::type;
private:
@ -49,9 +50,10 @@ namespace netlist
inline NETLIB_HANDLERI(ce)
{
using cet = typename D::chip_enable_time;
m_enabled = (m_CEQ() == D::chip_enable_mask);
m_enabled = (m_CEQ() == D::chip_enable_mask::value);
const auto delay = m_enabled ? D::access_time::value() : cet::value(N);
const data_type o = m_enabled ? m_ROM[m_A()] : (1 << D::data_width) - 1; // FIXME tristate !
const data_type o = m_enabled ? m_ROM[m_A()] :
(1 << D::data_width::value) - 1; // FIXME tristate !
m_O.push(o, delay);
}
@ -72,22 +74,22 @@ namespace netlist
}
state_var<bool> m_enabled;
object_array_t<logic_input_t, D::address_width> m_A;
object_array_t<logic_input_t, D::chip_enable_inputs> m_CEQ;
object_array_t<typename D::output_type, D::data_width> m_O;
object_array_t<logic_input_t, D::address_width::value> m_A;
object_array_t<logic_input_t, D::chip_enable_inputs::value> m_CEQ;
object_array_t<typename D::output_type, D::data_width::value> m_O;
param_rom_t<uint8_t, D::address_width, D::data_width> m_ROM;
param_rom_t<uint8_t, D::address_width::value, D::data_width::value> m_ROM;
nld_power_pins m_power_pins;
};
struct desc_82S126
struct desc_82S126 : public desc_base
{
static constexpr const size_t address_width = 8;
static constexpr const size_t data_width = 4;
static constexpr const size_t data_name_offset = 1; // O1, O2, ..
static constexpr const size_t chip_enable_inputs = 2;
using address_width = desc_const<8>;
using data_width = desc_const<4>;
using data_name_offset = desc_const<1>; // O1, O2, ..
using chip_enable_inputs = desc_const<2>;
// MATCH_MASK : all 0 ==> all bits inverted
static constexpr const size_t chip_enable_mask = 0x00;
using chip_enable_mask = desc_const<0x00>;
using chip_enable_time = times_ns2<25, 25>;
using access_time = time_ns<40>;
@ -102,15 +104,15 @@ namespace netlist
static constexpr const size_t data_name_offset = 0; // O0, O1, ..
};
struct desc_82S123
struct desc_82S123 : public desc_base
{
// FIXME: tristate outputs, add 82S23 (open collector)
static constexpr const size_t address_width = 5;
static constexpr const size_t data_width = 8;
static constexpr const size_t data_name_offset = 1; // O1, O2, ..
static constexpr const size_t chip_enable_inputs = 1;
using address_width = desc_const<5>;
using data_width = desc_const<8>;
using data_name_offset = desc_const<1>; // O1, O2, ..
using chip_enable_inputs = desc_const<1>;
// MATCH_MASK : all 0 ==> all bits inverted
static constexpr const size_t chip_enable_mask = 0x00;
using chip_enable_mask = desc_const<0x00>;
using chip_enable_time = times_ns1<35>;
using access_time = time_ns<45>;
@ -118,16 +120,16 @@ namespace netlist
using output_type = logic_output_t;
};
struct desc_2716
struct desc_2716 : public desc_base
{
// FIXME: tristate outputs
static constexpr const size_t address_width = 11;
static constexpr const size_t data_width = 8;
static constexpr const size_t data_name_offset = 0; // O0, O1, ..
using address_width = desc_const<11>;
using data_width = desc_const<8>;
using data_name_offset = desc_const<0>; // O0, O1, ..
static constexpr const size_t chip_enable_inputs = 2;
using chip_enable_inputs = desc_const<2>;
// MATCH_MASK : all 0 ==> all bits inverted
static constexpr const size_t chip_enable_mask = 0x00;
using chip_enable_mask = desc_const<0x00>;
using chip_enable_time = times_ns2<450, 100>; //CE, OE
using access_time = time_ns<450>;

3
src/lib/netlist/nltypes.h
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@ -162,6 +162,8 @@ namespace netlist
template <typename T> inline constexpr netlist_time NLTIME_FROM_US(T &&t) noexcept { return netlist_time::from_usec(t); }
template <typename T> inline constexpr netlist_time NLTIME_FROM_MS(T &&t) noexcept { return netlist_time::from_msec(t); }
struct desc_base
{
/// \brief: used to hold one static netlist_time value
///
template<netlist_time::internal_type value0>
@ -210,6 +212,7 @@ namespace netlist
///
template <std::size_t V>
using desc_const = std::integral_constant<std::size_t, V>;
};
} // namespace netlist