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srcclean in preparation for MAME 0.260 release branch

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This commit is contained in:
Vas Crabb 2023-10-22 01:50:53 +11:00
parent 63e8d2a1b4
commit 12266741f1
22 changed files with 236 additions and 236 deletions
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14
src/devices/bus/nubus/8lc.cpp
View File

@ -2,16 +2,16 @@
// copyright-holders:R. Belmont
/***************************************************************************
RasterOps ColorVue 8LC
RasterOps ColorVue 8LC
1, 2, 4, and 8 bpp at 1024x768 for the Macintosh LC
This is the same hardware as the ClearVueGS/LC board, which shows grayscale.
Both cards are documented to only work with the original LC due to some shortcuts
taken in how they map the address space.
taken in how they map the address space.
Note: the current ROM is a prototype from a former ROPS employee.
RasterOps' graphics driver software doesn't recognize it to enable the pan/zoom functionality.
ROM dumps from a retail card would resolve several questions.
RasterOps' graphics driver software doesn't recognize it to enable the pan/zoom functionality.
ROM dumps from a retail card would resolve several questions.
Map:
0xXXX00000: VRAM (768K)
@ -27,9 +27,9 @@
bit 8: monitor sense (1 = connected)
bit 11: Display enable switch on the 708+/SE this is derived from
TODO:
- Get real declaration ROMs for 8LC and ClearVueGS/LC and other related cards
- Implement pan/zoom functionality if supported, which likely requires VRAM to go through the TMS34061
TODO:
- Get real declaration ROMs for 8LC and ClearVueGS/LC and other related cards
- Implement pan/zoom functionality if supported, which likely requires VRAM to go through the TMS34061
***************************************************************************/

2
src/devices/cpu/h8/h8_intc.cpp
View File

@ -117,7 +117,7 @@ uint8_t h8_intc_device::ier_r()
void h8_intc_device::ier_w(uint8_t data)
{
m_ier = data;
// logerror("ier = %02x\n", data);
// logerror("ier = %02x\n", data);
update_irq_state();
}

12
src/devices/sound/swp00.cpp
View File

@ -33,7 +33,7 @@ const std::array<s32, 16> swp00_device::panmap = {
bool swp00_device::istep(s32 &value, s32 limit, s32 step)
{
// fprintf(stderr, "istep(%x, %x, %x)\n", value, limit, step);
// fprintf(stderr, "istep(%x, %x, %x)\n", value, limit, step);
if(value < limit) {
value += step;
if(value >= limit) {
@ -78,7 +78,7 @@ s32 swp00_device::fpsub(s32 value, s32 step)
s32 e = value >> 24;
s32 m = (value & 0xffffff) | 0xfe000000;
m = e < 0xc ? m - (step << e) : (m >> (e - 0xb)) - (step << 0xb);
// fprintf(stderr, "%07x %05x -> %x %08x\n", value, step, e, m);
// fprintf(stderr, "%07x %05x -> %x %08x\n", value, step, e, m);
if(m >= 0)
return 0;
if(e >= 0xc)
@ -99,7 +99,7 @@ s32 swp00_device::fpsub(s32 value, s32 step)
bool swp00_device::fpstep(s32 &value, s32 limit, s32 step)
{
// fprintf(stderr, "fpstep(%x, %x, %x)\n", value, limit, step);
// fprintf(stderr, "fpstep(%x, %x, %x)\n", value, limit, step);
// value, limit and step are 4.24 but step has its exponent and
// top four bits zero
@ -834,7 +834,7 @@ u8 swp00_device::state_r()
{
m_stream->update();
// logerror("state_r %x.%02x\n", m_state_adr >> 5, m_state_adr & 0x1f);
// logerror("state_r %x.%02x\n", m_state_adr >> 5, m_state_adr & 0x1f);
int chan = m_state_adr & 0x1f;
switch(m_state_adr & 0xe0) {
case 0x00: // lpf value
@ -905,8 +905,8 @@ u8 swp00_device::snd_r(offs_t offset)
void swp00_device::snd_w(offs_t offset, u8 data)
{
// if(rr[offset] == data)
// return;
// if(rr[offset] == data)
// return;
rr[offset] = data;

8
src/mame/dataeast/tumbleb.cpp
View File

@ -2490,10 +2490,10 @@ void tumbleb_state::suprtrio(machine_config &config) // OSCs: 14MHz, 12MHz & 8MH
/* video hardware */
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
// m_screen->set_refresh_hz(60);
// m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(529));
// m_screen->set_size(40*8, 32*8);
// m_screen->set_visarea(0*8, 40*8-1, 1*8-1, 31*8-2);
// m_screen->set_refresh_hz(60);
// m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(529));
// m_screen->set_size(40*8, 32*8);
// m_screen->set_visarea(0*8, 40*8-1, 1*8-1, 31*8-2);
// not measured, assume same as tumblep for now.
// Game has a very dull irq routine to stay at the mercy of set_vblank_time,
// reportedly happens to randomly crash at stage 3 boss + be laggy on later levels otherwise.

54
src/mame/ibm/ibm5550.cpp
View File

@ -86,13 +86,13 @@ private:
/*
static const gfx_layout kanji_layout =
{
32, 32,
RGN_FRAC(1,1),
1,
{ 0 },
{ STEP16(0,1), STEP16(16, 16) },
{ STEP16(0,16), STEP16(16*16, 16) },
32*32
32, 32,
RGN_FRAC(1,1),
1,
{ 0 },
{ STEP16(0,1), STEP16(16, 16) },
{ STEP16(0,16), STEP16(16*16, 16) },
32*32
};
*/
@ -145,13 +145,13 @@ void ibm5550_state::main_map(address_map &map)
void ibm5550_state::main_io(address_map &map)
{
map.unmap_value_high();
// map(0x00?0, 0x00?7).rw(m_dma, FUNC(am9517a_device::read), FUNC(am9517a_device::write));
// map(0x00?0, 0x00?7).rw(m_dma, FUNC(am9517a_device::read), FUNC(am9517a_device::write));
map(0x0020, 0x0021).rw(m_pic, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
// tested later, with bit 6 irq from PIC
// map(0x0040, 0x0047).rw(m_pit, FUNC(pit8253_device::read), FUNC(pit8253_device::write));
// map(0x0040, 0x0047).rw(m_pit, FUNC(pit8253_device::read), FUNC(pit8253_device::write));
// map(0x0060, 0x0060) / map(0x0064, 0x0064) standard XT keyboard
// map(0x0060, 0x0060) / map(0x0064, 0x0064) standard XT keyboard
// bit 0 on will punt before testing for $20-$21,
// but will be required on after $4c-$ec RAM holes above
@ -168,7 +168,7 @@ void ibm5550_state::main_io(address_map &map)
}
})
);
// map(0x00a1, 0x00a1) LED write?
// map(0x00a1, 0x00a1) LED write?
map(0x00a1, 0x00a1).lr8(
NAME([] (offs_t offset) {
// read thru NMI trap above, bit 3-0 must be low
@ -238,7 +238,7 @@ void ibm5550_state::ibm5550(machine_config &config)
// HD46505SP-2, unknown pixel clock
HD6845S(config, m_crtc, XTAL(40'000'000) / 10);
m_crtc->set_screen(m_screen);
// m_crtc->set_show_border_area(true);
// m_crtc->set_show_border_area(true);
m_crtc->set_char_width(16);
// IBM6343870 / MN50015SPG
@ -255,27 +255,27 @@ void ibm5550_state::ibm5550(machine_config &config)
PALETTE(config, m_palette, palette_device::MONOCHROME_HIGHLIGHT);
// ibm5160_mb_device &mb(IBM5160_MOTHERBOARD(config, "mb"));
// mb.set_cputag(m_maincpu);
// mb.int_callback().set_inputline(m_maincpu, 0);
// mb.nmi_callback().set_inputline(m_maincpu, INPUT_LINE_NMI);
// mb.kbdclk_callback().set("kbd", FUNC(pc_kbdc_device::clock_write_from_mb));
// mb.kbddata_callback().set("kbd", FUNC(pc_kbdc_device::data_write_from_mb));
// mb.set_input_default(DEVICE_INPUT_DEFAULTS_NAME(pccga));
// ibm5160_mb_device &mb(IBM5160_MOTHERBOARD(config, "mb"));
// mb.set_cputag(m_maincpu);
// mb.int_callback().set_inputline(m_maincpu, 0);
// mb.nmi_callback().set_inputline(m_maincpu, INPUT_LINE_NMI);
// mb.kbdclk_callback().set("kbd", FUNC(pc_kbdc_device::clock_write_from_mb));
// mb.kbddata_callback().set("kbd", FUNC(pc_kbdc_device::data_write_from_mb));
// mb.set_input_default(DEVICE_INPUT_DEFAULTS_NAME(pccga));
// FIXME: determine ISA bus clock
// ISA8_SLOT(config, "isa1", 0, "mb:isa", pc_isa8_cards, "cga", false);
// ISA8_SLOT(config, "isa2", 0, "mb:isa", pc_isa8_cards, "fdc_xt", false);
// ISA8_SLOT(config, "isa3", 0, "mb:isa", pc_isa8_cards, "lpt", false);
// ISA8_SLOT(config, "isa4", 0, "mb:isa", pc_isa8_cards, "com", false);
// ISA8_SLOT(config, "isa1", 0, "mb:isa", pc_isa8_cards, "cga", false);
// ISA8_SLOT(config, "isa2", 0, "mb:isa", pc_isa8_cards, "fdc_xt", false);
// ISA8_SLOT(config, "isa3", 0, "mb:isa", pc_isa8_cards, "lpt", false);
// ISA8_SLOT(config, "isa4", 0, "mb:isa", pc_isa8_cards, "com", false);
/* keyboard */
// pc_kbdc_device &kbd(PC_KBDC(config, "kbd", pc_xt_keyboards, STR_KBD_IBM_PC_XT_83));
// kbd.out_clock_cb().set("mb", FUNC(ibm5160_mb_device::keyboard_clock_w));
// kbd.out_data_cb().set("mb", FUNC(ibm5160_mb_device::keyboard_data_w));
// pc_kbdc_device &kbd(PC_KBDC(config, "kbd", pc_xt_keyboards, STR_KBD_IBM_PC_XT_83));
// kbd.out_clock_cb().set("mb", FUNC(ibm5160_mb_device::keyboard_clock_w));
// kbd.out_data_cb().set("mb", FUNC(ibm5160_mb_device::keyboard_data_w));
/* internal ram */
// RAM(config, RAM_TAG).set_default_size("256K").set_extra_options("512K");
// RAM(config, RAM_TAG).set_default_size("256K").set_extra_options("512K");
}
ROM_START( ibm5550 )

144
src/mame/misc/interflip8035.cpp
View File

@ -278,7 +278,7 @@
Toledo plays from 1 to 6 tokens.
All coins bet in the central line, but usually
the prize is multiplied by the number of inserted tokens.
the prize is multiplied by the number of inserted tokens.
TOLEDO PAYTABLE PRIZE
@ -409,7 +409,7 @@
Sevilla plays from 1 to 3 tokens.
All coins bet in the central line, but usually
the prize is multiplied by the number of inserted tokens.
the prize is multiplied by the number of inserted tokens.
SEVILLA PAYTABLE PRIZE
@ -687,26 +687,26 @@ void interflip8035_state::main_io_w(offs_t offset, u8 data)
CMD Binary
---- ---- ----
0x25 0010-0101 -> 001 (1) - 00101 Code=1: Program Clock Divider 5
0x25 0010-0101 -> 001 (1) - 00101 Code=1: Program Clock Divider 5
0x0C 0000-1100 -> 000 (0) - 01-100 Code=0: Keyboard Display Mode Set.
DD=01: 16 8bit character display.
KKK=100: Encoded Scan Sensor Matrix.
0x0C 0000-1100 -> 000 (0) - 01-100 Code=0: Keyboard Display Mode Set.
DD=01: 16 8bit character display.
KKK=100: Encoded Scan Sensor Matrix.
0xD6 1101-0110 -> 110 (6) - 101-10 Code=6: Clear
CD CD CD = 101: Clear all Zeroes
CF = 1: Fifo Status Cleared an the interrupt output line is reset.
Also, the sensor raw pointer is set to row 0.
CA = 0: No Clear all bit.
0xD6 1101-0110 -> 110 (6) - 101-10 Code=6: Clear
CD CD CD = 101: Clear all Zeroes
CF = 1: Fifo Status Cleared an the interrupt output line is reset.
Also, the sensor raw pointer is set to row 0.
CA = 0: No Clear all bit.
0xA5 1010-0101 -> 101 (5) - 0-0101 Code=5: Display Write inhibit/blanking
x = 0:
IWA IWB = 01: Inhibit port B
BLA BLB = 01: Blank port B
x = 0:
IWA IWB = 01: Inhibit port B
BLA BLB = 01: Blank port B
0x90 1001-0000 -> 100 (4) - 1-0000 Code = 4: Write display Ram
AI = 1 : Autoincrement
AD AD AD AD = 0000: Buffer base address to write.
AI = 1 : Autoincrement
AD AD AD AD = 0000: Buffer base address to write.
Then MPU sends gpkd data.
@ -730,17 +730,17 @@ void interflip8035_state::audio_io_w(offs_t offset, u8 data)
void interflip8035_state::main_p1_enc_data_w(u8 data) // Encoded lamps. (Sevilla & Toledo)
{
/*
Port P1 Maincpu
===============
Port P1 Maincpu
===============
P1.0 Coin Lamp Bit 0
P1.1 Coin Lamp Bit 1
P1.2 Coin Lamp Bit 2
P1.3 Interrupt Flag (enable/disable /INT via NAND Gate.)
P1.4 /CS PIA 1 - Debug: MPU usually writes 0x67, 0x6f, 0xe7 or 0xef to enable PIA access
P1.5 /CS PIA 2 - Debug: MPU usually writes 0x57, 0x5f, 0x57 or 0x5f to enable PIA access
P1.6 /CS PIA 3 - Debug: MPU usually writes 0x37, 0x3f, 0x37 or 0x3f to enable PIA access
P1.7 /GPKD Reset (Not implemented on device)
P1.0 Coin Lamp Bit 0
P1.1 Coin Lamp Bit 1
P1.2 Coin Lamp Bit 2
P1.3 Interrupt Flag (enable/disable /INT via NAND Gate.)
P1.4 /CS PIA 1 - Debug: MPU usually writes 0x67, 0x6f, 0xe7 or 0xef to enable PIA access
P1.5 /CS PIA 2 - Debug: MPU usually writes 0x57, 0x5f, 0x57 or 0x5f to enable PIA access
P1.6 /CS PIA 3 - Debug: MPU usually writes 0x37, 0x3f, 0x37 or 0x3f to enable PIA access
P1.7 /GPKD Reset (Not implemented on device)
*/
m_mp1 = data;
@ -773,17 +773,17 @@ m_outbit[5] -> Lamp: 6th. Coin
void interflip8035_state::main_p1_dec_data_w(u8 data) // Decoded lamps. (Costa Brava)
{
/*
Port P1 Maincpu
===============
Port P1 Maincpu
===============
P1.0 Lamp 1st. Coin
P1.1 Lamp 2nd. Coin
P1.2 Lamp 3rd. Coin
P1.3 Interrupt Flag (enable/disable /INT via NAND Gate.)
P1.4 /CS PIA 1 - Debug: MPU usually writes 0x67, 0x6f, 0xe7 or 0xef to enable PIA access
P1.5 /CS PIA 2 - Debug: MPU usually writes 0x57, 0x5f, 0x57 or 0x5f to enable PIA access
P1.6 /CS PIA 3 - Debug: MPU usually writes 0x37, 0x3f, 0x37 or 0x3f to enable PIA access
P1.7 /GPKD Reset (Not implemented on device)
P1.0 Lamp 1st. Coin
P1.1 Lamp 2nd. Coin
P1.2 Lamp 3rd. Coin
P1.3 Interrupt Flag (enable/disable /INT via NAND Gate.)
P1.4 /CS PIA 1 - Debug: MPU usually writes 0x67, 0x6f, 0xe7 or 0xef to enable PIA access
P1.5 /CS PIA 2 - Debug: MPU usually writes 0x57, 0x5f, 0x57 or 0x5f to enable PIA access
P1.6 /CS PIA 3 - Debug: MPU usually writes 0x37, 0x3f, 0x37 or 0x3f to enable PIA access
P1.7 /GPKD Reset (Not implemented on device)
*/
m_mp1 = data;
@ -803,19 +803,19 @@ void interflip8035_state::main_p1_dec_data_w(u8 data) // Decoded lamps. (Costa
void interflip8035_state::main_p2_w(u8 data)
{
/*
Port P2 Maincpu
===============
Port P2 Maincpu
===============
P2.0 A8 Address line
P2.1 A9 Address line
P2.2 A10 Address line
P2.3 A11 Address line
P2.4 /CE1 RAM 1 - Debug: MPU usually writes 0xef to enable NVRAM access
P2.5 /CE1 RAM 2 - Unused on these games
P2.6 /A0 GPKD - Selects -> [Data (rw)] or [Status(r)/ Control(w)] access on I8279
P2.7 /CS GPKD - Enable I8279 access.
P2.0 A8 Address line
P2.1 A9 Address line
P2.2 A10 Address line
P2.3 A11 Address line
P2.4 /CE1 RAM 1 - Debug: MPU usually writes 0xef to enable NVRAM access
P2.5 /CE1 RAM 2 - Unused on these games
P2.6 /A0 GPKD - Selects -> [Data (rw)] or [Status(r)/ Control(w)] access on I8279
P2.7 /CS GPKD - Enable I8279 access.
GPKD Notes: MPU writes 0x3f to data access and 0x7f to status/control
GPKD Notes: MPU writes 0x3f to data access and 0x7f to status/control
*/
m_mp2 = data;
@ -831,9 +831,9 @@ void interflip8035_state::main_p2_w(u8 data)
u8 interflip8035_state::main_p2_r()
{
/*
P1.4 /CS PIA 1 - Debug: MPU usually writes 0x67, 0x6f, 0xe7 or 0xef to enable PIA access
P1.5 /CS PIA 2 - Debug: MPU usually writes 0x57, 0x5f, 0xd7 or 0xdf to enable PIA access
P1.6 /CS PIA 3 - Debug: MPU usually writes 0x37, 0x3f, 0xb7 or 0xbf to enable PIA access
P1.4 /CS PIA 1 - Debug: MPU usually writes 0x67, 0x6f, 0xe7 or 0xef to enable PIA access
P1.5 /CS PIA 2 - Debug: MPU usually writes 0x57, 0x5f, 0xd7 or 0xdf to enable PIA access
P1.6 /CS PIA 3 - Debug: MPU usually writes 0x37, 0x3f, 0xb7 or 0xbf to enable PIA access
*/
u8 opt, ret;
opt = (m_mp1 & 0x70) >> 4; // valid PIA selectors are 3, 5, 6
@ -870,9 +870,9 @@ u8 interflip8035_state::main_p2_r()
u8 interflip8035_state::audio_p2_r()
{
/*
P2.4 Sound Code 0
P2.5 Sound Code 1
P2.6 Sound Code 2
P2.4 Sound Code 0
P2.5 Sound Code 1
P2.6 Sound Code 2
*/
return m_audio;
}
@ -888,7 +888,7 @@ void interflip8035_state::audio_p2_w(u8 data)
u8 change = false;
if(m_outbit[28] != BIT(data, 7))
change = true;
m_outbit[28] = BIT(data, 7); // P2.7 Topper Lamp
m_outbit[28] = BIT(data, 7); // P2.7 Topper Lamp
if(!m_outbit[28] && change)
{
@ -911,9 +911,9 @@ void interflip8035_state::audio_p2_w(u8 data)
I8243 IO Expander Interface x 3
Access:
P1 -> Enable PIA Access
IORW -> Destination Port (4, 5, 6, 7) 0xf4, 0xf5, 0xf6, 0xf7
Access:
P1 -> Enable PIA Access
IORW -> Destination Port (4, 5, 6, 7) 0xf4, 0xf5, 0xf6, 0xf7
****************************************************************/
@ -984,12 +984,12 @@ void interflip8035_state::exp3_p4_w(u8 data)
void interflip8035_state::exp3_p6_w(u8 data)
{
/* Swapped Sound Control bits
==========================
IO_Exp_Data -> Audio MPU P2
bit 0 - /Int /Int
bit 1 - Code2 P2.6
bit 2 - Code1 P2.5
bit 3 - Code0 P2.4
==========================
IO_Exp_Data -> Audio MPU P2
bit 0 - /Int /Int
bit 1 - Code2 P2.6
bit 2 - Code1 P2.5
bit 3 - Code0 P2.4
*/
u8 state;
@ -1009,7 +1009,7 @@ void interflip8035_state::kbd_sl_w(u8 data)
{
// Scan Line
m_kbd_sl = data;
// logerror("I8279: Scan Line: %02X\n", data);
// logerror("I8279: Scan Line: %02X\n", data);
}
u8 interflip8035_state::kbd_rl_r()
@ -1154,30 +1154,30 @@ static INPUT_PORTS_START( interflip )
// To select Game Mode all DSW5, DSW6 and DSW7 must be On. All others are ignored.
PORT_START("DSW_A")
PORT_DIPNAME(0x01, 0x00, DEF_STR(Unused)) PORT_DIPLOCATION("SW1:1")
PORT_DIPNAME(0x01, 0x00, DEF_STR(Unused)) PORT_DIPLOCATION("SW1:1")
PORT_DIPSETTING(0x00, DEF_STR(Off))
PORT_DIPSETTING(0x01, DEF_STR(On))
PORT_DIPNAME(0x02, 0x00, DEF_STR(Unused)) PORT_DIPLOCATION("SW1:2")
PORT_DIPNAME(0x02, 0x00, DEF_STR(Unused)) PORT_DIPLOCATION("SW1:2")
PORT_DIPSETTING(0x00, DEF_STR(Off))
PORT_DIPSETTING(0x02, DEF_STR(On))
PORT_DIPNAME(0x04, 0x00, DEF_STR(Unused)) PORT_DIPLOCATION("SW1:3")
PORT_DIPNAME(0x04, 0x00, DEF_STR(Unused)) PORT_DIPLOCATION("SW1:3")
PORT_DIPSETTING(0x00, DEF_STR(Off))
PORT_DIPSETTING(0x04, DEF_STR(On))
PORT_DIPNAME(0x08, 0x00, DEF_STR(Unused)) PORT_DIPLOCATION("SW1:4")
PORT_DIPNAME(0x08, 0x00, DEF_STR(Unused)) PORT_DIPLOCATION("SW1:4")
PORT_DIPSETTING(0x00, DEF_STR(Off))
PORT_DIPSETTING(0x08, DEF_STR(On))
PORT_START("DSW_B")
PORT_DIPNAME(0x01, 0x00, "General Test") PORT_DIPLOCATION("SW1:5")
PORT_DIPNAME(0x01, 0x00, "General Test") PORT_DIPLOCATION("SW1:5")
PORT_DIPSETTING(0x00, DEF_STR(Off))
PORT_DIPSETTING(0x01, DEF_STR(On))
PORT_DIPNAME(0x02, 0x00, "Reels Test") PORT_DIPLOCATION("SW1:6")
PORT_DIPNAME(0x02, 0x00, "Reels Test") PORT_DIPLOCATION("SW1:6")
PORT_DIPSETTING(0x00, DEF_STR(Off))
PORT_DIPSETTING(0x02, DEF_STR(On))
PORT_DIPNAME(0x04, 0x00, "Timing Test") PORT_DIPLOCATION("SW1:7")
PORT_DIPNAME(0x04, 0x00, "Timing Test") PORT_DIPLOCATION("SW1:7")
PORT_DIPSETTING(0x00, DEF_STR(Off))
PORT_DIPSETTING(0x04, DEF_STR(On))
PORT_DIPNAME(0x08, 0x00, DEF_STR(Unused)) PORT_DIPLOCATION("SW1:8")
PORT_DIPNAME(0x08, 0x00, DEF_STR(Unused)) PORT_DIPLOCATION("SW1:8")
PORT_DIPSETTING(0x00, DEF_STR(Off))
PORT_DIPSETTING(0x08, DEF_STR(On))
INPUT_PORTS_END

28
src/mame/misc/rfslotsmcs48.cpp
View File

@ -484,8 +484,8 @@ void rfslotsmcs48_state::exp2_p4_w(u8 data) // coils and emcounters
void rfslotsmcs48_state::exp2_p5_w(u8 data) // game lights
{
m_outbit[7] = BIT(data, 0); // insert coin lamp
m_outbit[8] = BIT(data, 1); // fault lamp
m_outbit[9] = BIT(data, 2); // start lamp
m_outbit[8] = BIT(data, 1); // fault lamp
m_outbit[9] = BIT(data, 2); // start lamp
m_outbit[10] = BIT(data, 3); // unused
}
@ -519,7 +519,7 @@ void rfslotsmcs48_state::kbd_sl_w(u8 data)
{
// Scan Line
m_kbd_sl = data;
// logerror("I8279: Scan Line: %02X\n", data);
// logerror("I8279: Scan Line: %02X\n", data);
}
void rfslotsmcs48_state::disp_w(u8 data)
@ -615,30 +615,30 @@ static INPUT_PORTS_START(babyfrts)
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("SWA") // switches order from schematics...
PORT_DIPNAME(0x01, 0x01, DEF_STR(Unknown)) PORT_DIPLOCATION("SWA:4")
PORT_DIPNAME(0x01, 0x01, DEF_STR(Unknown)) PORT_DIPLOCATION("SWA:4")
PORT_DIPSETTING(0x00, DEF_STR(On))
PORT_DIPSETTING(0x01, DEF_STR(Off))
PORT_DIPNAME(0x02, 0x02, DEF_STR(Unknown)) PORT_DIPLOCATION("SWA:3")
PORT_DIPNAME(0x02, 0x02, DEF_STR(Unknown)) PORT_DIPLOCATION("SWA:3")
PORT_DIPSETTING(0x00, DEF_STR(On))
PORT_DIPSETTING(0x02, DEF_STR(Off))
PORT_DIPNAME(0x04, 0x04, DEF_STR(Unknown)) PORT_DIPLOCATION("SWA:2")
PORT_DIPNAME(0x04, 0x04, DEF_STR(Unknown)) PORT_DIPLOCATION("SWA:2")
PORT_DIPSETTING(0x00, DEF_STR(On))
PORT_DIPSETTING(0x04, DEF_STR(Off))
PORT_DIPNAME(0x08, 0x08, DEF_STR(Unknown)) PORT_DIPLOCATION("SWA:1")
PORT_DIPNAME(0x08, 0x08, DEF_STR(Unknown)) PORT_DIPLOCATION("SWA:1")
PORT_DIPSETTING(0x00, DEF_STR(On))
PORT_DIPSETTING(0x08, DEF_STR(Off))
PORT_START("SWB") // switches order from schematics...
PORT_DIPNAME(0x01, 0x01, DEF_STR(Unknown)) PORT_DIPLOCATION("SWB:4")
PORT_DIPNAME(0x01, 0x01, DEF_STR(Unknown)) PORT_DIPLOCATION("SWB:4")
PORT_DIPSETTING(0x00, DEF_STR(On))
PORT_DIPSETTING(0x01, DEF_STR(Off))
PORT_DIPNAME(0x02, 0x02, DEF_STR(Unknown)) PORT_DIPLOCATION("SWB:1")
PORT_DIPNAME(0x02, 0x02, DEF_STR(Unknown)) PORT_DIPLOCATION("SWB:1")
PORT_DIPSETTING(0x00, DEF_STR(On))
PORT_DIPSETTING(0x02, DEF_STR(Off))
PORT_DIPNAME(0x04, 0x04, DEF_STR(Unknown)) PORT_DIPLOCATION("SWB:2")
PORT_DIPNAME(0x04, 0x04, DEF_STR(Unknown)) PORT_DIPLOCATION("SWB:2")
PORT_DIPSETTING(0x00, DEF_STR(On))
PORT_DIPSETTING(0x04, DEF_STR(Off))
PORT_DIPNAME(0x08, 0x08, DEF_STR(Unknown)) PORT_DIPLOCATION("SWB:3")
PORT_DIPNAME(0x08, 0x08, DEF_STR(Unknown)) PORT_DIPLOCATION("SWB:3")
PORT_DIPSETTING(0x00, DEF_STR(On))
PORT_DIPSETTING(0x08, DEF_STR(Off))
INPUT_PORTS_END
@ -830,7 +830,7 @@ void rfslotsmcs48_state::ajofrin(machine_config &config)
.----------------------------------.
| .-------------------------. |
| |·························| |
| '-------------------------' |
| '-------------------------' |
| Xtal |
| 6.000 MHz |
| .--------------------. |
@ -849,10 +849,10 @@ void rfslotsmcs48_state::ajofrin(machine_config &config)
| | GI AY-3-8910 | |
| | | |
| '--------------------' |
| .-------. |
| .-------. |
| |· · · ·| |
| '-------' |
'----------------------------------'
'----------------------------------'
*/
ROM_START(babyfrts)

2
src/mame/nmk/nmk16.cpp
View File

@ -686,7 +686,7 @@ void nmk16_state::hachamf_map(address_map &map)
map(0x09c000, 0x09c7ff).ram().w(FUNC(nmk16_state::txvideoram_w)).share("txvideoram");
// Main RAM, inc sprites, shared with MCU
map(0x0f0000, 0x0fffff).ram().share("mainram"); // ram is shared with MCU
map(0x0f0000, 0x0fffff).ram().share("mainram"); // ram is shared with MCU
}

8
src/mame/pc/quakeat.cpp
View File

@ -203,7 +203,7 @@ void quakeat_state::quake(machine_config &config)
{
PENTIUM2(config, m_maincpu, 233'000'000); /* Pentium II, 233MHz */
m_maincpu->set_addrmap(AS_PROGRAM, &quakeat_state::quake_map);
// m_maincpu->set_disable();
// m_maincpu->set_disable();
PCI_ROOT(config, "pci", 0);
// ...
@ -218,15 +218,15 @@ ROM_START(quake)
// 4N4XL0X0.86A.0011.P05
ROM_REGION32_LE(0x20000, "pc_bios", 0) /* motherboard bios */
// TODO: compressed
// ROM_LOAD("p05-0011.bio", 0x000000, 0x10000, NO_DUMP )
// ROM_CONTINUE( 0x1ffff-0xa0, 0xa0 )
// ROM_LOAD("p05-0011.bio", 0x000000, 0x10000, NO_DUMP )
// ROM_CONTINUE( 0x1ffff-0xa0, 0xa0 )
ROM_LOAD("quakearcadetournament.pcbios", 0x000000, 0x20000, NO_DUMP )
// Hitachi DK237A-21 A/A0A0, IDE/ATA 2.5" 2.1GB 4000 RPM
// WS03131880
DISK_REGION( "disks" )
// wrong chs 263,255,63
// DISK_IMAGE( "quakeat", 0, BAD_DUMP SHA1(c44695b9d521273c9d3c0e18c88f0dca0185bd7b) )
// DISK_IMAGE( "quakeat", 0, BAD_DUMP SHA1(c44695b9d521273c9d3c0e18c88f0dca0185bd7b) )
// regenerated from above, with -chs 4200,16,63 as per reported HDD label
DISK_IMAGE( "quakeat", 0, BAD_DUMP SHA1(9a422ad342aeddd447514d0287efde49e3de5fa8) )
ROM_END