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simplify masks

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This commit is contained in:
Michaël Banaan Ananas 2014-02-26 20:46:23 +00:00
parent 0caa890cca
commit 1259ee5648
2 changed files with 38 additions and 37 deletions
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34
src/emu/machine/rp5c01.c
View File

@ -59,7 +59,7 @@ enum
// register write mask
static const int REGISTER_WRITE_MASK[2][16] =
static const int register_write_mask[2][16] =
{
{ 0xf, 0x7, 0xf, 0x7, 0xf, 0x3, 0x7, 0xf, 0x3, 0xf, 0x1, 0xf, 0xf, 0xf, 0xf, 0xf },
{ 0x0, 0x0, 0xf, 0x7, 0xf, 0x3, 0x7, 0xf, 0x3, 0x0, 0x1, 0x3, 0x0, 0xf, 0xf, 0xf }
@ -347,8 +347,9 @@ WRITE_LINE_MEMBER( rp5c01_device::adj_w )
READ8_MEMBER( rp5c01_device::read )
{
UINT8 data = 0;
offset &= 0x0f;
switch (offset & 0x0f)
switch (offset)
{
case REGISTER_MODE:
data = m_mode;
@ -364,21 +365,21 @@ READ8_MEMBER( rp5c01_device::read )
{
case MODE00:
case MODE01:
data = m_reg[m_mode & MODE_MASK][offset & 0x0f];
data = m_reg[m_mode & MODE_MASK][offset];
break;
case BLOCK10:
data = m_ram[offset & 0x0f];
data = m_ram[offset];
break;
case BLOCK11:
data = m_ram[offset & 0x0f] >> 4;
data = m_ram[offset] >> 4;
break;
}
break;
}
if (LOG) logerror("RP5C01 '%s' Register %u Read %02x\n", tag(), offset & 0x0f, data);
if (LOG) logerror("RP5C01 '%s' Register %u Read %02x\n", tag(), offset, data);
return data & 0x0f;
}
@ -390,10 +391,13 @@ READ8_MEMBER( rp5c01_device::read )
WRITE8_MEMBER( rp5c01_device::write )
{
switch (offset & 0x0f)
data &= 0x0f;
offset &= 0x0f;
switch (offset)
{
case REGISTER_MODE:
m_mode = data & 0x0f;
m_mode = data;
if (LOG)
{
@ -408,14 +412,12 @@ WRITE8_MEMBER( rp5c01_device::write )
break;
case REGISTER_RESET:
m_reset = data & 0x0f;
m_reset = data;
if (data & RESET_ALARM)
{
int i;
// reset alarm registers
for (i = REGISTER_1_MINUTE; i < REGISTER_1_MONTH; i++)
for (int i = REGISTER_1_MINUTE; i < REGISTER_1_MONTH; i++)
{
m_reg[MODE01][i] = 0;
}
@ -435,22 +437,22 @@ WRITE8_MEMBER( rp5c01_device::write )
{
case MODE00:
case MODE01:
m_reg[m_mode & MODE_MASK][offset & 0x0f] = data & REGISTER_WRITE_MASK[m_mode & MODE_MASK][offset & 0x0f];
m_reg[m_mode & MODE_MASK][offset] = data & register_write_mask[m_mode & MODE_MASK][offset];
set_time(false, read_counter(REGISTER_1_YEAR), read_counter(REGISTER_1_MONTH), read_counter(REGISTER_1_DAY), m_reg[MODE00][REGISTER_DAY_OF_THE_WEEK],
read_counter(REGISTER_1_HOUR), read_counter(REGISTER_1_MINUTE), read_counter(REGISTER_1_SECOND));
break;
case BLOCK10:
m_ram[offset & 0x0f] = (m_ram[offset & 0x0f] & 0xf0) | (data & 0x0f);
m_ram[offset] = (m_ram[offset] & 0xf0) | data;
break;
case BLOCK11:
m_ram[offset & 0x0f] = (data << 4) | (m_ram[offset & 0x0f] & 0x0f);
m_ram[offset] = (data << 4) | (m_ram[offset] & 0x0f);
break;
}
if (LOG) logerror("RP5C01 '%s' Register %u Write %02x\n", tag(), offset & 0x0f, data);
if (LOG) logerror("RP5C01 '%s' Register %u Write %02x\n", tag(), offset, data);
break;
}
}

41
src/emu/machine/rp5c15.c
View File

@ -67,7 +67,7 @@ enum
// register write mask
static const int REGISTER_WRITE_MASK[2][16] =
static const int register_write_mask[2][16] =
{
{ 0xf, 0x7, 0xf, 0x7, 0xf, 0x3, 0x7, 0xf, 0x3, 0xf, 0x1, 0xf, 0xf, 0xf, 0xf, 0xf },
{ 0x3, 0x1, 0xf, 0x7, 0xf, 0x3, 0x7, 0xf, 0x3, 0x0, 0x1, 0x3, 0x0, 0xf, 0xf, 0xf }
@ -329,8 +329,9 @@ void rp5c15_device::rtc_clock_updated(int year, int month, int day, int day_of_w
READ8_MEMBER( rp5c15_device::read )
{
UINT8 data = 0;
offset &= 0x0f;
switch (offset & 0x0f)
switch (offset)
{
case REGISTER_MODE:
data = m_mode;
@ -342,11 +343,11 @@ READ8_MEMBER( rp5c15_device::read )
break;
default:
data = m_reg[m_mode & MODE_MASK][offset & 0x0f];
data = m_reg[m_mode & MODE_MASK][offset];
break;
}
if (LOG) logerror("RP5C15 '%s' Register %u Read %02x\n", tag(), offset & 0x0f, data);
if (LOG) logerror("RP5C15 '%s' Register %u Read %02x\n", tag(), offset, data);
return data & 0x0f;
}
@ -358,10 +359,13 @@ READ8_MEMBER( rp5c15_device::read )
WRITE8_MEMBER( rp5c15_device::write )
{
switch (offset & 0x0f)
data &= 0x0f;
offset &= 0x0f;
switch (offset)
{
case REGISTER_MODE:
m_mode = data & 0x0f;
m_mode = data;
if (LOG)
{
@ -376,14 +380,12 @@ WRITE8_MEMBER( rp5c15_device::write )
break;
case REGISTER_RESET:
m_reset = data & 0x0f;
m_reset = data;
if (data & RESET_ALARM)
{
int i;
// reset alarm registers
for (i = REGISTER_1_MINUTE; i < REGISTER_1_MONTH; i++)
for (int i = REGISTER_1_MINUTE; i < REGISTER_1_MONTH; i++)
{
m_reg[MODE01][i] = 0;
}
@ -399,19 +401,17 @@ WRITE8_MEMBER( rp5c15_device::write )
break;
default:
{
int mode = m_mode & MODE_MASK;
switch (mode)
switch (m_mode & MODE_MASK)
{
case MODE00:
m_reg[mode][offset & 0x0f] = data & REGISTER_WRITE_MASK[mode][offset & 0x0f];
m_reg[MODE00][offset] = data & register_write_mask[MODE00][offset];
set_time(false, read_counter(REGISTER_1_YEAR), read_counter(REGISTER_1_MONTH), read_counter(REGISTER_1_DAY), m_reg[MODE00][REGISTER_DAY_OF_THE_WEEK],
read_counter(REGISTER_1_HOUR), read_counter(REGISTER_1_MINUTE), read_counter(REGISTER_1_SECOND));
break;
case MODE01:
switch (offset & 0x0f)
switch (offset)
{
case REGISTER_CLOCK_OUTPUT:
switch (data & 0x07)
@ -447,26 +447,25 @@ WRITE8_MEMBER( rp5c15_device::write )
break;
}
m_reg[mode][offset & 0x0f] = data & REGISTER_WRITE_MASK[mode][offset & 0x0f];
m_reg[MODE01][offset] = data & register_write_mask[MODE01][offset];
break;
case REGISTER_ADJUST:
if (BIT(data, 0))
if (data & 0x01)
{
adjust_seconds();
}
m_reg[mode][offset & 0x0f] = data & REGISTER_WRITE_MASK[mode][offset & 0x0f];
m_reg[MODE01][offset] = data & register_write_mask[MODE01][offset];
break;
default:
m_reg[mode][offset & 0x0f] = data & REGISTER_WRITE_MASK[mode][offset & 0x0f];
m_reg[MODE01][offset] = data & register_write_mask[MODE01][offset];
break;
}
break;
}
if (LOG) logerror("RP5C15 '%s' Register %u Write %02x\n", tag(), offset & 0x0f, data);
if (LOG) logerror("RP5C15 '%s' Register %u Write %02x\n", tag(), offset, data);
break;
}
}
}