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first srcclean pass (nw)

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This commit is contained in:
Vas Crabb 2016-12-25 13:54:27 +11:00
parent ad50cf5fd4
commit 127fd9b427
132 changed files with 1464 additions and 1464 deletions
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20
hash/pcw.xml
View File

@ -1513,16 +1513,16 @@
</software>
<!--
<software name="sirlance">
<description>Sir Lancelot (Spa)</description>
<year>1985</year>
<publisher>OMK</publisher>
<part name="flop1" interface="floppy_3">
<dataarea name="flop" size="194816">
<rom name="sirlancelot_pcw.dsk" size="194816" crc="c47fb488" sha1="18d09cab70d50e0e9b2682ea751258fa47841120" offset="0" />
</dataarea>
</part>
</software>
<software name="sirlance">
<description>Sir Lancelot (Spa)</description>
<year>1985</year>
<publisher>OMK</publisher>
<part name="flop1" interface="floppy_3">
<dataarea name="flop" size="194816">
<rom name="sirlancelot_pcw.dsk" size="194816" crc="c47fb488" sha1="18d09cab70d50e0e9b2682ea751258fa47841120" offset="0" />
</dataarea>
</part>
</software>
-->
<software name="sirperce">

22
src/devices/bus/amiga/zorro/buddha.cpp
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@ -6,19 +6,19 @@
Zorro-II IDE controller
The 'speed' register is used to select the IDE timing according to
the following table (bits 7-5 are used):
The 'speed' register is used to select the IDE timing according to
the following table (bits 7-5 are used):
0 497ns 7c to select, IOR/IOW after 172ns 2c
1 639ns 9c to select, IOR/IOW after 243ns 3c
2 781ns 11c to select, IOR/IOW after 314ns 4c
3 355ns 5c to select, IOR/IOW after 101ns 1c
4 355ns 5c to select, IOR/IOW after 172ns 2c
5 355ns 5c to select, IOR/IOW after 243ns 3c
6 1065ns 15c to select, IOR/IOW after 314ns 4c
7 355ns 5c to select, IOR/IOW after 101ns 1c
0 497ns 7c to select, IOR/IOW after 172ns 2c
1 639ns 9c to select, IOR/IOW after 243ns 3c
2 781ns 11c to select, IOR/IOW after 314ns 4c
3 355ns 5c to select, IOR/IOW after 101ns 1c
4 355ns 5c to select, IOR/IOW after 172ns 2c
5 355ns 5c to select, IOR/IOW after 243ns 3c
6 1065ns 15c to select, IOR/IOW after 314ns 4c
7 355ns 5c to select, IOR/IOW after 101ns 1c
c = clock cycles. This isn't emulated.
c = clock cycles. This isn't emulated.
***************************************************************************/

6
src/devices/bus/apricot/keyboard/hle.cpp
View File

@ -5,9 +5,9 @@
ACT Apricot Keyboard (HLE)
TODO:
- MicroScreen emulation
- Mouse emulation
- LEDs
- MicroScreen emulation
- Mouse emulation
- LEDs
Keyboard to System:
- 01-60: Key make codes

2
src/devices/bus/coco/coco_t4426.cpp
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@ -71,7 +71,7 @@
#define UART_TAG "acia"
#define PIA_TAG "pia"
#define CARTSLOT_TAG "t4426"
#define CARTSLOT_TAG "t4426"
/***************************************************************************
IMPLEMENTATION

6
src/devices/cpu/i960/i960.cpp
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@ -106,7 +106,7 @@ uint32_t i960_cpu_device::get_ea(uint32_t opcode)
case 0x4:
return m_r[abase];
case 0x5: // address of this instruction + the offset dword + 8
case 0x5: // address of this instruction + the offset dword + 8
// which in reality is "address of next instruction + the offset dword"
ret = m_direct->read_dword(m_IP);
m_IP += 4;
@ -1129,7 +1129,7 @@ void i960_cpu_device::execute_op(uint32_t opcode)
case 0xc: // scanbyte
m_icount -= 2;
m_AC &= ~7; // clear CC
m_AC &= ~7; // clear CC
t1 = get_1_ri(opcode);
t2 = get_2_ri(opcode);
if ((t1 & 0xff000000) == (t2 & 0xff000000) ||
@ -1379,7 +1379,7 @@ void i960_cpu_device::execute_op(uint32_t opcode)
switch((opcode >> 7) & 0xf) {
case 0x0: // calls
t1 = get_1_ri(opcode);
t2 = m_program->read_dword(m_SAT + 152); // get pointer to system procedure table
t2 = m_program->read_dword(m_SAT + 152); // get pointer to system procedure table
t2 = m_program->read_dword(t2 + 48 + (t1 * 4));
if ((t2 & 3) != 0)
{

2
src/devices/cpu/m68000/m68kcpu.h
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@ -697,7 +697,7 @@ static inline uint32_t m68ki_ic_readimm16(m68000_base_device *m68k, uint32_t add
uint32_t data = m68k->read32(address & ~3);
//printf("m68k: doing cache fill at %08x (tag %08x idx %d)\n", address, tag, idx);
//printf("m68k: doing cache fill at %08x (tag %08x idx %d)\n", address, tag, idx);
// if no buserror occurred, validate the tag
if (!m68k->mmu_tmp_buserror_occurred)

2
src/devices/cpu/m68000/makefile
View File

@ -31,7 +31,7 @@ m68kmake$(EXE) : m68kmake.o
@echo Linking $@...
$(SILENT) $(CXX) -lstdc++ $^ -o $@
m68kops.cpp: m68kmake$(EXE) m68k_in.cpp
m68kops.cpp: m68kmake$(EXE) m68k_in.cpp
@echo Generating M68K source files...
$(SILENT) ./m68kmake$(EXE) . m68k_in.cpp

4
src/devices/cpu/m6805/m6805.h
View File

@ -438,9 +438,9 @@ protected:
// device-level overrides
virtual void device_start() override;
// virtual void execute_set_input(int inputnum, int state) override;
// virtual void execute_set_input(int inputnum, int state) override;
// virtual void interrupt() override;
// virtual void interrupt() override;
};
// ======================> hd63705_device

2
src/devices/cpu/mb86235/mb86235.cpp
View File

@ -17,7 +17,7 @@
#include "mb86235fe.h"
#define ENABLE_DRC 0
#define ENABLE_DRC 0
#define CACHE_SIZE (1 * 1024 * 1024)

26
src/devices/cpu/mb86235/mb86235.h
View File

@ -19,19 +19,19 @@ class mb86235_frontend;
#define OP_USERFLAG_FIFOIN 0x1
#define OP_USERFLAG_FIFOOUT0 0x2
#define OP_USERFLAG_FIFOOUT1 0x4
#define OP_USERFLAG_REPEAT 0x8
#define OP_USERFLAG_REPEATED_OP 0x10
#define OP_USERFLAG_PR_MASK 0x300
#define OP_USERFLAG_PR_INC 0x100
#define OP_USERFLAG_PR_DEC 0x200
#define OP_USERFLAG_PR_ZERO 0x300
#define OP_USERFLAG_PW_MASK 0xc00
#define OP_USERFLAG_PW_INC 0x400
#define OP_USERFLAG_PW_DEC 0x800
#define OP_USERFLAG_PW_ZERO 0xc00
#define OP_USERFLAG_FIFOIN 0x1
#define OP_USERFLAG_FIFOOUT0 0x2
#define OP_USERFLAG_FIFOOUT1 0x4
#define OP_USERFLAG_REPEAT 0x8
#define OP_USERFLAG_REPEATED_OP 0x10
#define OP_USERFLAG_PR_MASK 0x300
#define OP_USERFLAG_PR_INC 0x100
#define OP_USERFLAG_PR_DEC 0x200
#define OP_USERFLAG_PR_ZERO 0x300
#define OP_USERFLAG_PW_MASK 0xc00
#define OP_USERFLAG_PW_INC 0x400
#define OP_USERFLAG_PW_DEC 0x800
#define OP_USERFLAG_PW_ZERO 0xc00
class mb86235_device : public cpu_device

314
src/devices/cpu/mb86235/mb86235drc.cpp
View File

@ -16,8 +16,8 @@
#include "cpu/drcumlsh.h"
/*
TODO:
- check jump condition before parallel ALU/MUL (flags!)
TODO:
- check jump condition before parallel ALU/MUL (flags!)
*/
@ -38,55 +38,55 @@ using namespace uml;
#define EXECUTE_RESET_CACHE 3
#define AR(reg) mem(&m_core->ar[(reg)])
#define AA(reg) m_regmap[(reg)]
#define AB(reg) m_regmap[(reg)+8]
#define MA(reg) m_regmap[(reg)+16]
#define MB(reg) m_regmap[(reg)+24]
#define FLAGS_AZ mem(&m_core->flags.az)
#define FLAGS_AN mem(&m_core->flags.an)
#define FLAGS_AV mem(&m_core->flags.av)
#define FLAGS_AU mem(&m_core->flags.au)
#define FLAGS_AD mem(&m_core->flags.ad)
#define FLAGS_ZC mem(&m_core->flags.zc)
#define FLAGS_IL mem(&m_core->flags.il)
#define FLAGS_NR mem(&m_core->flags.nr)
#define FLAGS_ZD mem(&m_core->flags.zd)
#define FLAGS_MN mem(&m_core->flags.mn)
#define FLAGS_MZ mem(&m_core->flags.mz)
#define FLAGS_MV mem(&m_core->flags.mv)
#define FLAGS_MU mem(&m_core->flags.mu)
#define FLAGS_MD mem(&m_core->flags.md)
#define AR(reg) mem(&m_core->ar[(reg)])
#define AA(reg) m_regmap[(reg)]
#define AB(reg) m_regmap[(reg)+8]
#define MA(reg) m_regmap[(reg)+16]
#define MB(reg) m_regmap[(reg)+24]
#define FLAGS_AZ mem(&m_core->flags.az)
#define FLAGS_AN mem(&m_core->flags.an)
#define FLAGS_AV mem(&m_core->flags.av)
#define FLAGS_AU mem(&m_core->flags.au)
#define FLAGS_AD mem(&m_core->flags.ad)
#define FLAGS_ZC mem(&m_core->flags.zc)
#define FLAGS_IL mem(&m_core->flags.il)
#define FLAGS_NR mem(&m_core->flags.nr)
#define FLAGS_ZD mem(&m_core->flags.zd)
#define FLAGS_MN mem(&m_core->flags.mn)
#define FLAGS_MZ mem(&m_core->flags.mz)
#define FLAGS_MV mem(&m_core->flags.mv)
#define FLAGS_MU mem(&m_core->flags.mu)
#define FLAGS_MD mem(&m_core->flags.md)
#define PRP mem(&m_core->prp)
#define PWP mem(&m_core->pwp)
#define RPC mem(&m_core->rpc)
#define LPC mem(&m_core->lpc)
#define PRP mem(&m_core->prp)
#define PWP mem(&m_core->pwp)
#define RPC mem(&m_core->rpc)
#define LPC mem(&m_core->lpc)
#define AZ_CALC_REQUIRED ((desc->regreq[1] & 0x1) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define AN_CALC_REQUIRED ((desc->regreq[1] & 0x2) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define AV_CALC_REQUIRED ((desc->regreq[1] & 0x4) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define AU_CALC_REQUIRED ((desc->regreq[1] & 0x8) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define AD_CALC_REQUIRED ((desc->regreq[1] & 0x10) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define ZC_CALC_REQUIRED ((desc->regreq[1] & 0x20) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define IL_CALC_REQUIRED ((desc->regreq[1] & 0x40) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define NR_CALC_REQUIRED ((desc->regreq[1] & 0x80) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define ZD_CALC_REQUIRED ((desc->regreq[1] & 0x100) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define MN_CALC_REQUIRED ((desc->regreq[1] & 0x200) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define MZ_CALC_REQUIRED ((desc->regreq[1] & 0x400) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define MV_CALC_REQUIRED ((desc->regreq[1] & 0x800) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define MU_CALC_REQUIRED ((desc->regreq[1] & 0x1000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define MD_CALC_REQUIRED ((desc->regreq[1] & 0x2000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define AZ_CALC_REQUIRED ((desc->regreq[1] & 0x1) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define AN_CALC_REQUIRED ((desc->regreq[1] & 0x2) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define AV_CALC_REQUIRED ((desc->regreq[1] & 0x4) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define AU_CALC_REQUIRED ((desc->regreq[1] & 0x8) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define AD_CALC_REQUIRED ((desc->regreq[1] & 0x10) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define ZC_CALC_REQUIRED ((desc->regreq[1] & 0x20) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define IL_CALC_REQUIRED ((desc->regreq[1] & 0x40) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define NR_CALC_REQUIRED ((desc->regreq[1] & 0x80) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define ZD_CALC_REQUIRED ((desc->regreq[1] & 0x100) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define MN_CALC_REQUIRED ((desc->regreq[1] & 0x200) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define MZ_CALC_REQUIRED ((desc->regreq[1] & 0x400) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define MV_CALC_REQUIRED ((desc->regreq[1] & 0x800) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define MU_CALC_REQUIRED ((desc->regreq[1] & 0x1000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define MD_CALC_REQUIRED ((desc->regreq[1] & 0x2000) || desc->flags & OPFLAG_IN_DELAY_SLOT)
#define FIFOIN_RPOS mem(&m_core->fifoin.rpos)
#define FIFOIN_WPOS mem(&m_core->fifoin.wpos)
#define FIFOIN_NUM mem(&m_core->fifoin.num)
#define FIFOOUT0_RPOS mem(&m_core->fifoout0.rpos)
#define FIFOOUT0_WPOS mem(&m_core->fifoout0.wpos)
#define FIFOOUT0_NUM mem(&m_core->fifoout0.num)
#define FIFOOUT1_RPOS mem(&m_core->fifoout1.rpos)
#define FIFOOUT1_WPOS mem(&m_core->fifoout1.wpos)
#define FIFOOUT1_NUM mem(&m_core->fifoout1.num)
#define FIFOIN_RPOS mem(&m_core->fifoin.rpos)
#define FIFOIN_WPOS mem(&m_core->fifoin.wpos)
#define FIFOIN_NUM mem(&m_core->fifoin.num)
#define FIFOOUT0_RPOS mem(&m_core->fifoout0.rpos)
#define FIFOOUT0_WPOS mem(&m_core->fifoout0.wpos)
#define FIFOOUT0_NUM mem(&m_core->fifoout0.num)
#define FIFOOUT1_RPOS mem(&m_core->fifoout1.rpos)
#define FIFOOUT1_WPOS mem(&m_core->fifoout1.wpos)
#define FIFOOUT1_NUM mem(&m_core->fifoout1.num)
inline void mb86235_device::alloc_handle(drcuml_state *drcuml, code_handle **handleptr, const char *name)
@ -631,17 +631,17 @@ void mb86235_device::generate_ea(drcuml_block *block, compiler_state *compiler,
switch (md)
{
case 0x0: // @ARx
case 0x0: // @ARx
UML_MOV(block, I0, AR(arx));
break;
case 0x1: // @ARx++
case 0x1: // @ARx++
UML_MOV(block, I0, AR(arx));
UML_ADD(block, AR(arx), AR(arx), 1);
break;
case 0x4: // @ARx+ARy
case 0x4: // @ARx+ARy
UML_ADD(block, I0, AR(arx), AR(ary));
break;
case 0xa: // @ARx+disp12
case 0xa: // @ARx+disp12
UML_ADD(block, I0, AR(arx), disp);
break;
@ -672,11 +672,11 @@ void mb86235_device::generate_reg_read(drcuml_block *block, compiler_state *comp
UML_MOV(block, dst, AB(reg & 7));
break;
case 0x30: // PR
case 0x30: // PR
UML_LOAD(block, dst, m_core->pr, PRP, SIZE_DWORD, SCALE_x4);
break;
case 0x31: // FI
case 0x31: // FI
UML_CALLH(block, *m_read_fifo_in);
UML_MOV(block, dst, I0);
break;
@ -702,15 +702,15 @@ void mb86235_device::generate_reg_write(drcuml_block *block, compiler_state *com
UML_MOV(block, AA(reg & 7), src);
break;
case 0x10: // EB
case 0x10: // EB
UML_MOV(block, mem(&m_core->eb), src);
break;
case 0x13: // EO
case 0x13: // EO
UML_MOV(block, mem(&m_core->eo), src);
break;
case 0x14: // SP
case 0x14: // SP
UML_MOV(block, mem(&m_core->sp), src);
break;
@ -729,28 +729,28 @@ void mb86235_device::generate_reg_write(drcuml_block *block, compiler_state *com
UML_MOV(block, AB(reg & 7), src);
break;
case 0x30: // PR
case 0x30: // PR
UML_STORE(block, m_core->pr, PWP, src, SIZE_DWORD, SCALE_x4);
break;
case 0x32: // FO0
case 0x32: // FO0
UML_MOV(block, I0, src);
UML_CALLH(block, *m_write_fifo_out0);
break;
case 0x34: // PDR
case 0x34: // PDR
UML_MOV(block, mem(&m_core->pdr), src);
break;
case 0x35: // DDR
case 0x35: // DDR
UML_MOV(block, mem(&m_core->ddr), src);
break;
case 0x36: // PRP
case 0x36: // PRP
UML_MOV(block, PRP, src);
break;
case 0x37: // PWP
case 0x37: // PWP
UML_MOV(block, PWP, src);
break;
@ -788,9 +788,9 @@ bool mb86235_device::aluop_has_result(int aluop)
{
switch (aluop)
{
case 0x04: // FCMP
case 0x07: // NOP
case 0x14: // CMP
case 0x04: // FCMP
case 0x07: // NOP
case 0x14: // CMP
return false;
default:
@ -979,17 +979,17 @@ bool mb86235_device::generate_opcode(drcuml_block *block, compiler_state *compil
{
switch ((desc->userflags & OP_USERFLAG_PR_MASK) >> 8)
{
case 1: // PR++
case 1: // PR++
UML_ADD(block, PRP, PRP, 1);
UML_CMP(block, PRP, 24);
UML_MOVc(block, COND_GE, PRP, 0);
break;
case 2: // PR--
case 2: // PR--
UML_SUB(block, PRP, PRP, 1);
UML_CMP(block, PRP, 0);
UML_MOVc(block, COND_L, PRP, 23);
break;
case 3: // PR#0
case 3: // PR#0
UML_MOV(block, PRP, 0);
break;
}
@ -999,17 +999,17 @@ bool mb86235_device::generate_opcode(drcuml_block *block, compiler_state *compil
{
switch ((desc->userflags & OP_USERFLAG_PW_MASK) >> 10)
{
case 1: // PW++
case 1: // PW++
UML_ADD(block, PWP, PWP, 1);
UML_CMP(block, PWP, 24);
UML_MOVc(block, COND_GE, PWP, 0);
break;
case 2: // PW--
case 2: // PW--
UML_SUB(block, PWP, PWP, 1);
UML_CMP(block, PWP, 0);
UML_MOVc(block, COND_L, PWP, 23);
break;
case 3: // PW#0
case 3: // PW#0
UML_MOV(block, PWP, 0);
break;
}
@ -1055,51 +1055,51 @@ void mb86235_device::generate_alumul_input(drcuml_block *block, compiler_state *
UML_MOV(block, dst, AB(reg & 7));
break;
case 0x10: // PR
case 0x11: // PR++
case 0x12: // PR--
case 0x13: // PR#0
case 0x10: // PR
case 0x11: // PR++
case 0x12: // PR--
case 0x13: // PR#0
UML_LOAD(block, dst, m_core->pr, PRP, SIZE_DWORD, SCALE_x4);
break;
case 0x18: // 0 / -1.0E+0
case 0x18: // 0 / -1.0E+0
if (fp)
UML_MOV(block, dst, 0xbf800000);
else
UML_MOV(block, dst, 0);
break;
case 0x19: // 1 / 0.0E+0
case 0x19: // 1 / 0.0E+0
if (fp)
UML_MOV(block, dst, 0);
else
UML_MOV(block, dst, 1);
break;
case 0x1a: // -1 / 0.5+0
case 0x1a: // -1 / 0.5+0
if (fp)
UML_MOV(block, dst, 0x3f000000);
else
UML_MOV(block, dst, -1);
break;
case 0x1b: // 1.0E+0
case 0x1b: // 1.0E+0
UML_MOV(block, dst, 0x3f800000);
break;
case 0x1c: // 1.5E+0
case 0x1c: // 1.5E+0
UML_MOV(block, dst, 0x3fc00000);
break;
case 0x1d: // 2.0E+0
case 0x1d: // 2.0E+0
UML_MOV(block, dst, 0x40000000);
break;
case 0x1e: // 3.0E+0
case 0x1e: // 3.0E+0
UML_MOV(block, dst, 0x40400000);
break;
case 0x1f: // 5.0E+0
case 0x1f: // 5.0E+0
UML_MOV(block, dst, 0x40a00000);
break;
@ -1161,7 +1161,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
switch (op)
{
case 0x00: // FADD
case 0x00: // FADD
generate_alumul_input(block, compiler, desc, i2, I0, true, false);
UML_FSCOPYI(block, F0, I0);
UML_FSCOPYI(block, F1, get_alu1_input(i1));
@ -1176,7 +1176,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
// TODO: AD flag
break;
case 0x02: // FSUB
case 0x02: // FSUB
generate_alumul_input(block, compiler, desc, i2, I0, true, false);
UML_FSCOPYI(block, F0, I0);
UML_FSCOPYI(block, F1, get_alu1_input(i1));
@ -1191,7 +1191,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
// TODO: AD flag
break;
case 0x04: // FCMP
case 0x04: // FCMP
generate_alumul_input(block, compiler, desc, i2, I0, true, false);
UML_FSCOPYI(block, F0, I0);
UML_FSCOPYI(block, F1, get_alu1_input(i1));
@ -1203,14 +1203,14 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
// TODO: AD flag
break;
case 0x05: // FABS
case 0x05: // FABS
UML_AND(block, alutemp ? mem(&m_core->alutemp) : get_alu_output(io), get_alu1_input(i1), 0x7fffffff);
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, FLAGS_AZ);
if (AN_CALC_REQUIRED) UML_MOV(block, FLAGS_AN, 0);
// TODO: AD flag
break;
case 0x06: // FABC
case 0x06: // FABC
generate_alumul_input(block, compiler, desc, i2, I0, true, false);
UML_AND(block, I0, I0, 0x7fffffff);
UML_AND(block, I1, get_alu1_input(i1), 0x7fffffff);
@ -1223,10 +1223,10 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
// TODO: AD flag
break;
case 0x07: // NOP
case 0x07: // NOP
break;
case 0x0d: // CIF
case 0x0d: // CIF
generate_alumul_input(block, compiler, desc, i1, I1, true, false);
UML_FSFRINT(block, F0, I1, SIZE_DWORD);
if (AZ_CALC_REQUIRED || AN_CALC_REQUIRED)
@ -1236,7 +1236,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
UML_ICOPYFS(block, alutemp ? mem(&m_core->alutemp) : get_alu_output(io), F0);
break;
case 0x0e: // CFI
case 0x0e: // CFI
{
code_label truncate = compiler->labelnum++;
code_label end = compiler->labelnum++;
@ -1263,7 +1263,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
break;
}
case 0x10: // ADD
case 0x10: // ADD
generate_alumul_input(block, compiler, desc, i2, I1, false, false);
UML_ADD(block, I0, I1, get_alu1_input(i1));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, FLAGS_AZ);
@ -1277,7 +1277,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
UML_MOV(block, alutemp ? mem(&m_core->alutemp) : get_alu_output(io), I0);
break;
case 0x12: // SUB
case 0x12: // SUB
generate_alumul_input(block, compiler, desc, i2, I1, false, false);
UML_SUB(block, I0, I1, get_alu1_input(i1));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, FLAGS_AZ);
@ -1291,7 +1291,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
UML_MOV(block, alutemp ? mem(&m_core->alutemp) : get_alu_output(io), I0);
break;
case 0x14: // CMP
case 0x14: // CMP
generate_alumul_input(block, compiler, desc, i2, I1, false, false);
UML_SUB(block, I0, I1, get_alu1_input(i1));
if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, FLAGS_AZ);
@ -1305,11 +1305,11 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
}
break;
case 0x16: // ATR
case 0x16: // ATR
UML_MOV(block, alutemp ? mem(&m_core->alutemp) : get_alu_output(io), get_alu1_input(i1));
break;
case 0x18: // AND
case 0x18: // AND
generate_alumul_input(block, compiler, desc, i2, I0, false, false);
UML_AND(block, alutemp ? mem(&m_core->alutemp) : get_alu_output(io), I0, get_alu1_input(i1));
if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, FLAGS_AN);
@ -1318,7 +1318,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
if (AU_CALC_REQUIRED) UML_MOV(block, FLAGS_AU, 0);
break;
case 0x1c: // LSR
case 0x1c: // LSR
generate_alumul_input(block, compiler, desc, i1, I0, false, false);
UML_SHR(block, I0, I0, i2);
if (AZ_CALC_REQUIRED || AN_CALC_REQUIRED)
@ -1330,7 +1330,7 @@ void mb86235_device::generate_alu(drcuml_block *block, compiler_state *compiler,
UML_MOV(block, alutemp ? mem(&m_core->alutemp) : get_alu_output(io), I0);
break;
case 0x1d: // LSL
case 0x1d: // LSL
generate_alumul_input(block, compiler, desc, i1, I0, false, false);
UML_SHL(block, I0, I0, i2);
if (AZ_CALC_REQUIRED || AN_CALC_REQUIRED)
@ -1438,13 +1438,13 @@ void mb86235_device::generate_branch_target(drcuml_block *block, compiler_state
{
case 0x0: break;
case 0x1: break;
case 0x2: // ARx
case 0x2: // ARx
{
int reg = (ef2 >> 6) & 7;
UML_MOV(block, I0, AR(reg));
break;
}
case 0x4: // Axx
case 0x4: // Axx
{
int reg = (ef2 >> 6) & 7;
if (ef2 & 0x400)
@ -1464,59 +1464,59 @@ void mb86235_device::generate_condition(drcuml_block *block, compiler_state *com
{
switch (cc)
{
case 0x00: // MN
case 0x00: // MN
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_MN, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
case 0x01: // MZ
case 0x01: // MZ
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_MZ, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
case 0x02: // MV
case 0x02: // MV
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_MV, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
case 0x03: // MU
case 0x03: // MU
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_MU, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
case 0x04: // ZD
case 0x04: // ZD
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_ZD, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
case 0x05: // NR
case 0x05: // NR
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_NR, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
case 0x06: // IL
case 0x06: // IL
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_IL, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
case 0x07: // ZC
case 0x07: // ZC
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_ZC, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
case 0x08: // AN
case 0x08: // AN
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_AN, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
case 0x09: // AZ
case 0x09: // AZ
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_AZ, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
case 0x0a: // AV
case 0x0a: // AV
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_AV, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
case 0x0b: // AU
case 0x0b: // AU
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_AU, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
case 0x0c: // MD
case 0x0c: // MD
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_MD, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
case 0x0d: // AD
case 0x0d: // AD
UML_CMP(block, condtemp ? mem(&m_core->condtemp) : FLAGS_AD, 0);
UML_JMPc(block, n ? COND_NE : COND_E, skip_label);
break;
@ -1533,22 +1533,22 @@ void mb86235_device::generate_control(drcuml_block *block, compiler_state *compi
int ef1 = (op >> 16) & 0x3f;
int ef2 = op & 0xffff;
int cop = (op >> 22) & 0x1f;
// int rel12 = (op & 0x800) ? (0xfffff000 | (op & 0xfff)) : (op & 0xfff);
// int rel12 = (op & 0x800) ? (0xfffff000 | (op & 0xfff)) : (op & 0xfff);
switch (cop)
{
case 0x00: // NOP
case 0x00: // NOP
break;
case 0x03: //
if (ef1 == 1) // CLRFI
case 0x03: //
if (ef1 == 1) // CLRFI
UML_CALLH(block, *m_clear_fifo_in);
else if (ef1 == 2) // CLRFO
else if (ef1 == 2) // CLRFO
{
UML_CALLH(block, *m_clear_fifo_out0);
UML_CALLH(block, *m_clear_fifo_out1);
}
else if (ef1 == 3) // CLRF
else if (ef1 == 3) // CLRF
{
UML_CALLH(block, *m_clear_fifo_in);
UML_CALLH(block, *m_clear_fifo_out0);
@ -1556,11 +1556,11 @@ void mb86235_device::generate_control(drcuml_block *block, compiler_state *compi
}
break;
case 0x08: // SETM #imm16
case 0x08: // SETM #imm16
UML_MOV(block, mem(&m_core->mod), ef2);
break;
case 0x10: // DBcc
case 0x10: // DBcc
{
code_label skip_label = compiler->labelnum++;
@ -1571,7 +1571,7 @@ void mb86235_device::generate_control(drcuml_block *block, compiler_state *compi
break;
}
case 0x11: // DBNcc
case 0x11: // DBNcc
{
code_label skip_label = compiler->labelnum++;
@ -1582,14 +1582,14 @@ void mb86235_device::generate_control(drcuml_block *block, compiler_state *compi
break;
}
case 0x12: // DJMP
case 0x12: // DJMP
{
generate_branch_target(block, compiler, desc, (op >> 12) & 0xf, ef2);
generate_branch(block, compiler, desc);
break;
}
case 0x1a: // DCALL
case 0x1a: // DCALL
{
// push PC
code_label no_overflow = compiler->labelnum++;
@ -1607,7 +1607,7 @@ void mb86235_device::generate_control(drcuml_block *block, compiler_state *compi
break;
}
case 0x1b: // DRET
case 0x1b: // DRET
{
// pop PC
code_label no_underflow = compiler->labelnum++;
@ -1642,7 +1642,7 @@ void mb86235_device::generate_xfer1(drcuml_block *block, compiler_state *compile
int ary = (opcode >> 4) & 7;
int disp5 = (opcode >> 7) & 0x1f;
int trm = (opcode >> 26) & 1;
// int dir = (opcode >> 25) & 1;
// int dir = (opcode >> 25) & 1;
if (trm == 0)
{
@ -1660,7 +1660,7 @@ void mb86235_device::generate_xfer1(drcuml_block *block, compiler_state *compile
else
{
generate_ea(block, compiler, desc, md, sr & 7, ary, disp5);
if (sr & 0x20) // RAM-B
if (sr & 0x20) // RAM-B
{
UML_SHL(block, I0, I0, 2);
UML_READ(block, I1, I0, SIZE_DWORD, SPACE_IO);
@ -1678,7 +1678,7 @@ void mb86235_device::generate_xfer1(drcuml_block *block, compiler_state *compile
else
{
generate_ea(block, compiler, desc, md, dr & 7, ary, disp5);
if (dr & 0x20) // RAM-B
if (dr & 0x20) // RAM-B
{
UML_SHL(block, I0, I0, 2);
UML_WRITE(block, I0, I1, SIZE_DWORD, SPACE_IO);
@ -1719,7 +1719,7 @@ void mb86235_device::generate_xfer2(drcuml_block *block, compiler_state *compile
int disp14 = (opcode >> 7) & 0x3fff;
if (disp14 & 0x2000) disp14 |= 0xffffc000;
if (op == 0) // MOV2
if (op == 0) // MOV2
{
if (trm == 0)
{
@ -1737,7 +1737,7 @@ void mb86235_device::generate_xfer2(drcuml_block *block, compiler_state *compile
else
{
generate_ea(block, compiler, desc, md, sr & 7, ary, disp14);
if (sr & 0x20) // RAM-B
if (sr & 0x20) // RAM-B
{
UML_SHL(block, I0, I0, 2);
UML_READ(block, I1, I0, SIZE_DWORD, SPACE_IO);
@ -1755,7 +1755,7 @@ void mb86235_device::generate_xfer2(drcuml_block *block, compiler_state *compile
else
{
generate_ea(block, compiler, desc, md, dr & 7, ary, disp14);
if (dr & 0x20) // RAM-B
if (dr & 0x20) // RAM-B
{
UML_SHL(block, I0, I0, 2);
UML_WRITE(block, I0, I1, SIZE_DWORD, SPACE_IO);
@ -1791,7 +1791,7 @@ void mb86235_device::generate_xfer2(drcuml_block *block, compiler_state *compile
UML_ADD(block, mem(&m_core->eo), mem(&m_core->eo), disp14);
}
}
else if (op == 2) // MOV4
else if (op == 2) // MOV4
{
fatalerror("generate_xfer2 MOV4 at %08X (%08X%08X)", desc->pc, (uint32_t)(opcode >> 32), (uint32_t)(opcode));
}
@ -1819,17 +1819,17 @@ void mb86235_device::generate_xfer3(drcuml_block *block, compiler_state *compile
switch (dr >> 5)
{
case 0:
case 1: // reg
case 1: // reg
generate_reg_write(block, compiler, desc, dr & 0x3f, uml::parameter(imm));
break;
case 2: // RAM-A
case 2: // RAM-A
generate_ea(block, compiler, desc, md, dr & 7, ary, disp);
UML_MOV(block, I1, imm);
UML_CALLH(block, *m_write_abus);
break;
case 3: // RAM-B
case 3: // RAM-B
generate_ea(block, compiler, desc, md, dr & 7, ary, disp);
UML_SHL(block, I0, I0, 2);
UML_WRITE(block, I0, imm, SIZE_DWORD, SPACE_IO);
@ -1847,38 +1847,38 @@ void mb86235_device::generate_pre_control(drcuml_block *block, compiler_state *c
switch (cop)
{
case 0x10: // DBcc
case 0x11: // DBNcc
case 0x18: // DCcc
case 0x19: // DCNcc
case 0x10: // DBcc
case 0x11: // DBNcc
case 0x18: // DCcc
case 0x19: // DCNcc
switch (ef1)
{
case 0x00: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MN); break; // MN
case 0x01: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MZ); break; // MZ
case 0x02: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MV); break; // MV
case 0x03: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MU); break; // MU
case 0x04: UML_MOV(block, mem(&m_core->condtemp), FLAGS_ZD); break; // ZD
case 0x05: UML_MOV(block, mem(&m_core->condtemp), FLAGS_NR); break; // NR
case 0x06: UML_MOV(block, mem(&m_core->condtemp), FLAGS_IL); break; // IL
case 0x07: UML_MOV(block, mem(&m_core->condtemp), FLAGS_ZC); break; // ZC
case 0x08: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AN); break; // AN
case 0x09: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AZ); break; // AZ
case 0x0a: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AV); break; // AV
case 0x0b: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AU); break; // AU
case 0x0c: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MD); break; // MD
case 0x0d: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AD); break; // AD
case 0x00: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MN); break; // MN
case 0x01: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MZ); break; // MZ
case 0x02: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MV); break; // MV
case 0x03: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MU); break; // MU
case 0x04: UML_MOV(block, mem(&m_core->condtemp), FLAGS_ZD); break; // ZD
case 0x05: UML_MOV(block, mem(&m_core->condtemp), FLAGS_NR); break; // NR
case 0x06: UML_MOV(block, mem(&m_core->condtemp), FLAGS_IL); break; // IL
case 0x07: UML_MOV(block, mem(&m_core->condtemp), FLAGS_ZC); break; // ZC
case 0x08: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AN); break; // AN
case 0x09: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AZ); break; // AZ
case 0x0a: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AV); break; // AV
case 0x0b: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AU); break; // AU
case 0x0c: UML_MOV(block, mem(&m_core->condtemp), FLAGS_MD); break; // MD
case 0x0d: UML_MOV(block, mem(&m_core->condtemp), FLAGS_AD); break; // AD
default:
fatalerror("generate_pre_control: unimplemented cc %02X at %08X", ef1, desc->pc);
break;
}
break;
case 0x14: // DBBC ARx:y, rel12
case 0x14: // DBBC ARx:y, rel12
// TODO: copy ARx
UML_MOV(block, mem(&m_core->condtemp), AR((ef2 >> 13) & 7));
break;
case 0x15: // DBBS ARx:y, rel12
case 0x15: // DBBS ARx:y, rel12
// TODO: copy ARx
UML_MOV(block, mem(&m_core->condtemp), AR((ef2 >> 13) & 7));
break;

308
src/devices/cpu/mb86235/mb86235fe.cpp
View File

@ -11,45 +11,45 @@
#include "mb86235fe.h"
#define AA_USED(desc,x) do { (desc).regin[0] |= 1 << (x); } while(0)
#define AA_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (x); } while(0)
#define AB_USED(desc,x) do { (desc).regin[0] |= 1 << (8+(x)); } while(0)
#define AB_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (8+(x)); } while(0)
#define MA_USED(desc,x) do { (desc).regin[0] |= 1 << (16+(x)); } while(0)
#define MA_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (16+(x)); } while(0)
#define MB_USED(desc,x) do { (desc).regin[0] |= 1 << (24+(x)); } while(0)
#define MB_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (24+(x)); } while(0)
#define AR_USED(desc,x) do { (desc).regin[1] |= 1 << (24+(x)); } while(0)
#define AR_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << (24+(x)); } while(0)
#define AA_USED(desc,x) do { (desc).regin[0] |= 1 << (x); } while(0)
#define AA_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (x); } while(0)
#define AB_USED(desc,x) do { (desc).regin[0] |= 1 << (8+(x)); } while(0)
#define AB_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (8+(x)); } while(0)
#define MA_USED(desc,x) do { (desc).regin[0] |= 1 << (16+(x)); } while(0)
#define MA_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (16+(x)); } while(0)
#define MB_USED(desc,x) do { (desc).regin[0] |= 1 << (24+(x)); } while(0)
#define MB_MODIFIED(desc,x) do { (desc).regout[0] |= 1 << (24+(x)); } while(0)
#define AR_USED(desc,x) do { (desc).regin[1] |= 1 << (24+(x)); } while(0)
#define AR_MODIFIED(desc,x) do { (desc).regout[1] |= 1 << (24+(x)); } while(0)
#define AZ_USED(desc) do { (desc).regin[1] |= 1 << 0; } while (0)
#define AZ_MODIFIED(desc) do { (desc).regout[1] |= 1 << 0; } while (0)
#define AN_USED(desc) do { (desc).regin[1] |= 1 << 1; } while (0)
#define AN_MODIFIED(desc) do { (desc).regout[1] |= 1 << 1; } while (0)
#define AV_USED(desc) do { (desc).regin[1] |= 1 << 2; } while (0)
#define AV_MODIFIED(desc) do { (desc).regout[1] |= 1 << 2; } while (0)
#define AU_USED(desc) do { (desc).regin[1] |= 1 << 3; } while (0)
#define AU_MODIFIED(desc) do { (desc).regout[1] |= 1 << 3; } while (0)
#define AD_USED(desc) do { (desc).regin[1] |= 1 << 4; } while (0)
#define AD_MODIFIED(desc) do { (desc).regout[1] |= 1 << 4; } while (0)
#define ZC_USED(desc) do { (desc).regin[1] |= 1 << 5; } while (0)
#define ZC_MODIFIED(desc) do { (desc).regout[1] |= 1 << 5; } while (0)
#define IL_USED(desc) do { (desc).regin[1] |= 1 << 6; } while (0)
#define IL_MODIFIED(desc) do { (desc).regout[1] |= 1 << 6; } while (0)
#define NR_USED(desc) do { (desc).regin[1] |= 1 << 7; } while (0)
#define NR_MODIFIED(desc) do { (desc).regout[1] |= 1 << 7; } while (0)
#define ZD_USED(desc) do { (desc).regin[1] |= 1 << 8; } while (0)
#define ZD_MODIFIED(desc) do { (desc).regout[1] |= 1 << 8; } while (0)
#define MN_USED(desc) do { (desc).regin[1] |= 1 << 9; } while (0)
#define MN_MODIFIED(desc) do { (desc).regout[1] |= 1 << 9; } while (0)
#define MZ_USED(desc) do { (desc).regin[1] |= 1 << 10; } while (0)
#define MZ_MODIFIED(desc) do { (desc).regout[1] |= 1 << 10; } while (0)
#define MV_USED(desc) do { (desc).regin[1] |= 1 << 11; } while (0)
#define MV_MODIFIED(desc) do { (desc).regout[1] |= 1 << 11; } while (0)
#define MU_USED(desc) do { (desc).regin[1] |= 1 << 12; } while (0)
#define MU_MODIFIED(desc) do { (desc).regout[1] |= 1 << 12; } while (0)
#define MD_USED(desc) do { (desc).regin[1] |= 1 << 13; } while (0)
#define MD_MODIFIED(desc) do { (desc).regout[1] |= 1 << 13; } while (0)
#define AZ_USED(desc) do { (desc).regin[1] |= 1 << 0; } while (0)
#define AZ_MODIFIED(desc) do { (desc).regout[1] |= 1 << 0; } while (0)
#define AN_USED(desc) do { (desc).regin[1] |= 1 << 1; } while (0)
#define AN_MODIFIED(desc) do { (desc).regout[1] |= 1 << 1; } while (0)
#define AV_USED(desc) do { (desc).regin[1] |= 1 << 2; } while (0)
#define AV_MODIFIED(desc) do { (desc).regout[1] |= 1 << 2; } while (0)
#define AU_USED(desc) do { (desc).regin[1] |= 1 << 3; } while (0)
#define AU_MODIFIED(desc) do { (desc).regout[1] |= 1 << 3; } while (0)
#define AD_USED(desc) do { (desc).regin[1] |= 1 << 4; } while (0)
#define AD_MODIFIED(desc) do { (desc).regout[1] |= 1 << 4; } while (0)
#define ZC_USED(desc) do { (desc).regin[1] |= 1 << 5; } while (0)
#define ZC_MODIFIED(desc) do { (desc).regout[1] |= 1 << 5; } while (0)
#define IL_USED(desc) do { (desc).regin[1] |= 1 << 6; } while (0)
#define IL_MODIFIED(desc) do { (desc).regout[1] |= 1 << 6; } while (0)
#define NR_USED(desc) do { (desc).regin[1] |= 1 << 7; } while (0)
#define NR_MODIFIED(desc) do { (desc).regout[1] |= 1 << 7; } while (0)
#define ZD_USED(desc) do { (desc).regin[1] |= 1 << 8; } while (0)
#define ZD_MODIFIED(desc) do { (desc).regout[1] |= 1 << 8; } while (0)
#define MN_USED(desc) do { (desc).regin[1] |= 1 << 9; } while (0)
#define MN_MODIFIED(desc) do { (desc).regout[1] |= 1 << 9; } while (0)
#define MZ_USED(desc) do { (desc).regin[1] |= 1 << 10; } while (0)
#define MZ_MODIFIED(desc) do { (desc).regout[1] |= 1 << 10; } while (0)
#define MV_USED(desc) do { (desc).regin[1] |= 1 << 11; } while (0)
#define MV_MODIFIED(desc) do { (desc).regout[1] |= 1 << 11; } while (0)
#define MU_USED(desc) do { (desc).regin[1] |= 1 << 12; } while (0)
#define MU_MODIFIED(desc) do { (desc).regout[1] |= 1 << 12; } while (0)
#define MD_USED(desc) do { (desc).regin[1] |= 1 << 13; } while (0)
#define MD_MODIFIED(desc) do { (desc).regout[1] |= 1 << 13; } while (0)
mb86235_frontend::mb86235_frontend(mb86235_device *core, uint32_t window_start, uint32_t window_end, uint32_t max_sequence)
@ -137,18 +137,18 @@ void mb86235_frontend::describe_alu_input(opcode_desc &desc, int reg)
AB_USED(desc, reg & 7);
break;
case 0x10: // PR
case 0x10: // PR
break;
case 0x11: // PR++
case 0x11: // PR++
desc.userflags &= ~OP_USERFLAG_PR_MASK;
desc.userflags |= OP_USERFLAG_PR_INC;
break;
case 0x12: // PR--
case 0x12: // PR--
desc.userflags &= ~OP_USERFLAG_PR_MASK;
desc.userflags |= OP_USERFLAG_PR_DEC;
break;
case 0x13: // PR#0
case 0x13: // PR#0
desc.userflags &= ~OP_USERFLAG_PR_MASK;
desc.userflags |= OP_USERFLAG_PR_ZERO;
break;
@ -171,23 +171,23 @@ void mb86235_frontend::describe_mul_input(opcode_desc &desc, int reg)
MB_USED(desc, reg & 7);
break;
case 0x10: // PR
case 0x10: // PR
break;
case 0x11: // PR++
if ((desc.userflags & OP_USERFLAG_PR_MASK) == 0) // ALU PR update has higher priority
case 0x11: // PR++
if ((desc.userflags & OP_USERFLAG_PR_MASK) == 0) // ALU PR update has higher priority
{
desc.userflags |= OP_USERFLAG_PR_INC;
}
break;
case 0x12: // PR--
if ((desc.userflags & OP_USERFLAG_PR_MASK) == 0) // ALU PR update has higher priority
case 0x12: // PR--
if ((desc.userflags & OP_USERFLAG_PR_MASK) == 0) // ALU PR update has higher priority
{
desc.userflags |= OP_USERFLAG_PR_DEC;
}
break;
case 0x13: // PR#0
if ((desc.userflags & OP_USERFLAG_PR_MASK) == 0) // ALU PR update has higher priority
case 0x13: // PR#0
if ((desc.userflags & OP_USERFLAG_PR_MASK) == 0) // ALU PR update has higher priority
{
desc.userflags |= OP_USERFLAG_PR_ZERO;
}
@ -248,31 +248,31 @@ void mb86235_frontend::describe_reg_read(opcode_desc &desc, int reg)
AB_USED(desc, reg & 7);
break;
case 0x31: // FI
case 0x31: // FI
desc.userflags |= OP_USERFLAG_FIFOIN;
desc.flags |= OPFLAG_IS_BRANCH_TARGET; // fifo check makes this a branch target
desc.flags |= OPFLAG_IS_BRANCH_TARGET; // fifo check makes this a branch target
break;
case 0x32: // FO0
case 0x32: // FO0
break;
case 0x33: // FO1
case 0x33: // FO1
break;
case 0x10: // EB
case 0x11: // EBU
case 0x12: // EBL
case 0x13: // EO
case 0x15: // ST
case 0x16: // MOD
case 0x17: // LRPC
case 0x34: // PDR
case 0x35: // DDR
case 0x36: // PRP
case 0x37: // PWP
case 0x10: // EB
case 0x11: // EBU
case 0x12: // EBL
case 0x13: // EO
case 0x15: // ST
case 0x16: // MOD
case 0x17: // LRPC
case 0x34: // PDR
case 0x35: // DDR
case 0x36: // PRP
case 0x37: // PWP
break;
case 0x30: // PR
if ((desc.userflags & OP_USERFLAG_PR_MASK) == 0) // ALU and MUL PR updates have higher priority
case 0x30: // PR
if ((desc.userflags & OP_USERFLAG_PR_MASK) == 0) // ALU and MUL PR updates have higher priority
{
desc.userflags |= OP_USERFLAG_PR_INC;
}
@ -305,32 +305,32 @@ void mb86235_frontend::describe_reg_write(opcode_desc &desc, int reg)
AB_MODIFIED(desc, reg & 7);
break;
case 0x31: // FI
case 0x31: // FI
break;
case 0x32: // FO0
case 0x32: // FO0
desc.userflags |= OP_USERFLAG_FIFOOUT0;
desc.flags |= OPFLAG_IS_BRANCH_TARGET; // fifo check makes this a branch target
desc.flags |= OPFLAG_IS_BRANCH_TARGET; // fifo check makes this a branch target
break;
case 0x33: // FO1
case 0x33: // FO1
desc.userflags |= OP_USERFLAG_FIFOOUT1;
desc.flags |= OPFLAG_IS_BRANCH_TARGET; // fifo check makes this a branch target
desc.flags |= OPFLAG_IS_BRANCH_TARGET; // fifo check makes this a branch target
break;
case 0x10: // EB
case 0x11: // EBU
case 0x12: // EBL
case 0x13: // EO
case 0x15: // ST
case 0x16: // MOD
case 0x17: // LRPC
case 0x34: // PDR
case 0x35: // DDR
case 0x36: // PRP
case 0x37: // PWP
case 0x10: // EB
case 0x11: // EBU
case 0x12: // EBL
case 0x13: // EO
case 0x15: // ST
case 0x16: // MOD
case 0x17: // LRPC
case 0x34: // PDR
case 0x35: // DDR
case 0x36: // PRP
case 0x37: // PWP
break;
case 0x30: // PR
case 0x30: // PR
desc.userflags &= ~OP_USERFLAG_PW_MASK;
desc.userflags |= OP_USERFLAG_PW_INC;
break;
@ -347,14 +347,14 @@ void mb86235_frontend::describe_alu(opcode_desc &desc, uint32_t aluop)
switch (op)
{
case 0x00: // FADD
case 0x00: // FADD
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AU_MODIFIED(desc);
break;
case 0x01: // FADDZ
case 0x01: // FADDZ
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
ZC_MODIFIED(desc);
AN_MODIFIED(desc);
@ -363,7 +363,7 @@ void mb86235_frontend::describe_alu(opcode_desc &desc, uint32_t aluop)
AU_MODIFIED(desc);
AD_MODIFIED(desc);
break;
case 0x02: // FSUB
case 0x02: // FSUB
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
@ -371,7 +371,7 @@ void mb86235_frontend::describe_alu(opcode_desc &desc, uint32_t aluop)
AU_MODIFIED(desc);
AD_MODIFIED(desc);
break;
case 0x03: // FSUBZ
case 0x03: // FSUBZ
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
ZC_MODIFIED(desc);
AN_MODIFIED(desc);
@ -380,7 +380,7 @@ void mb86235_frontend::describe_alu(opcode_desc &desc, uint32_t aluop)
AU_MODIFIED(desc);
AD_MODIFIED(desc);
break;
case 0x04: // FCMP
case 0x04: // FCMP
describe_alu_input(desc, i1); describe_alu_input(desc, i2);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
@ -388,36 +388,36 @@ void mb86235_frontend::describe_alu(opcode_desc &desc, uint32_t aluop)
AU_MODIFIED(desc);
AD_MODIFIED(desc);
break;
case 0x05: // FABS
case 0x05: // FABS
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AD_MODIFIED(desc);
break;
case 0x06: // FABC
case 0x06: // FABC
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AU_MODIFIED(desc);
AD_MODIFIED(desc);
break;
case 0x07: // NOP
case 0x07: // NOP
break;
case 0x08: // FEA
case 0x08: // FEA
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AD_MODIFIED(desc);
break;
case 0x09: // FES
case 0x09: // FES
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AU_MODIFIED(desc);
AD_MODIFIED(desc);
break;
case 0x0a: // FRCP
case 0x0a: // FRCP
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
ZD_MODIFIED(desc);
AN_MODIFIED(desc);
@ -425,7 +425,7 @@ void mb86235_frontend::describe_alu(opcode_desc &desc, uint32_t aluop)
AU_MODIFIED(desc);
AD_MODIFIED(desc);
break;
case 0x0b: // FRSQ
case 0x0b: // FRSQ
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
NR_MODIFIED(desc);
AN_MODIFIED(desc);
@ -433,26 +433,26 @@ void mb86235_frontend::describe_alu(opcode_desc &desc, uint32_t aluop)
AU_MODIFIED(desc);
AD_MODIFIED(desc);
break;
case 0x0c: // FLOG
case 0x0c: // FLOG
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
IL_MODIFIED(desc);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AD_MODIFIED(desc);
break;
case 0x0d: // CIF
case 0x0d: // CIF
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
break;
case 0x0e: // CFI
case 0x0e: // CFI
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AD_MODIFIED(desc);
break;
case 0x0f: // CFIB
case 0x0f: // CFIB
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
@ -460,99 +460,99 @@ void mb86235_frontend::describe_alu(opcode_desc &desc, uint32_t aluop)
AD_MODIFIED(desc);
AU_MODIFIED(desc);
break;
case 0x10: // ADD
case 0x10: // ADD
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
break;
case 0x11: // ADDZ
case 0x11: // ADDZ
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
ZC_MODIFIED(desc);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
break;
case 0x12: // SUB
case 0x12: // SUB
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
break;
case 0x13: // SUBZ
case 0x13: // SUBZ
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
ZC_MODIFIED(desc);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
break;
case 0x14: // CMP
case 0x14: // CMP
describe_alu_input(desc, i1); describe_alu_input(desc, i2);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
break;
case 0x15: // ABS
case 0x15: // ABS
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
break;
case 0x16: // ATR
case 0x16: // ATR
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
break;
case 0x17: // ATRZ
case 0x17: // ATRZ
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
ZC_MODIFIED(desc);
break;
case 0x18: // AND
case 0x18: // AND
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AU_MODIFIED(desc);
break;
case 0x19: // OR
case 0x19: // OR
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AU_MODIFIED(desc);
break;
case 0x1a: // XOR
case 0x1a: // XOR
describe_alu_input(desc, i1); describe_alu_input(desc, i2); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AU_MODIFIED(desc);
break;
case 0x1b: // NOT
case 0x1b: // NOT
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AU_MODIFIED(desc);
break;
case 0x1c: // LSR
case 0x1c: // LSR
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AU_MODIFIED(desc);
break;
case 0x1d: // LSL
case 0x1d: // LSL
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
AV_MODIFIED(desc);
AU_MODIFIED(desc);
break;
case 0x1e: // ASR
case 0x1e: // ASR
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
break;
case 0x1f: // ASL
case 0x1f: // ASL
describe_alu_input(desc, i1); describe_alumul_output(desc, io);
AN_MODIFIED(desc);
AZ_MODIFIED(desc);
@ -593,51 +593,51 @@ void mb86235_frontend::describe_ea(opcode_desc &desc, int md, int arx, int ary,
{
switch (md)
{
case 0x0: // @ARx
case 0x0: // @ARx
AR_USED(desc, arx);
break;
case 0x1: // @ARx++
case 0x1: // @ARx++
AR_USED(desc, arx); AR_MODIFIED(desc, arx);
break;
case 0x2: // @ARx--
case 0x2: // @ARx--
AR_USED(desc, arx); AR_MODIFIED(desc, arx);
break;
case 0x3: // @ARx++disp
case 0x3: // @ARx++disp
AR_USED(desc, arx); AR_MODIFIED(desc, arx);
break;
case 0x4: // @ARx+ARy
case 0x4: // @ARx+ARy
AR_USED(desc, arx); AR_USED(desc, ary);
break;
case 0x5: // @ARx+ARy++
case 0x5: // @ARx+ARy++
AR_USED(desc, arx); AR_USED(desc, ary); AR_MODIFIED(desc, ary);
break;
case 0x6: // @ARx+ARy--
case 0x6: // @ARx+ARy--
AR_USED(desc, arx); AR_USED(desc, ary); AR_MODIFIED(desc, ary);
break;
case 0x7: // @ARx+ARy++disp
case 0x7: // @ARx+ARy++disp
AR_USED(desc, arx); AR_USED(desc, ary); AR_MODIFIED(desc, ary);
break;
case 0x8: // @ARx+ARyU
case 0x8: // @ARx+ARyU
AR_USED(desc, arx); AR_USED(desc, ary);
break;
case 0x9: // @ARx+ARyL
case 0x9: // @ARx+ARyL
AR_USED(desc, arx); AR_USED(desc, ary);
break;
case 0xa: // @ARx+disp
case 0xa: // @ARx+disp
AR_USED(desc, arx);
break;
case 0xb: // @ARx+ARy+disp
case 0xb: // @ARx+ARy+disp
AR_USED(desc, arx); AR_USED(desc, ary);
break;
case 0xc: // @disp
case 0xc: // @disp
break;
case 0xd: // @ARx+[ARy++]
case 0xd: // @ARx+[ARy++]
AR_USED(desc, arx); AR_USED(desc, ary); AR_MODIFIED(desc, ary);
break;
case 0xe: // @ARx+[ARy--]
case 0xe: // @ARx+[ARy--]
AR_USED(desc, arx); AR_USED(desc, ary); AR_MODIFIED(desc, ary);
break;
case 0xf: // @ARx+[ARy++disp]
case 0xf: // @ARx+[ARy++disp]
AR_USED(desc, arx); AR_USED(desc, ary); AR_MODIFIED(desc, ary);
break;
}
@ -717,7 +717,7 @@ void mb86235_frontend::describe_xfer2(opcode_desc &desc)
int md = opcode & 0xf;
int disp14 = (opcode >> 7) & 0x3fff;
if (op == 0) // MOV2
if (op == 0) // MOV2
{
if (trm == 0)
{
@ -760,7 +760,7 @@ void mb86235_frontend::describe_xfer2(opcode_desc &desc)
}
}
}
else if (op == 2) // MOV4
else if (op == 2) // MOV4
{
fatalerror("mb86235_frontend: describe_xfer2 MOV4 at %08X (%08X%08X)", desc.pc, (uint32_t)(opcode >> 32), (uint32_t)(opcode));
}
@ -785,12 +785,12 @@ void mb86235_frontend::describe_xfer3(opcode_desc &desc)
switch (dr >> 5)
{
case 0:
case 1: // reg
case 1: // reg
describe_reg_write(desc, dr & 0x3f);
break;
case 2: // RAM-A
case 3: // RAM-B
case 2: // RAM-A
case 3: // RAM-B
desc.flags |= OPFLAG_WRITES_MEMORY;
describe_ea(desc, md, dr & 7, ary, disp);
break;
@ -806,56 +806,56 @@ void mb86235_frontend::describe_control(opcode_desc &desc)
switch (cop)
{
case 0x00: // NOP
case 0x00: // NOP
break;
case 0x01: // REP
if (ef1 != 0) // ARx
case 0x01: // REP
if (ef1 != 0) // ARx
AR_USED(desc, (ef2 >> 12) & 7);
desc.userflags |= OP_USERFLAG_REPEAT;
break;
case 0x02: // SETL
if (ef1 != 0) // ARx
case 0x02: // SETL
if (ef1 != 0) // ARx
AR_USED(desc, (ef2 >> 12) & 7);
break;
case 0x03: // CLRFI/CLRFO/CLRF
case 0x03: // CLRFI/CLRFO/CLRF
break;
case 0x04: // PUSH
case 0x04: // PUSH
describe_reg_read(desc, (ef2 >> 6) & 0x3f);
break;
case 0x05: // POP
case 0x05: // POP
describe_reg_write(desc, (ef2 >> 6) & 0x3f);
break;
case 0x08: // SETM #imm16
case 0x08: // SETM #imm16
break;
case 0x09: // SETM #imm3, CBSA
case 0x09: // SETM #imm3, CBSA
break;
case 0x0a: // SETM #imm3, CBSB
case 0x0a: // SETM #imm3, CBSB
break;
case 0x0b: // SETM #imm1, RF
case 0x0b: // SETM #imm1, RF
break;
case 0x0c: // SETM #imm1, RDY
case 0x0c: // SETM #imm1, RDY
break;
case 0x0d: // SETM #imm1, WAIT
case 0x0d: // SETM #imm1, WAIT
break;
case 0x13: // DBLP rel12
case 0x13: // DBLP rel12
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
desc.targetpc = desc.pc + rel12;
desc.delayslots = 1;
break;
case 0x14: // DBBC ARx:y, rel12
case 0x14: // DBBC ARx:y, rel12
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
desc.targetpc = desc.pc + rel12;
desc.delayslots = 1;
AR_USED(desc, ((desc.opptr.q[0] >> 13) & 7));
break;
case 0x15: // DBBS ARx:y, rel12
case 0x15: // DBBS ARx:y, rel12
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
desc.targetpc = desc.pc + rel12;
desc.delayslots = 1;
AR_USED(desc, ((desc.opptr.q[0] >> 13) & 7));
break;
case 0x1b: // DRET
case 0x1b: // DRET
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
desc.targetpc = BRANCH_TARGET_DYNAMIC;
desc.delayslots = 1;

12
src/devices/cpu/powerpc/ppcdrc.cpp
View File

@ -791,9 +791,9 @@ void ppc_device::static_generate_tlb_mismatch()
{
// DAR gets the address, DSISR gets the 'reason' flags
UML_MOV(block, SPR32(SPROEA_DAR), mem(&m_core->param0)); // mov [dar],[param0]
m_core->param1 = 0; // always a read here
UML_CALLC(block, (c_function)cfunc_ppccom_get_dsisr, this); // get DSISR to param1
UML_MOV(block, SPR32(SPROEA_DSISR), mem(&m_core->param1)); // move [dsisr], [param1]
m_core->param1 = 0; // always a read here
UML_CALLC(block, (c_function)cfunc_ppccom_get_dsisr, this); // get DSISR to param1
UML_MOV(block, SPR32(SPROEA_DSISR), mem(&m_core->param1)); // move [dsisr], [param1]
UML_EXH(block, *m_exception[EXCEPTION_ISI], I0); // exh isi,i0
}
else
@ -1408,9 +1408,9 @@ void ppc_device::static_generate_memory_accessor(int mode, int size, int iswrite
{
m_core->param1 = 0;
}
UML_CALLC(block, (c_function)cfunc_ppccom_get_dsisr, this); // get DSISR to param1
UML_MOV(block, SPR32(SPROEA_DSISR), mem(&m_core->param1)); // move [dsisr], [param1]
UML_EXH(block, *m_exception[EXCEPTION_DSI], I0); // exh dsi,i0
UML_CALLC(block, (c_function)cfunc_ppccom_get_dsisr, this); // get DSISR to param1
UML_MOV(block, SPR32(SPROEA_DSISR), mem(&m_core->param1)); // move [dsisr], [param1]
UML_EXH(block, *m_exception[EXCEPTION_DSI], I0); // exh dsi,i0
}
}

2
src/devices/machine/68230pit.cpp
View File

@ -241,7 +241,7 @@ void pit68230_device::trigger_interrupt(int source)
void pit68230_device::tick_clock()
{
if (m_tcr & REG_TCR_TIMER_ENABLE)
{
{
if (m_cntr-- == 0) // Zero detect
{
LOGINT(("Timer reached zero!\n"));

90
src/devices/machine/68230pit.h
View File

@ -216,61 +216,61 @@ class pit68230_device : public device_t//, public device_execute_interface
protected:
enum { // PGCR - Port Global Control register
REG_PGCR_MODE_MASK = 0xc0,
REG_PGCR_MODE_0 = 0x00, // 0 0 Unidirectional 8 bit mode
REG_PGCR_MODE_1 = 0x40, // 0 1 Unidirectional 16 bit mode
REG_PGCR_MODE_2 = 0x80, // 1 0 Bidirectional 8 bit mode
REG_PGCR_MODE_3 = 0xc0, // 1 1 Bidirectional 16 bit mode
REG_PGCR_H34_ENABLE = 0x20,
REG_PGCR_H12_ENABLE = 0x10,
REG_PGCR_H4_SENSE = 0x80,
REG_PGCR_H3_SENSE = 0x40,
REG_PGCR_H2_SENSE = 0x20,
REG_PGCR_H1_SENSE = 0x10,
REG_PGCR_MODE_MASK = 0xc0,
REG_PGCR_MODE_0 = 0x00, // 0 0 Unidirectional 8 bit mode
REG_PGCR_MODE_1 = 0x40, // 0 1 Unidirectional 16 bit mode
REG_PGCR_MODE_2 = 0x80, // 1 0 Bidirectional 8 bit mode
REG_PGCR_MODE_3 = 0xc0, // 1 1 Bidirectional 16 bit mode
REG_PGCR_H34_ENABLE = 0x20,
REG_PGCR_H12_ENABLE = 0x10,
REG_PGCR_H4_SENSE = 0x80,
REG_PGCR_H3_SENSE = 0x40,
REG_PGCR_H2_SENSE = 0x20,
REG_PGCR_H1_SENSE = 0x10,
};
enum {
REG_PACR_SUBMODE_MASK = 0xc0,
REG_PACR_SUBMODE_0 = 0x00, // 0 0
REG_PACR_SUBMODE_1 = 0x40, // 0 1
REG_PACR_SUBMODE_2 = 0x80, // 1 0
REG_PACR_SUBMODE_3 = 0xc0, // 1 1
REG_PACR_H2_CTRL_MASK = 0x38,
REG_PACR_H2_CTRL_IN_OUT = 0x20, // H2 sense always cleared if set
REG_PACR_H2_CTRL_OUT_00 = 0x20, // H2 output negated
REG_PACR_H2_CTRL_OUT_01 = 0x28, // H2 output asserted
REG_PACR_H2_CTRL_OUT_10 = 0x30, // H2 output in interlocked input handshake protocol
REG_PACR_H2_CTRL_OUT_11 = 0x38, // H2 output in pulsed input handshake protocol
REG_PACR_H2_INT_ENABLE = 0x04,
REG_PACR_H1_SVCR_ENABLE = 0x02,
REG_PACR_H1_STATUS_CTRL = 0x01,
REG_PACR_SUBMODE_MASK = 0xc0,
REG_PACR_SUBMODE_0 = 0x00, // 0 0
REG_PACR_SUBMODE_1 = 0x40, // 0 1
REG_PACR_SUBMODE_2 = 0x80, // 1 0
REG_PACR_SUBMODE_3 = 0xc0, // 1 1
REG_PACR_H2_CTRL_MASK = 0x38,
REG_PACR_H2_CTRL_IN_OUT = 0x20, // H2 sense always cleared if set
REG_PACR_H2_CTRL_OUT_00 = 0x20, // H2 output negated
REG_PACR_H2_CTRL_OUT_01 = 0x28, // H2 output asserted
REG_PACR_H2_CTRL_OUT_10 = 0x30, // H2 output in interlocked input handshake protocol
REG_PACR_H2_CTRL_OUT_11 = 0x38, // H2 output in pulsed input handshake protocol
REG_PACR_H2_INT_ENABLE = 0x04,
REG_PACR_H1_SVCR_ENABLE = 0x02,
REG_PACR_H1_STATUS_CTRL = 0x01,
};
enum {
REG_PBCR_SUBMODE_MASK = 0xc0,
REG_PBCR_SUBMODE_00 = 0x00, // 0 0
REG_PBCR_SUBMODE_01 = 0x40, // 0 1
REG_PBCR_SUBMODE_10 = 0x80, // 1 0
REG_PBCR_SUBMODE_11 = 0xc0, // 1 1
REG_PBCR_SUBMODE_1X = 0x80, // submode 2 or 3
REG_PBCR_H4_CTRL_MASK = 0x38,
REG_PBCR_H4_CTRL_IN_OUT = 0x20, // H4 sense always cleared if set
REG_PBCR_H4_CTRL_OUT_00 = 0x20, // H4 output negated
REG_PBCR_H4_CTRL_OUT_01 = 0x28, // H4 output asserted
REG_PBCR_H4_CTRL_OUT_10 = 0x30, // H4 output in interlocked input handshake protocol
REG_PBCR_H4_CTRL_OUT_11 = 0x38, // H4 output in pulsed input handshake protocol
REG_PBCR_H4_INT_ENABLE = 0x04,
REG_PBCR_SUBMODE_MASK = 0xc0,
REG_PBCR_SUBMODE_00 = 0x00, // 0 0
REG_PBCR_SUBMODE_01 = 0x40, // 0 1
REG_PBCR_SUBMODE_10 = 0x80, // 1 0
REG_PBCR_SUBMODE_11 = 0xc0, // 1 1
REG_PBCR_SUBMODE_1X = 0x80, // submode 2 or 3
REG_PBCR_H4_CTRL_MASK = 0x38,
REG_PBCR_H4_CTRL_IN_OUT = 0x20, // H4 sense always cleared if set
REG_PBCR_H4_CTRL_OUT_00 = 0x20, // H4 output negated
REG_PBCR_H4_CTRL_OUT_01 = 0x28, // H4 output asserted
REG_PBCR_H4_CTRL_OUT_10 = 0x30, // H4 output in interlocked input handshake protocol
REG_PBCR_H4_CTRL_OUT_11 = 0x38, // H4 output in pulsed input handshake protocol
REG_PBCR_H4_INT_ENABLE = 0x04,
REG_PBCR_H3_SVCRQ_ENABLE= 0x02,
REG_PBCR_H3_STATUS_CTRL = 0x01,
REG_PBCR_H3_STATUS_CTRL = 0x01,
};
enum {
REG_PCDR_TIN_BIT = 2, // BIT number
REG_PCDR_TIN = 0x04 // bit position
REG_PCDR_TIN_BIT = 2, // BIT number
REG_PCDR_TIN = 0x04 // bit position
};
enum {
REG_TCR_TIMER_ENABLE = 0x01
REG_TCR_TIMER_ENABLE = 0x01
};
enum { // TCR - Timer Control register
@ -333,10 +333,10 @@ protected:
uint8_t m_pbdr; // Port B Data register
uint8_t m_pcdr; // Port C Data register
uint8_t m_psr; // Port Status Register
uint8_t m_tcr; // Timer Control Register
uint8_t m_tcr; // Timer Control Register
uint8_t m_tivr; // Timer Interrupt Vector register
int m_cpr; // Counter Preload Registers (3 x 8 = 24 bits)
int m_cntr; // - The 24 bit Counter
int m_cpr; // Counter Preload Registers (3 x 8 = 24 bits)
int m_cntr; // - The 24 bit Counter
uint8_t m_tsr; // Timer Status Register

2
src/devices/machine/netlist.cpp
View File

@ -249,7 +249,7 @@ void netlist_ram_pointer_t::device_start()
fatalerror("device %s wrong parameter type for %s\n", basetag(), m_param_name.cstr());
}
m_data = (*m_param)();
m_data = (*m_param)();
}
// ----------------------------------------------------------------------------------------

6
src/devices/machine/netlist.h
View File

@ -422,7 +422,7 @@ private:
// ----------------------------------------------------------------------------------------
class netlist_mame_int_input_t : public device_t,
public netlist_mame_sub_interface
public netlist_mame_sub_interface
{
public:
@ -514,7 +514,7 @@ private:
// ----------------------------------------------------------------------------------------
class netlist_mame_rom_t : public device_t,
public netlist_mame_sub_interface
public netlist_mame_sub_interface
{
public:
@ -544,7 +544,7 @@ private:
// ----------------------------------------------------------------------------------------
class netlist_ram_pointer_t: public device_t,
public netlist_mame_sub_interface
public netlist_mame_sub_interface
{
public:

2
src/devices/machine/z80scc.h
View File

@ -409,7 +409,7 @@ protected:
WR1_RX_INT_MODE_MASK = 0x18,
WR1_RX_INT_DISABLE = 0x00,
WR1_RX_INT_FIRST = 0x08,
WR1_RX_INT_ALL = 0x10,
WR1_RX_INT_ALL = 0x10,
WR1_RX_INT_PARITY = 0x18,
WR1_WRDY_ON_RX_TX = 0x20,
WR1_WRDY_FUNCTION = 0x40,

2
src/devices/sound/dac76.cpp
View File

@ -33,7 +33,7 @@ const device_type DAC76 = &device_creator<dac76_device>;
// dac76_device - constructor
//-------------------------------------------------
dac76_device::dac76_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
dac76_device::dac76_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
device_t(mconfig, DAC76, "DAC-76 COMDAC", tag, owner, clock, "dac76", __FILE__),
device_sound_interface(mconfig, *this),
m_stream(nullptr),

10
src/devices/sound/votrax.cpp
View File

@ -438,13 +438,13 @@ void votrax_sc01_device::chip_update()
// The formants are frozen on a pause phone unless both voice and
// noise volumes are zero.
if(tick_208 && (!m_rom_pause || !(m_filt_fa || m_filt_va))) {
// interpolate(m_cur_va, m_rom_va);
// interpolate(m_cur_va, m_rom_va);
interpolate(m_cur_fc, m_rom_fc);
interpolate(m_cur_f1, m_rom_f1);
interpolate(m_cur_f2, m_rom_f2);
interpolate(m_cur_f2q, m_rom_f2q);
interpolate(m_cur_f3, m_rom_f3);
// logerror("int fa=%x va=%x fc=%x f1=%x f2=%02x f2q=%02x f3=%x\n", m_cur_fa >> 4, m_cur_va >> 4, m_cur_fc >> 4, m_cur_f1 >> 4, m_cur_f2 >> 3, m_cur_f2q >> 4, m_cur_f3 >> 4);
// logerror("int fa=%x va=%x fc=%x f1=%x f2=%02x f2q=%02x f3=%x\n", m_cur_fa >> 4, m_cur_va >> 4, m_cur_fc >> 4, m_cur_f1 >> 4, m_cur_f2 >> 3, m_cur_f2q >> 4, m_cur_f3 >> 4);
}
// Non-formant update. Same bug there, va should be updated, not fc.
@ -452,9 +452,9 @@ void votrax_sc01_device::chip_update()
if(m_ticks >= m_rom_vd)
interpolate(m_cur_fa, m_rom_fa);
if(m_ticks >= m_rom_cld)
// interpolate(m_cur_fc, m_rom_fc);
// interpolate(m_cur_fc, m_rom_fc);
interpolate(m_cur_va, m_rom_va);
// logerror("int fa=%x va=%x fc=%x f1=%x f2=%02x f2q=%02x f3=%x\n", m_cur_fa >> 4, m_cur_va >> 4, m_cur_fc >> 4, m_cur_f1 >> 4, m_cur_f2 >> 3, m_cur_f2q >> 4, m_cur_f3 >> 4);
// logerror("int fa=%x va=%x fc=%x f1=%x f2=%02x f2q=%02x f3=%x\n", m_cur_fa >> 4, m_cur_va >> 4, m_cur_fc >> 4, m_cur_f1 >> 4, m_cur_f2 >> 3, m_cur_f2q >> 4, m_cur_f3 >> 4);
}
// Closure counter, reset every other tick in theory when not
@ -486,7 +486,7 @@ void votrax_sc01_device::chip_update()
m_noise = ((m_noise << 1) & 0x7ffe) | inp;
m_cur_noise = !(((m_noise >> 14) ^ (m_noise >> 13)) & 1);
// logerror("tick %02x.%03x 625=%d 208=%d pitch=%02x.%x ns=%04x ni=%d noise=%d cl=%x.%x clf=%d/%d\n", m_ticks, m_phonetick, tick_625, tick_208, m_pitch >> 2, m_pitch & 3, m_noise, inp, m_cur_noise, m_closure >> 2, m_closure & 3, m_rom_closure, m_cur_closure);
// logerror("tick %02x.%03x 625=%d 208=%d pitch=%02x.%x ns=%04x ni=%d noise=%d cl=%x.%x clf=%d/%d\n", m_ticks, m_phonetick, tick_625, tick_208, m_pitch >> 2, m_pitch & 3, m_noise, inp, m_cur_noise, m_closure >> 2, m_closure & 3, m_rom_closure, m_cur_closure);
}
void votrax_sc01_device::filters_commit(bool force)

2
src/devices/video/ef9369.cpp
View File

@ -100,5 +100,5 @@ WRITE8_MEMBER( ef9369_device::data_w )
WRITE8_MEMBER( ef9369_device::address_w )
{
m_address = data & 0x1f; // 5-bit
m_address = data & 0x1f; // 5-bit
}

4
src/devices/video/ef9369.h
View File

@ -48,7 +48,7 @@
//**************************************************************************
typedef device_delegate<void (int entry, bool m, uint8_t ca, uint8_t cb, uint8_t cc)> ef9369_color_update_delegate;
#define EF9369_COLOR_UPDATE(name) void name(int entry, bool m, uint8_t ca, uint8_t cb, uint8_t cc)
#define EF9369_COLOR_UPDATE(name) void name(int entry, bool m, uint8_t ca, uint8_t cb, uint8_t cc)
// ======================> ef9369_device
@ -76,7 +76,7 @@ private:
ef9369_color_update_delegate m_color_update_cb;
// state
uint8_t m_ca[NUMCOLORS], m_cb[NUMCOLORS], m_cc[NUMCOLORS]; // actually 4-bit
uint8_t m_ca[NUMCOLORS], m_cb[NUMCOLORS], m_cc[NUMCOLORS]; // actually 4-bit
bool m_m[NUMCOLORS];
int m_address;
};

10
src/devices/video/zeus2.cpp
View File

@ -716,7 +716,7 @@ void zeus2_device::zeus2_register_update(offs_t offset, uint32_t oldval, int log
}
/* make sure we log anything else */
//else if (logit || m_zeusbase[0x50] != 0x0)
// logerror("\tw[50]=%08X [5E]=%08X\n", m_zeusbase[0x50], m_zeusbase[0x5e]);
// logerror("\tw[50]=%08X [5E]=%08X\n", m_zeusbase[0x50], m_zeusbase[0x5e]);
}
}
break;
@ -1634,14 +1634,14 @@ void zeus2_renderer::zeus2_draw_quad(const uint32_t *databuffer, uint32_t texdat
vert[i].p[0] += m_state->zeus_point[2];
}
//if (0)
// //vert[i].p[0] += m_state->zbase;
// vert[i].p[0] += reinterpret_cast<float&>(m_state->m_zeusbase[0x63]);
// //vert[i].p[0] += m_state->zbase;
// vert[i].p[0] += reinterpret_cast<float&>(m_state->m_zeusbase[0x63]);
//else {
int shift;
shift = 1024 >> m_state->m_zeusbase[0x6c];
vert[i].p[0] += shift;
// //float zScale = reinterpret_cast<float&>(m_state->m_zeusbase[0x63]);
// //vert[i].p[0] += zScale;
// //float zScale = reinterpret_cast<float&>(m_state->m_zeusbase[0x63]);
// //vert[i].p[0] += zScale;
//}
vert[i].p[2] += (texdata >> 16) << 2;

10
src/lib/netlist/devices/net_lib.cpp
View File

@ -143,8 +143,8 @@ static void initialize_factory(factory_list_t &factory)
ENTRYX(9312, TTL_9312, "-")
ENTRYX(9316, TTL_9316, "+CLK,ENP,ENT,CLRQ,LOADQ,A,B,C,D")
ENTRYX(9322, TTL_9322, "-")
ENTRYX(9334, TTL_9334, "+CQ,EQ,D,A0,A1,A2")
ENTRYX(AM2847, TTL_AM2847, "+CP,INA,INB,INC,IND,RCA,RCB,RCC,RCD")
ENTRYX(9334, TTL_9334, "+CQ,EQ,D,A0,A1,A2")
ENTRYX(AM2847, TTL_AM2847, "+CP,INA,INB,INC,IND,RCA,RCB,RCC,RCD")
ENTRYX(CD4020, CD4020, "")
ENTRYX(CD4066_GATE, CD4066_GATE, "")
/* entries with suffix WI are legacy only */
@ -153,8 +153,8 @@ static void initialize_factory(factory_list_t &factory)
ENTRYX(NE555, NE555, "-")
ENTRYX(r2r_dac, R2R_DAC, "+VIN,R,N")
ENTRYX(tristate, TTL_TRISTATE, "+CEQ1,D1,CEQ2,D2")
ENTRYX(tristate3, TTL_TRISTATE3, "-")
ENTRYX(2102A_dip, RAM_2102A_DIP, "-")
ENTRYX(tristate3, TTL_TRISTATE3, "-")
ENTRYX(2102A_dip, RAM_2102A_DIP, "-")
ENTRYX(2716_dip, EPROM_2716_DIP, "-")
ENTRYX(4538_dip, CD4538_DIP, "-")
ENTRYX(7448_dip, TTL_7448_DIP, "-")
@ -191,7 +191,7 @@ static void initialize_factory(factory_list_t &factory)
ENTRYX(9316_dip, TTL_9316_DIP, "-")
ENTRYX(9322_dip, TTL_9322_DIP, "-")
ENTRYX(9334_dip, TTL_9334_DIP, "-")
ENTRYX(AM2847_dip, TTL_AM2847_DIP, "-")
ENTRYX(AM2847_dip, TTL_AM2847_DIP, "-")
ENTRYX(SN74LS629_dip, SN74LS629_DIP, "1.CAP1,2.CAP2")
ENTRYX(NE555_dip, NE555_DIP, "-")
ENTRYX(MM5837_dip, MM5837_DIP, "-")

4
src/lib/netlist/devices/nld_2102A.cpp
View File

@ -7,8 +7,8 @@
#include "nld_2102A.h"
#define ADDR2BYTE(a) ((a) >> 3)
#define ADDR2BIT(a) ((a) & 0x7)
#define ADDR2BYTE(a) ((a) >> 3)
#define ADDR2BIT(a) ((a) & 0x7)
namespace netlist
{

28
src/lib/netlist/devices/nld_2102A.h
View File

@ -26,20 +26,20 @@
#include "nl_setup.h"
#define RAM_2102A(name, cCEQ, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7, cA8, cA9, cRWQ, cDI) \
NET_REGISTER_DEV(RAM_2102A, name) \
NET_CONNECT(name, CEQ, cCEQ) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, A4, cA4) \
NET_CONNECT(name, A5, cA5) \
NET_CONNECT(name, A6, cA6) \
NET_CONNECT(name, A7, cA7) \
NET_CONNECT(name, A8, cA8) \
NET_CONNECT(name, A9, cA9) \
NET_CONNECT(name, RWQ, cRWQ) \
#define RAM_2102A(name, cCEQ, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7, cA8, cA9, cRWQ, cDI) \
NET_REGISTER_DEV(RAM_2102A, name) \
NET_CONNECT(name, CEQ, cCEQ) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, A4, cA4) \
NET_CONNECT(name, A5, cA5) \
NET_CONNECT(name, A6, cA6) \
NET_CONNECT(name, A7, cA7) \
NET_CONNECT(name, A8, cA8) \
NET_CONNECT(name, A9, cA9) \
NET_CONNECT(name, RWQ, cRWQ) \
NET_CONNECT(name, DI, cDI)
#define RAM_2102A_DIP(name) \

8
src/lib/netlist/devices/nld_2716.cpp
View File

@ -78,10 +78,10 @@ namespace netlist
for (std::size_t i=0; i<11; i++)
a |= (m_A[i]() << i);
if (m_ROM() != nullptr)
{
d = ((std::uint_fast8_t*)(m_ROM()))[a];
}
if (m_ROM() != nullptr)
{
d = ((std::uint_fast8_t*)(m_ROM()))[a];
}
if (m_last_EPQ)
delay = NLTIME_FROM_NS(120);

26
src/lib/netlist/devices/nld_2716.h
View File

@ -30,20 +30,20 @@
#include "nl_setup.h"
#define EPROM_2716(name, cGQ, cEPQ, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7, cA8, cA9, cA10) \
#define EPROM_2716(name, cGQ, cEPQ, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7, cA8, cA9, cA10) \
NET_REGISTER_DEV(EPROM_2716, name) \
NET_CONNECT(name, GQ, cGQ) \
NET_CONNECT(name, EPQ, cEPQ) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, A4, cA4) \
NET_CONNECT(name, A5, cA5) \
NET_CONNECT(name, A6, cA6) \
NET_CONNECT(name, A7, cA7) \
NET_CONNECT(name, A8, cA8) \
NET_CONNECT(name, A9, cA9) \
NET_CONNECT(name, GQ, cGQ) \
NET_CONNECT(name, EPQ, cEPQ) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, A4, cA4) \
NET_CONNECT(name, A5, cA5) \
NET_CONNECT(name, A6, cA6) \
NET_CONNECT(name, A7, cA7) \
NET_CONNECT(name, A8, cA8) \
NET_CONNECT(name, A9, cA9) \
NET_CONNECT(name, A10, cA10)
#define EPROM_2716_DIP(name) \

2
src/lib/netlist/devices/nld_74107.h
View File

@ -76,7 +76,7 @@
#define TTL_74107(name, cCLK, cJ, cK, cCLRQ) \
TTL_74107A(name, cCLK, cJ, cK, cCLRQ)
#define TTL_74107_DIP(name) \
#define TTL_74107_DIP(name) \
NET_REGISTER_DEV(TTL_74107_DIP, name)
#endif /* NLD_74107_H_ */

16
src/lib/netlist/devices/nld_74161.cpp
View File

@ -96,31 +96,31 @@ namespace netlist
netlist_sig_t tRippleCarryOut = 0;
if (!m_CLRQ())
{
m_cnt = 0;
m_cnt = 0;
}
else if (m_CLK() && !m_last_CLK)
{
if (!m_LOADQ())
{
m_cnt = (m_D() << 3) | (m_C() << 2)
m_cnt = (m_D() << 3) | (m_C() << 2)
| (m_B() << 1) | (m_A() << 0);
}
}
else if (m_ENABLET() && m_ENABLEP())
{
m_cnt++;
if (m_cnt > MAXCNT)
m_cnt = 0;
}
}
}
if (m_ENABLET() && (m_cnt == MAXCNT))
{
tRippleCarryOut = 1;
}
{
tRippleCarryOut = 1;
}
m_last_CLK = m_CLK();
for (std::size_t i=0; i<4; i++)
for (std::size_t i=0; i<4; i++)
m_Q[i].push((m_cnt >> i) & 1, delay[i]);
m_RCO.push(tRippleCarryOut, NLTIME_FROM_NS(20)); //FIXME

16
src/lib/netlist/devices/nld_74161.h
View File

@ -28,14 +28,14 @@
#include "nl_setup.h"
#define TTL_74161(name, cA, cB, cC, cD, cCLRQ, cLOADQ, cCLK, cENABLEP, cENABLET) \
NET_REGISTER_DEV(TTL_74161, name) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, CLRQ, cCLRQ) \
NET_CONNECT(name, LOADQ, cLOADQ) \
NET_CONNECT(name, CLK, cCLK) \
NET_REGISTER_DEV(TTL_74161, name) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, CLRQ, cCLRQ) \
NET_CONNECT(name, LOADQ, cLOADQ) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, ENABLEP, cENABLEP) \
NET_CONNECT(name, ENABLET, cENABLET)

26
src/lib/netlist/devices/nld_74165.h
View File

@ -29,19 +29,19 @@
#include "nl_setup.h"
#define TTL_74165(name, cCLK, cCLKINH, cSH_LDQ, cSER, cA, cB, cC, cD, cE, cF, cG, cH) \
NET_REGISTER_DEV(TTL_74165, name) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, CLKINH, cCLKINH) \
NET_CONNECT(name, SH_LDQ, cSH_LDQ) \
NET_CONNECT(name, SER, cSER) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, E, cE) \
NET_CONNECT(name, F, cF) \
NET_CONNECT(name, G, cG) \
#define TTL_74165(name, cCLK, cCLKINH, cSH_LDQ, cSER, cA, cB, cC, cD, cE, cF, cG, cH) \
NET_REGISTER_DEV(TTL_74165, name) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, CLKINH, cCLKINH) \
NET_CONNECT(name, SH_LDQ, cSH_LDQ) \
NET_CONNECT(name, SER, cSER) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, E, cE) \
NET_CONNECT(name, F, cF) \
NET_CONNECT(name, G, cG) \
NET_CONNECT(name, H, cH)
#define TTL_74165_DIP(name) \

28
src/lib/netlist/devices/nld_74166.h
View File

@ -29,20 +29,20 @@
#include "nl_setup.h"
#define TTL_74166(name, cCLK, cCLKINH, cSH_LDQ, cSER, cA, cB, cC, cD, cE, cF, cG, cH, cCLRQ) \
NET_REGISTER_DEV(TTL_74166, name) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, CLKINH, cCLKINH) \
NET_CONNECT(name, SH_LDQ, cSH_LDQ) \
NET_CONNECT(name, SER, cSER) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, E, cE) \
NET_CONNECT(name, F, cF) \
NET_CONNECT(name, G, cG) \
NET_CONNECT(name, H, cH) \
#define TTL_74166(name, cCLK, cCLKINH, cSH_LDQ, cSER, cA, cB, cC, cD, cE, cF, cG, cH, cCLRQ) \
NET_REGISTER_DEV(TTL_74166, name) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, CLKINH, cCLKINH) \
NET_CONNECT(name, SH_LDQ, cSH_LDQ) \
NET_CONNECT(name, SER, cSER) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, E, cE) \
NET_CONNECT(name, F, cF) \
NET_CONNECT(name, G, cG) \
NET_CONNECT(name, H, cH) \
NET_CONNECT(name, CLRQ, cCLRQ)
#define TTL_74166_DIP(name) \

18
src/lib/netlist/devices/nld_74174.h
View File

@ -38,15 +38,15 @@
#include "nl_setup.h"
#define TTL_74174(name, cCLK, cD1, cD2, cD3, cD4, cD5, cD6, cCLRQ) \
NET_REGISTER_DEV(TTL_74174, name) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, D1, cD1) \
NET_CONNECT(name, D2, cD2) \
NET_CONNECT(name, D3, cD3) \
NET_CONNECT(name, D4, cD4) \
NET_CONNECT(name, D5, cD5) \
NET_CONNECT(name, D6, cD6) \
#define TTL_74174(name, cCLK, cD1, cD2, cD3, cD4, cD5, cD6, cCLRQ) \
NET_REGISTER_DEV(TTL_74174, name) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, D1, cD1) \
NET_CONNECT(name, D2, cD2) \
NET_CONNECT(name, D3, cD3) \
NET_CONNECT(name, D4, cD4) \
NET_CONNECT(name, D5, cD5) \
NET_CONNECT(name, D6, cD6) \
NET_CONNECT(name, CLRQ, cCLRQ)
#define TTL_74174_DIP(name) \

14
src/lib/netlist/devices/nld_74175.h
View File

@ -38,13 +38,13 @@
#include "nl_setup.h"
#define TTL_74175(name, cCLK, cD1, cD2, cD3, cD4, cCLRQ) \
NET_REGISTER_DEV(TTL_74175, name) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, D1, cD1) \
NET_CONNECT(name, D2, cD2) \
NET_CONNECT(name, D3, cD3) \
NET_CONNECT(name, D4, cD4) \
#define TTL_74175(name, cCLK, cD1, cD2, cD3, cD4, cCLRQ) \
NET_REGISTER_DEV(TTL_74175, name) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, D1, cD1) \
NET_CONNECT(name, D2, cD2) \
NET_CONNECT(name, D3, cD3) \
NET_CONNECT(name, D4, cD4) \
NET_CONNECT(name, CLRQ, cCLRQ)
#define TTL_74175_DIP(name) \

18
src/lib/netlist/devices/nld_74192.h
View File

@ -31,15 +31,15 @@
#include "nl_setup.h"
#define TTL_74192(name, cA, cB, cC, cD, cCLEAR, cLOADQ, cCU, cCD) \
NET_REGISTER_DEV(TTL_74192, name) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, CLEAR, cCLEAR) \
NET_CONNECT(name, LOADQ, cLOADQ) \
NET_CONNECT(name, CU, cCU) \
#define TTL_74192(name, cA, cB, cC, cD, cCLEAR, cLOADQ, cCU, cCD) \
NET_REGISTER_DEV(TTL_74192, name) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, CLEAR, cCLEAR) \
NET_CONNECT(name, LOADQ, cLOADQ) \
NET_CONNECT(name, CU, cCU) \
NET_CONNECT(name, CD, cCD)
#define TTL_74192_DIP(name) \

14
src/lib/netlist/devices/nld_74193.h
View File

@ -28,15 +28,15 @@
#include "nl_setup.h"
#define TTL_74193(name, cA, cB, cC, cD, cCLEAR, cLOADQ, cCU, cCD) \
NET_REGISTER_DEV(TTL_74193, name) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
#define TTL_74193(name, cA, cB, cC, cD, cCLEAR, cLOADQ, cCU, cCD) \
NET_REGISTER_DEV(TTL_74193, name) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, CLEAR, cCLEAR) \
NET_CONNECT(name, LOADQ, cLOADQ) \
NET_CONNECT(name, CU, cCU) \
NET_CONNECT(name, CU, cCU) \
NET_CONNECT(name, CD, cCD)
#define TTL_74193_DIP(name) \

22
src/lib/netlist/devices/nld_74194.h
View File

@ -28,17 +28,17 @@
#include "nl_setup.h"
#define TTL_74194(name, cCLK, cS0, cS1, cSRIN, cA, cB, cC, cD, cSLIN, cCLRQ) \
NET_REGISTER_DEV(TTL_74194, name) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, S0, cS0) \
NET_CONNECT(name, S1, cC1) \
NET_CONNECT(name, SRIN, cSRIN) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, SLIN, cSLIN) \
#define TTL_74194(name, cCLK, cS0, cS1, cSRIN, cA, cB, cC, cD, cSLIN, cCLRQ) \
NET_REGISTER_DEV(TTL_74194, name) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, S0, cS0) \
NET_CONNECT(name, S1, cC1) \
NET_CONNECT(name, SRIN, cSRIN) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, SLIN, cSLIN) \
NET_CONNECT(name, CLRQ, cCLRQ)
#define TTL_74194_DIP(name) \

18
src/lib/netlist/devices/nld_74365.h
View File

@ -27,15 +27,15 @@
#include "nl_setup.h"
#define TTL_74365(name, cG1Q, cG2Q, cA1, cA2, cA3, cA4, cA5, cA6) \
NET_REGISTER_DEV(TTL_74365, name) \
NET_CONNECT(name, G1Q, cG1Q) \
NET_CONNECT(name, G2Q, cG2Q) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, A4, cA4) \
NET_CONNECT(name, A5, cA5) \
#define TTL_74365(name, cG1Q, cG2Q, cA1, cA2, cA3, cA4, cA5, cA6) \
NET_REGISTER_DEV(TTL_74365, name) \
NET_CONNECT(name, G1Q, cG1Q) \
NET_CONNECT(name, G2Q, cG2Q) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, A4, cA4) \
NET_CONNECT(name, A5, cA5) \
NET_CONNECT(name, A6, cA6)
#define TTL_74365_DIP(name) \

58
src/lib/netlist/devices/nld_7473.cpp
View File

@ -18,14 +18,14 @@ namespace netlist
, m_J(*this, "J")
, m_K(*this, "K")
, m_CLRQ(*this, "CLRQ")
, m_last_CLK(*this, "m_last_CLK", 0)
, m_q(*this, "m_q", 0)
, m_last_CLK(*this, "m_last_CLK", 0)
, m_q(*this, "m_q", 0)
, m_Q(*this, "Q")
, m_QQ(*this, "QQ")
{
}
NETLIB_RESETI();
NETLIB_RESETI();
NETLIB_UPDATEI();
public:
@ -34,10 +34,10 @@ namespace netlist
logic_input_t m_K;
logic_input_t m_CLRQ;
state_var<unsigned> m_last_CLK;
state_var<unsigned> m_q;
state_var<unsigned> m_last_CLK;
state_var<unsigned> m_q;
logic_output_t m_Q;
logic_output_t m_Q;
logic_output_t m_QQ;
};
@ -104,38 +104,38 @@ namespace netlist
NETLIB_SUB(7473A) m_2;
};
NETLIB_RESET(7473)
{
m_last_CLK = 0;
}
NETLIB_RESET(7473)
{
m_last_CLK = 0;
}
NETLIB_UPDATE(7473)
NETLIB_UPDATE(7473)
{
const auto JK = (m_J() << 1) | m_K();
if (m_CLRQ())
{
if (!m_CLK() && m_last_CLK)
{
switch (JK)
{
case 1: // (!m_J) & m_K))
m_q = 0;
break;
case 2: // (m_J) & !m_K))
m_q = 1;
break;
case 3: // (m_J) & m_K))
m_q ^= 1;
break;
default:
case 0:
break;
}
}
{
switch (JK)
{
case 1: // (!m_J) & m_K))
m_q = 0;
break;
case 2: // (m_J) & !m_K))
m_q = 1;
break;
case 3: // (m_J) & m_K))
m_q ^= 1;
break;
default:
case 0:
break;
}
}
}
m_last_CLK = m_CLK();
m_last_CLK = m_CLK();
m_Q.push(m_q, NLTIME_FROM_NS(20)); // FIXME: timing
m_QQ.push(m_q ^ 1, NLTIME_FROM_NS(20)); // FIXME: timing

16
src/lib/netlist/devices/nld_7473.h
View File

@ -62,21 +62,21 @@
#include "nl_setup.h"
#define TTL_7473(name, cCLK, cJ, cK, cCLRQ) \
NET_REGISTER_DEV(TTL_7473, name) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, J, cJ) \
NET_CONNECT(name, K, cK) \
#define TTL_7473(name, cCLK, cJ, cK, cCLRQ) \
NET_REGISTER_DEV(TTL_7473, name) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, J, cJ) \
NET_CONNECT(name, K, cK) \
NET_CONNECT(name, CLRQ, cCLRQ)
#define TTL_7473A(name, cCLK, cJ, cK, cCLRQ) \
#define TTL_7473A(name, cCLK, cJ, cK, cCLRQ) \
TTL_7473(name, cCLK, cJ, cK, cCLRQ)
#define TTL_7473_DIP(name) \
#define TTL_7473_DIP(name) \
NET_REGISTER_DEV(TTL_7473_DIP, name)
#define TTL_7473A_DIP(name) \
#define TTL_7473A_DIP(name) \
NET_REGISTER_DEV(TTL_7473A_DIP, name)
#endif /* NLD_7473_H_ */

2
src/lib/netlist/devices/nld_7475.cpp
View File

@ -128,7 +128,7 @@ namespace netlist
m_last_Q = 0;
}
NETLIB_UPDATE(7477)
NETLIB_UPDATE(7477)
{
netlist_sig_t c1c2 = m_C1C2();
netlist_sig_t c3c4 = m_C3C4();

24
src/lib/netlist/devices/nld_7475.h
View File

@ -37,26 +37,26 @@
#include "nl_setup.h"
#define PARAMS_7475_7477(name, cC1C2, cC3C4, cD1, cD2, cD3, cD4) \
NET_CONNECT(name, C1C2, cC1C2) \
NET_CONNECT(name, C3C4, cC3C4) \
NET_CONNECT(name, D1, cD1) \
NET_CONNECT(name, D2, cD2) \
NET_CONNECT(name, D3, cD3) \
#define PARAMS_7475_7477(name, cC1C2, cC3C4, cD1, cD2, cD3, cD4) \
NET_CONNECT(name, C1C2, cC1C2) \
NET_CONNECT(name, C3C4, cC3C4) \
NET_CONNECT(name, D1, cD1) \
NET_CONNECT(name, D2, cD2) \
NET_CONNECT(name, D3, cD3) \
NET_CONNECT(name, D4, cD4)
#define TTL_7475(name, cC1C2, cC3C4, cD1, cD2, cD3, cD4) \
NET_REGISTER_DEV(TTL_7475, name) \
#define TTL_7475(name, cC1C2, cC3C4, cD1, cD2, cD3, cD4) \
NET_REGISTER_DEV(TTL_7475, name) \
PARAMS_7475_7477(name, cC1C2, cC3C4, cD1, cD2, cD3, cD4)
#define TTL_7477(name, cC1C2, cC3C4, cD1, cD2, cD3, cD4) \
NET_REGISTER_DEV(TTL_7477, name) \
#define TTL_7477(name, cC1C2, cC3C4, cD1, cD2, cD3, cD4) \
NET_REGISTER_DEV(TTL_7477, name) \
PARAMS_7475_7477(name, cC1C2, cC3C4, cD1, cD2, cD3, cD4)
#define TTL_7475_DIP(name) \
#define TTL_7475_DIP(name) \
NET_REGISTER_DEV(TTL_7475_DIP, name)
#define TTL_7477_DIP(name) \
#define TTL_7477_DIP(name) \
NET_REGISTER_DEV(TTL_7477_DIP, name)
#endif /* NLD_7475_H_ */

22
src/lib/netlist/devices/nld_7485.h
View File

@ -26,17 +26,17 @@
#include "nl_setup.h"
#define TTL_7485(name, cA0, cA1, cA2, cA3, cB0, cB1, cB2, cB3, cLTIN, cEQIN, cGTIN) \
NET_REGISTER_DEV(TTL_7485, name) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, B0, cB0) \
NET_CONNECT(name, B1, cB1) \
NET_CONNECT(name, B2, cB2) \
NET_CONNECT(name, B3, cB3) \
NET_CONNECT(name, LTIN, cLTIN) \
NET_CONNECT(name, EQIN, cEQIN) \
NET_REGISTER_DEV(TTL_7485, name) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, B0, cB0) \
NET_CONNECT(name, B1, cB1) \
NET_CONNECT(name, B2, cB2) \
NET_CONNECT(name, B3, cB3) \
NET_CONNECT(name, LTIN, cLTIN) \
NET_CONNECT(name, EQIN, cEQIN) \
NET_CONNECT(name, GTIN, cGTIN)
#define TTL_7485_DIP(name) \

2
src/lib/netlist/devices/nld_82S115.cpp
View File

@ -101,7 +101,7 @@ namespace netlist
m_last_O = o;
// FIXME: Outputs are tristate. This needs to be properly implemented
// FIXME: Outputs are tristate. This needs to be properly implemented
for (std::size_t i=0; i<8; i++)
m_O[i].push((o >> i) & 1, NLTIME_FROM_NS(40)); // FIXME: Timing
}

26
src/lib/netlist/devices/nld_82S115.h
View File

@ -30,19 +30,19 @@
#include "nl_setup.h"
#define PROM_82S115(name, cCE1, cCE2Q, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7, cA8, cSTROBE) \
NET_REGISTER_DEV(PROM_82S115, name) \
NET_CONNECT(name, CE1Q, cCE1Q) \
NET_CONNECT(name, CE2Q, cCE2Q) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, A4, cA4) \
NET_CONNECT(name, A5, cA5) \
NET_CONNECT(name, A6, cA6) \
NET_CONNECT(name, A7, cA7) \
NET_CONNECT(name, A8, cA8) \
#define PROM_82S115(name, cCE1, cCE2Q, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7, cA8, cSTROBE) \
NET_REGISTER_DEV(PROM_82S115, name) \
NET_CONNECT(name, CE1Q, cCE1Q) \
NET_CONNECT(name, CE2Q, cCE2Q) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, A4, cA4) \
NET_CONNECT(name, A5, cA5) \
NET_CONNECT(name, A6, cA6) \
NET_CONNECT(name, A7, cA7) \
NET_CONNECT(name, A8, cA8) \
NET_CONNECT(name, STROBE, cSTROBE)
#define PROM_82S115_DIP(name) \

6
src/lib/netlist/devices/nld_82S123.cpp
View File

@ -66,13 +66,13 @@ namespace netlist
for (std::size_t i=0; i<5; i++)
a |= (m_A[i]() << i);
if (m_ROM() != nullptr)
o = ((std::uint_fast8_t*)(m_ROM()))[a];
if (m_ROM() != nullptr)
o = ((std::uint_fast8_t*)(m_ROM()))[a];
delay = NLTIME_FROM_NS(50);
}
// FIXME: Outputs are tristate. This needs to be properly implemented
// FIXME: Outputs are tristate. This needs to be properly implemented
for (std::size_t i=0; i<8; i++)
m_O[i].push((o >> i) & 1, delay);
}

14
src/lib/netlist/devices/nld_82S123.h
View File

@ -27,13 +27,13 @@
#include "nl_setup.h"
#define PROM_82S123(name, cCEQ, cA0, cA1, cA2, cA3, cA4) \
NET_REGISTER_DEV(PROM_82S123, name) \
NET_CONNECT(name, CEQ, cCEQ) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, A3, cA3) \
#define PROM_82S123(name, cCEQ, cA0, cA1, cA2, cA3, cA4) \
NET_REGISTER_DEV(PROM_82S123, name) \
NET_CONNECT(name, CEQ, cCEQ) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, A4, cA4)
#define PROM_82S123_DIP(name) \

6
src/lib/netlist/devices/nld_82S126.cpp
View File

@ -68,13 +68,13 @@ namespace netlist
for (std::size_t i=0; i<8; i++)
a |= (m_A[i]() << i);
if (m_ROM() != nullptr)
o = ((std::uint_fast8_t*)(m_ROM()))[a];
if (m_ROM() != nullptr)
o = ((std::uint_fast8_t*)(m_ROM()))[a];
delay = NLTIME_FROM_NS(50);
}
// FIXME: Outputs are tristate. This needs to be properly implemented
// FIXME: Outputs are tristate. This needs to be properly implemented
for (std::size_t i=0; i<4; i++)
m_O[i].push((o >> i) & 1, delay);
}

22
src/lib/netlist/devices/nld_82S126.h
View File

@ -26,17 +26,17 @@
#include "nl_setup.h"
#define PROM_82S126(name, cCE1Q, cCE2Q, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7) \
NET_REGISTER_DEV(PROM_82S126, name) \
NET_CONNECT(name, CE1Q, cCE1Q) \
NET_CONNECT(name, CE2Q, cCE2Q) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, A4, cA4) \
NET_CONNECT(name, A5, cA5) \
NET_CONNECT(name, A6, cA6) \
#define PROM_82S126(name, cCE1Q, cCE2Q, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7) \
NET_REGISTER_DEV(PROM_82S126, name) \
NET_CONNECT(name, CE1Q, cCE1Q) \
NET_CONNECT(name, CE2Q, cCE2Q) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, A4, cA4) \
NET_CONNECT(name, A5, cA5) \
NET_CONNECT(name, A6, cA6) \
NET_CONNECT(name, A7, cA7)
#define PROM_82S126_DIP(name) \

26
src/lib/netlist/devices/nld_9312.h
View File

@ -39,19 +39,19 @@
#include "nl_setup.h"
#define TTL_9312(name, cA, cB, cC, cD0, cD1, cD2, cD3, cD4, cD5, cD6, cD7, cSTROBE) \
NET_REGISTER_DEV(TTL_9312, name) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D0, cD0) \
NET_CONNECT(name, D1, cD1) \
NET_CONNECT(name, D2, cD2) \
NET_CONNECT(name, D3, cD3) \
NET_CONNECT(name, D4, cD4) \
NET_CONNECT(name, D5, cD5) \
NET_CONNECT(name, D6, cD6) \
NET_CONNECT(name, D7, cD7) \
#define TTL_9312(name, cA, cB, cC, cD0, cD1, cD2, cD3, cD4, cD5, cD6, cD7, cSTROBE) \
NET_REGISTER_DEV(TTL_9312, name) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D0, cD0) \
NET_CONNECT(name, D1, cD1) \
NET_CONNECT(name, D2, cD2) \
NET_CONNECT(name, D3, cD3) \
NET_CONNECT(name, D4, cD4) \
NET_CONNECT(name, D5, cD5) \
NET_CONNECT(name, D6, cD6) \
NET_CONNECT(name, D7, cD7) \
NET_CONNECT(name, STROBE, cSTROBE)
#define TTL_9312_DIP(name) \

4
src/lib/netlist/devices/nld_9316.h
View File

@ -44,8 +44,8 @@
*
* Naming conventions follow National Semiconductor datasheet
*
* TODO: DM74161 is compatible to DM9316 (both asynchronous clear)
* DM74163 has asynchronous clear (on L to H transition of clock)
* TODO: DM74161 is compatible to DM9316 (both asynchronous clear)
* DM74163 has asynchronous clear (on L to H transition of clock)
*/
#ifndef NLD_9316_H_

22
src/lib/netlist/devices/nld_9322.h
View File

@ -23,17 +23,17 @@
#include "nl_setup.h"
#define TTL_9322(name, cSELECT, cA1, cB1, cA2, cB2, cA3, cB3, cA4, cB4, cSTROBE) \
NET_REGISTER_DEV(TTL_9322, name) \
NET_CONNECT(name, SELECT, cSELECT) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, B1, cB1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, B2, cB2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, B3, cB3) \
NET_CONNECT(name, A4, cA4) \
NET_CONNECT(name, B4, cB4) \
#define TTL_9322(name, cSELECT, cA1, cB1, cA2, cB2, cA3, cB3, cA4, cB4, cSTROBE) \
NET_REGISTER_DEV(TTL_9322, name) \
NET_CONNECT(name, SELECT, cSELECT) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, B1, cB1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, B2, cB2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, B3, cB3) \
NET_CONNECT(name, A4, cA4) \
NET_CONNECT(name, B4, cB4) \
NET_CONNECT(name, STROBE, cSTROBE)
#define TTL_9322_DIP(name) \

2
src/lib/netlist/devices/nld_am2847.cpp
View File

@ -105,7 +105,7 @@ namespace netlist
m_C.shift();
m_D.shift();
}
m_last_CP = m_CP();
m_last_CP = m_CP();
}
inline NETLIB_FUNC_VOID(Am2847_shifter, shift, (void))

20
src/lib/netlist/devices/nld_am2847.h
View File

@ -23,16 +23,16 @@
#include "nl_setup.h"
#define TTL_AM2847(name, cCP, cINA, cINB, cINC, cIND, cRCA, cRCB, cRCC, cRCD) \
NET_REGISTER_DEV(TTL_AM2847, name) \
NET_CONNECT(name, CP, cCP) \
NET_CONNECT(name, INA, cINA) \
NET_CONNECT(name, INB, cINB) \
NET_CONNECT(name, INC, cINC) \
NET_CONNECT(name, IND, cIND) \
NET_CONNECT(name, RCA, cRCA) \
NET_CONNECT(name, RCB, cRCB) \
NET_CONNECT(name, RCC, cRCC) \
#define TTL_AM2847(name, cCP, cINA, cINB, cINC, cIND, cRCA, cRCB, cRCC, cRCD) \
NET_REGISTER_DEV(TTL_AM2847, name) \
NET_CONNECT(name, CP, cCP) \
NET_CONNECT(name, INA, cINA) \
NET_CONNECT(name, INB, cINB) \
NET_CONNECT(name, INC, cINC) \
NET_CONNECT(name, IND, cIND) \
NET_CONNECT(name, RCA, cRCA) \
NET_CONNECT(name, RCB, cRCB) \
NET_CONNECT(name, RCC, cRCC) \
NET_CONNECT(name, RCD, cRCD)
#define TTL_AM2847_DIP(name) \

14
src/lib/netlist/devices/nld_dm9334.h
View File

@ -67,13 +67,13 @@
#include "nl_setup.h"
#define TTL_9334(name, cCQ, cEQ, cD, cA0, cA1, cA2) \
NET_REGISTER_DEV(TTL_9334, name) \
NET_CONNECT(name, CQ, cCQ) \
NET_CONNECT(name, EQ, cEQ) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \
#define TTL_9334(name, cCQ, cEQ, cD, cA0, cA1, cA2) \
NET_REGISTER_DEV(TTL_9334, name) \
NET_CONNECT(name, CQ, cCQ) \
NET_CONNECT(name, EQ, cEQ) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2)
#define TTL_9334_DIP(name) \

56
src/lib/netlist/devices/nld_tristate.cpp
View File

@ -28,24 +28,24 @@ namespace netlist
logic_output_t m_Q;
};
NETLIB_OBJECT(tristate3)
{
NETLIB_CONSTRUCTOR(tristate3)
, m_CEQ(*this, {{ "CEQ1", "CEQ2", "CEQ3" }} )
, m_D(*this, {{ "D1", "D2", "D3" }} )
, m_Q(*this, "Q")
{
}
NETLIB_OBJECT(tristate3)
{
NETLIB_CONSTRUCTOR(tristate3)
, m_CEQ(*this, {{ "CEQ1", "CEQ2", "CEQ3" }} )
, m_D(*this, {{ "D1", "D2", "D3" }} )
, m_Q(*this, "Q")
{
}
NETLIB_UPDATEI();
NETLIB_UPDATEI();
protected:
object_array_t<logic_input_t, 3> m_CEQ;
object_array_t<logic_input_t, 3> m_D;
logic_output_t m_Q;
};
protected:
object_array_t<logic_input_t, 3> m_CEQ;
object_array_t<logic_input_t, 3> m_D;
logic_output_t m_Q;
};
NETLIB_UPDATE(tristate)
NETLIB_UPDATE(tristate)
{
unsigned q = 0;
if (!m_CEQ[0]())
@ -56,21 +56,21 @@ namespace netlist
m_Q.push(q, NLTIME_FROM_NS(1));
}
NETLIB_UPDATE(tristate3)
{
unsigned q = 0;
if (!m_CEQ[0]())
q |= m_D[0]();
if (!m_CEQ[1]())
q |= m_D[1]();
if (!m_CEQ[2]())
q |= m_D[2]();
NETLIB_UPDATE(tristate3)
{
unsigned q = 0;
if (!m_CEQ[0]())
q |= m_D[0]();
if (!m_CEQ[1]())
q |= m_D[1]();
if (!m_CEQ[2]())
q |= m_D[2]();
m_Q.push(q, NLTIME_FROM_NS(1));
}
m_Q.push(q, NLTIME_FROM_NS(1));
}
NETLIB_DEVICE_IMPL(tristate)
NETLIB_DEVICE_IMPL(tristate3)
NETLIB_DEVICE_IMPL(tristate)
NETLIB_DEVICE_IMPL(tristate3)
} //namespace devices
} // namespace netlist

24
src/lib/netlist/devices/nld_tristate.h
View File

@ -12,20 +12,20 @@
#include "nl_setup.h"
#define TTL_TRISTATE(name, cCEQ1, cD1, cCEQ2, cD2) \
NET_REGISTER_DEV(TTL_TRISTATE, name) \
NET_CONNECT(name, CEQ1, cCEQ1) \
NET_CONNECT(name, D1, cD1) \
NET_CONNECT(name, CEQ2, cCEQ2) \
#define TTL_TRISTATE(name, cCEQ1, cD1, cCEQ2, cD2) \
NET_REGISTER_DEV(TTL_TRISTATE, name) \
NET_CONNECT(name, CEQ1, cCEQ1) \
NET_CONNECT(name, D1, cD1) \
NET_CONNECT(name, CEQ2, cCEQ2) \
NET_CONNECT(name, D2, cD2)
#define TTL_TRISTATE3(name, cCEQ1, cD1, cCEQ2, cD2, cCEQ3, cD3) \
NET_REGISTER_DEV(TTL_TRISTATE3, name) \
NET_CONNECT(name, CEQ1, cCEQ1) \
NET_CONNECT(name, D1, cD1) \
NET_CONNECT(name, CEQ2, cCEQ2) \
#define TTL_TRISTATE3(name, cCEQ1, cD1, cCEQ2, cD2, cCEQ3, cD3) \
NET_REGISTER_DEV(TTL_TRISTATE3, name) \
NET_CONNECT(name, CEQ1, cCEQ1) \
NET_CONNECT(name, D1, cD1) \
NET_CONNECT(name, CEQ2, cCEQ2) \
NET_CONNECT(name, D2, cD2) \
NET_CONNECT(name, CEQ3, cCEQ3) \
NET_CONNECT(name, D3, cD3)
NET_CONNECT(name, CEQ3, cCEQ3) \
NET_CONNECT(name, D3, cD3)
#endif /* NLD_TRISTATE_H_ */

14
src/lib/netlist/macro/nlm_ttl74xx.h
View File

@ -189,15 +189,15 @@
#define TTL_74260_GATE(name) \
NET_REGISTER_DEV(TTL_74260_GATE, name)
#define TTL_74260_NOR(name, cA, cB, cC, cD, cE) \
NET_REGISTER_DEV(TTL_74260_NOR, name) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
#define TTL_74260_NOR(name, cA, cB, cC, cD, cE) \
NET_REGISTER_DEV(TTL_74260_NOR, name) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD) \
NET_CONNECT(name, E, cE)
#define TTL_74260_DIP(name) \
#define TTL_74260_DIP(name) \
NET_REGISTER_DEV(TTL_74260_DIP, name)
/* ----------------------------------------------------------------------------

2
src/mame/audio/csd.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders: Aaron Giles
/***************************************************************************
Cheap Squeak Deluxe / Artificial Artist Sound Board
Cheap Squeak Deluxe / Artificial Artist Sound Board
***************************************************************************/

2
src/mame/audio/csd.h
View File

@ -2,7 +2,7 @@
// copyright-holders: Aaron Giles
/***************************************************************************
Cheap Squeak Deluxe / Artificial Artist Sound Board
Cheap Squeak Deluxe / Artificial Artist Sound Board
***************************************************************************/

2
src/mame/audio/dcs.cpp
View File

@ -246,7 +246,7 @@ enum
#define DSIO_DM_PG ((m_dsio.reg[2] >> 0) & 0x7ff)
#define DSIO_BANK_END 0x7ff
#define DSIO_BANK_END 0x7ff
/* these macros are used to reference the DENVER ASIC */
#define DENV_DSP_SPEED ((m_dsio.reg[1] >> 2) & 3) /* read only: 1=33.33MHz */

14
src/mame/drivers/atarittl.cpp
View File

@ -57,15 +57,15 @@
netlist system per-game:
TM-057 (Stunt Cycle)
4136 Quad General-Purpose Operational Amplifiers
4136 Quad General-Purpose Operational Amplifiers
TM-055 (Indy 4)
7406 Hex Inverter Buffers/Drivers with O.C. H.V. Outputs (note: Might not be needed, could just clone from 7404)
7414 Hex Schmitt-Trigger Inverters
7417 Hex Buffers/Drivers
74164 8-bit Serial-In, Parallel-Out Shift Register
9301 1-of-10 Decoder
LM339 Quad Comparator
7406 Hex Inverter Buffers/Drivers with O.C. H.V. Outputs (note: Might not be needed, could just clone from 7404)
7414 Hex Schmitt-Trigger Inverters
7417 Hex Buffers/Drivers
74164 8-bit Serial-In, Parallel-Out Shift Register
9301 1-of-10 Decoder
LM339 Quad Comparator
***************************************************************************/

32
src/mame/drivers/beezer.cpp
View File

@ -3,23 +3,23 @@
// thanks-to: Jonathan Gevaryahu
/***************************************************************************
Beezer
Beezer
(c) 1982 Tong Electronic
(c) 1982 Tong Electronic
Notes:
- To enter test mode, hold down 1P Start and 2P Start, then reset
- One of the ROMs contains a message that this game was created
by "Pacific Polytechnical Corporation, Santa Cruz"
Notes:
- To enter test mode, hold down 1P Start and 2P Start, then reset
- One of the ROMs contains a message that this game was created
by "Pacific Polytechnical Corporation, Santa Cruz"
TODO:
- Improve sound (filters? A reference recording would be nice)
- Schematics in the sound area seem incomplete, there are
several unknown connections
- Watchdog timing (controlled by a 555)
- Figure out differences between the two sets (test mode isn't
working in beezer1, instruction screen is different)
- Verify accuracy of colors
TODO:
- Improve sound (filters? A reference recording would be nice)
- Schematics in the sound area seem incomplete, there are
several unknown connections
- Watchdog timing (controlled by a 555)
- Figure out differences between the two sets (test mode isn't
working in beezer1, instruction screen is different)
- Verify accuracy of colors
***************************************************************************/
@ -154,8 +154,8 @@ static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, beezer_state )
AM_RANGE(0x1000, 0x1007) AM_MIRROR(0x07f8) AM_DEVREADWRITE("ptm", ptm6840_device, read, write)
AM_RANGE(0x1800, 0x180f) AM_MIRROR(0x07f0) AM_DEVREADWRITE("via_u18", via6522_device, read, write)
AM_RANGE(0x8000, 0x8003) AM_MIRROR(0x1ffc) AM_WRITE(dac_w)
// AM_RANGE(0xa000, 0xbfff) AM_ROM // 2d (can be ram, unpopulated)
// AM_RANGE(0xc000, 0xdfff) AM_ROM // 4d (unpopulated)
// AM_RANGE(0xa000, 0xbfff) AM_ROM // 2d (can be ram, unpopulated)
// AM_RANGE(0xc000, 0xdfff) AM_ROM // 4d (unpopulated)
AM_RANGE(0xe000, 0xffff) AM_ROM AM_REGION("audiocpu", 0) // 6d
ADDRESS_MAP_END

2
src/mame/drivers/by35.cpp
View File

@ -2306,7 +2306,7 @@ ROM_START(uboat65)
ROM_RELOAD(0x28000, 0x8000)
ROM_RELOAD(0x38000, 0x8000)
ROM_REGION(0x10000, "cpu2", 0)
ROM_LOAD("snd_u8.bin", 0x8000, 0x8000, CRC(d00fd4fd) SHA1(23f6b7c5d60821eb7fa2fdcfc85caeb536eef99a))
ROM_LOAD("snd_u8.bin", 0x8000, 0x8000, CRC(d00fd4fd) SHA1(23f6b7c5d60821eb7fa2fdcfc85caeb536eef99a))
ROM_END
/*--------------------------------
/ Big Ball Bowling (Bowler)

16
src/mame/drivers/ccastles.cpp
View File

@ -361,10 +361,10 @@ static INPUT_PORTS_START( ccastles )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_TILT )
PORT_SERVICE( 0x10, IP_ACTIVE_LOW )
PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, ccastles_state,get_vblank, nullptr)
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Left Jump/1P Start Upright") PORT_CONDITION("IN1",0x20,EQUALS,0x00) /* left Jump, non-cocktail start1 */
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("1P Jump") PORT_CONDITION("IN1",0x20,EQUALS,0x20) /* 1p Jump, cocktail */
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("Right Jump/2P Start Upright") PORT_CONDITION("IN1",0x20,EQUALS,0x00) /* right Jump, non-cocktail start2 */
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL PORT_NAME("2P Jump") PORT_CONDITION("IN1",0x20,EQUALS,0x20) /* 2p Jump, cocktail */
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Left Jump/1P Start Upright") PORT_CONDITION("IN1",0x20,EQUALS,0x00) /* left Jump, non-cocktail start1 */
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("1P Jump") PORT_CONDITION("IN1",0x20,EQUALS,0x20) /* 1p Jump, cocktail */
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("Right Jump/2P Start Upright") PORT_CONDITION("IN1",0x20,EQUALS,0x00) /* right Jump, non-cocktail start2 */
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL PORT_NAME("2P Jump") PORT_CONDITION("IN1",0x20,EQUALS,0x20) /* 2p Jump, cocktail */
PORT_START("IN1") /* IN1 */
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
@ -376,8 +376,8 @@ static INPUT_PORTS_START( ccastles )
PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 ) PORT_NAME("1P Start Cocktail") /* cocktail only */
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START2 ) PORT_NAME("2P Start Cocktail") /* cocktail only */
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 ) PORT_NAME("1P Start Cocktail") /* cocktail only */
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START2 ) PORT_NAME("2P Start Cocktail") /* cocktail only */
PORT_DIPNAME( 0x20, 0x00, DEF_STR( Cabinet ) )
PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
PORT_DIPSETTING( 0x20, DEF_STR( Cocktail ) )
@ -390,10 +390,10 @@ static INPUT_PORTS_START( ccastles )
PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(10) PORT_KEYDELTA(30)
PORT_START("LETA2")
PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_COCKTAIL PORT_SENSITIVITY(10) PORT_KEYDELTA(30) PORT_REVERSE /* cocktail only */
PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_COCKTAIL PORT_SENSITIVITY(10) PORT_KEYDELTA(30) PORT_REVERSE /* cocktail only */
PORT_START("LETA3")
PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_COCKTAIL PORT_SENSITIVITY(10) PORT_KEYDELTA(30) /* cocktail only */
PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_X ) PORT_COCKTAIL PORT_SENSITIVITY(10) PORT_KEYDELTA(30) /* cocktail only */
INPUT_PORTS_END

2
src/mame/drivers/coco12.cpp
View File

@ -470,4 +470,4 @@ COMP( 1985?, coco2b, coco, 0, coco2b, coco, driver_device,
COMP( 1984, cp400, coco, 0, cp400, coco, driver_device, 0, "Prologica", "CP400", 0)
COMP( 1984, lzcolor64, coco, 0, coco, coco, driver_device, 0, "Digiponto", "LZ Color64", 0)
COMP( 1984, mx1600, coco, 0, coco, coco, driver_device, 0, "Dynacom", "MX-1600", 0)
COMP( 1986, t4426, coco, 0, t4426, coco, driver_device, 0, "Terco AB", "Terco 4426 CNC Programming station", MACHINE_NOT_WORKING)
COMP( 1986, t4426, coco, 0, t4426, coco, driver_device, 0, "Terco AB", "Terco 4426 CNC Programming station", MACHINE_NOT_WORKING)

4
src/mame/drivers/fccpu30.cpp
View File

@ -699,7 +699,7 @@ static MACHINE_CONFIG_START (cpu30, cpu30_state)
MCFG_PIT68230_PB_OUTPUT_CB(WRITE8(cpu30_state, flop_dmac_w))
MCFG_PIT68230_PC_INPUT_CB(READ8(cpu30_state, pit1c_r))
MCFG_PIT68230_PC_OUTPUT_CB(WRITE8(cpu30_state, pit1c_w))
// MCFG_PIT68230_TIMER_IRQ_CB(DEVWRITELINE("fga002", fga002_device, lirq2_w)) // The timer interrupt seems to silence the terminal interrupt, needs invectigation
// MCFG_PIT68230_TIMER_IRQ_CB(DEVWRITELINE("fga002", fga002_device, lirq2_w)) // The timer interrupt seems to silence the terminal interrupt, needs invectigation
MCFG_DEVICE_ADD ("pit2", PIT68230, XTAL_16MHz / 2) // Th PIT clock is not verified on schema but reversed from behaviour
MCFG_PIT68230_PB_INPUT_CB(READ8(cpu30_state, board_mem_id_rd))
@ -707,7 +707,7 @@ static MACHINE_CONFIG_START (cpu30, cpu30_state)
MCFG_PIT68230_PA_OUTPUT_CB(WRITE8(cpu30_state, pit2a_w))
MCFG_PIT68230_PC_INPUT_CB(READ8(cpu30_state, pit2c_r))
MCFG_PIT68230_PC_OUTPUT_CB(WRITE8(cpu30_state, pit2c_w))
// MCFG_PIT68230_TIMER_IRQ_CB(DEVWRITELINE("fga002", fga002_device, lirq3_w)) // The timer interrupt seems to silence the terminal interrupt, needs invectigation
// MCFG_PIT68230_TIMER_IRQ_CB(DEVWRITELINE("fga002", fga002_device, lirq3_w)) // The timer interrupt seems to silence the terminal interrupt, needs invectigation
/* FGA-002, Force Gate Array */
MCFG_FGA002_ADD("fga002", 0)

14
src/mame/drivers/gkigt.cpp
View File

@ -79,8 +79,8 @@ PCB board that connects to 044 boards via J6 & J7
or 039 EPROM + SIMM software
More chips (from eBay auction):
2x Phillips / NXT 28C94 quad UART (8 serial channels total)
ADV476 256 color RAMDAC
2x Phillips / NXT 28C94 quad UART (8 serial channels total)
ADV476 256 color RAMDAC
*/
#include "emu.h"
@ -105,7 +105,7 @@ public:
DECLARE_READ32_MEMBER(igt_gk_28010008_r)
{
return rand(); // don't quite understand this one
return rand(); // don't quite understand this one
};
DECLARE_READ32_MEMBER(igt_gk_28030000_r)
@ -193,12 +193,12 @@ static ADDRESS_MAP_START( igt_gameking_mem, AS_PROGRAM, 32, igt_gameking_state )
AM_RANGE(0x10000000, 0x10ffffff) AM_RAM
AM_RANGE(0x18000000, 0x181fffff) AM_RAM // igtsc writes from 18000000 to 1817ffff, ms3 all the way to 181fffff.
AM_RANGE(0x18000000, 0x181fffff) AM_RAM // igtsc writes from 18000000 to 1817ffff, ms3 all the way to 181fffff.
// 28010000-2801007f: first 28C94 QUART
AM_RANGE(0x28010008, 0x2801000b) AM_READ(igt_gk_28010008_r)
AM_RANGE(0x28010030, 0x28010033) AM_READ(uart_status_r) // channel D
AM_RANGE(0x28010034, 0x28010037) AM_WRITE(uart_w) // channel D
AM_RANGE(0x28010030, 0x28010033) AM_READ(uart_status_r) // channel D
AM_RANGE(0x28010034, 0x28010037) AM_WRITE(uart_w) // channel D
// 28020000-2802007f: second 28C94 QUART
AM_RANGE(0x28030000, 0x28030003) AM_READ(igt_gk_28030000_r)
AM_RANGE(0x28040000, 0x2804ffff) AM_RAM
@ -206,7 +206,7 @@ static ADDRESS_MAP_START( igt_gameking_mem, AS_PROGRAM, 32, igt_gameking_state )
AM_RANGE(0x28060000, 0x28060003) AM_WRITE(clut_w)
AM_RANGE(0x28060004, 0x28060007) AM_WRITE(clut_mask_w)
AM_RANGE(0xa1000000, 0xa1011fff) AM_RAM // used by gkkey for restart IAC
AM_RANGE(0xa1000000, 0xa1011fff) AM_RAM // used by gkkey for restart IAC
ADDRESS_MAP_END

28
src/mame/drivers/guab.cpp
View File

@ -355,36 +355,36 @@ WRITE8_MEMBER( guab_state::output2_w )
{
output().set_value("led_8", BIT(data, 0));
output().set_value("led_9", BIT(data, 1));
output().set_value("led_10", BIT(data, 2)); // start (ten up: start)
output().set_value("led_10", BIT(data, 2)); // start (ten up: start)
output().set_value("led_11", BIT(data, 3)); // (ten up: feature 6)
output().set_value("led_12", BIT(data, 4)); // (ten up: feature 11)
output().set_value("led_13", BIT(data, 5)); // (ten up: feature 13)
output().set_value("led_14", BIT(data, 6)); // lamp a (ten up: feature 12)
output().set_value("led_15", BIT(data, 7)); // lamp b (ten up: pass)
output().set_value("led_14", BIT(data, 6)); // lamp a (ten up: feature 12)
output().set_value("led_15", BIT(data, 7)); // lamp b (ten up: pass)
}
WRITE8_MEMBER( guab_state::output3_w )
{
output().set_value("led_16", BIT(data, 0)); // select (ten up: collect)
output().set_value("led_16", BIT(data, 0)); // select (ten up: collect)
output().set_value("led_17", BIT(data, 1)); // (ten up: feature 14)
output().set_value("led_18", BIT(data, 2)); // (ten up: feature 9)
output().set_value("led_19", BIT(data, 3)); // (ten up: lamp a)
output().set_value("led_20", BIT(data, 4)); // lamp c (ten up: lamp b)
output().set_value("led_21", BIT(data, 5)); // lamp d (ten up: lamp c)
output().set_value("led_20", BIT(data, 4)); // lamp c (ten up: lamp b)
output().set_value("led_21", BIT(data, 5)); // lamp d (ten up: lamp c)
output().set_value("led_22", BIT(data, 6));
output().set_value("led_23", BIT(data, 7));
}
WRITE8_MEMBER( guab_state::output4_w )
{
output().set_value("led_24", BIT(data, 0)); // feature 1 (ten up: feature 1)
output().set_value("led_25", BIT(data, 1)); // feature 2 (ten up: feature 10)
output().set_value("led_26", BIT(data, 2)); // feature 3 (ten up: feature 7)
output().set_value("led_27", BIT(data, 3)); // feature 4 (ten up: feature 2)
output().set_value("led_28", BIT(data, 4)); // feature 5 (ten up: feature 8)
output().set_value("led_29", BIT(data, 5)); // feature 6 (ten up: feature 3)
output().set_value("led_30", BIT(data, 6)); // feature 7 (ten up: feature 4)
output().set_value("led_31", BIT(data, 7)); // feature 8 (ten up: feature 5)
output().set_value("led_24", BIT(data, 0)); // feature 1 (ten up: feature 1)
output().set_value("led_25", BIT(data, 1)); // feature 2 (ten up: feature 10)
output().set_value("led_26", BIT(data, 2)); // feature 3 (ten up: feature 7)
output().set_value("led_27", BIT(data, 3)); // feature 4 (ten up: feature 2)
output().set_value("led_28", BIT(data, 4)); // feature 5 (ten up: feature 8)
output().set_value("led_29", BIT(data, 5)); // feature 6 (ten up: feature 3)
output().set_value("led_30", BIT(data, 6)); // feature 7 (ten up: feature 4)
output().set_value("led_31", BIT(data, 7)); // feature 8 (ten up: feature 5)
}
WRITE8_MEMBER( guab_state::output5_w )

236
src/mame/drivers/hazeltin.cpp
View File

@ -34,7 +34,7 @@ References:
#include "netlist/devices/net_lib.h"
#define CPU_TAG "maincpu"
#define NETLIST_TAG "videobrd"
#define NETLIST_TAG "videobrd"
#define UART_TAG "uart"
#define BAUDGEN_TAG "baudgen"
#define KBDC_TAG "ay53600"
@ -44,16 +44,16 @@ References:
#define MISCKEYS_TAG "misc_keys"
#define SCREEN_TAG "screen"
#define BAUD_PROM_TAG "u39"
#define NL_PROM_TAG "videobrd:u71"
#define NL_EPROM_TAG "videobrd:u78"
#define VIDEO_PROM_TAG "u71"
#define CHAR_EPROM_TAG "u78"
#define VIDEO_OUT_TAG "videobrd:video_out"
#define VBLANK_OUT_TAG "videobrd:vblank"
#define NL_PROM_TAG "videobrd:u71"
#define NL_EPROM_TAG "videobrd:u78"
#define VIDEO_PROM_TAG "u71"
#define CHAR_EPROM_TAG "u78"
#define VIDEO_OUT_TAG "videobrd:video_out"
#define VBLANK_OUT_TAG "videobrd:vblank"
#define TVINTERQ_OUT_TAG "videobrd:tvinterq"
#define VIDEO_CLOCK (XTAL_33_264MHz/2)
#define VIDEOBRD_CLOCK (XTAL_33_264MHz*30)
#define VIDEO_CLOCK (XTAL_33_264MHz/2)
#define VIDEOBRD_CLOCK (XTAL_33_264MHz*30)
#define SR2_FULL_DUPLEX (0x01)
#define SR2_UPPER_ONLY (0x08)
@ -97,28 +97,28 @@ public:
, m_u27(*this, "videobrd:u27")
, m_u28(*this, "videobrd:u28")
, m_u29(*this, "videobrd:u29")
, m_cpu_db0(*this, "videobrd:cpu_db0")
, m_cpu_db1(*this, "videobrd:cpu_db1")
, m_cpu_db2(*this, "videobrd:cpu_db2")
, m_cpu_db3(*this, "videobrd:cpu_db3")
, m_cpu_db4(*this, "videobrd:cpu_db4")
, m_cpu_db5(*this, "videobrd:cpu_db5")
, m_cpu_db6(*this, "videobrd:cpu_db6")
, m_cpu_db7(*this, "videobrd:cpu_db7")
, m_cpu_ba4(*this, "videobrd:cpu_ba4")
, m_cpu_iowq(*this, "videobrd:cpu_iowq")
, m_video_out(*this, VIDEO_OUT_TAG)
, m_vblank_out(*this, VBLANK_OUT_TAG)
, m_tvinterq_out(*this, TVINTERQ_OUT_TAG)
, m_uart(*this, UART_TAG)
, m_cpu_db0(*this, "videobrd:cpu_db0")
, m_cpu_db1(*this, "videobrd:cpu_db1")
, m_cpu_db2(*this, "videobrd:cpu_db2")
, m_cpu_db3(*this, "videobrd:cpu_db3")
, m_cpu_db4(*this, "videobrd:cpu_db4")
, m_cpu_db5(*this, "videobrd:cpu_db5")
, m_cpu_db6(*this, "videobrd:cpu_db6")
, m_cpu_db7(*this, "videobrd:cpu_db7")
, m_cpu_ba4(*this, "videobrd:cpu_ba4")
, m_cpu_iowq(*this, "videobrd:cpu_iowq")
, m_video_out(*this, VIDEO_OUT_TAG)
, m_vblank_out(*this, VBLANK_OUT_TAG)
, m_tvinterq_out(*this, TVINTERQ_OUT_TAG)
, m_uart(*this, UART_TAG)
, m_kbdc(*this, KBDC_TAG)
, m_baud_dips(*this, BAUDPORT_TAG)
, m_baud_prom(*this, BAUD_PROM_TAG)
, m_misc_dips(*this, MISCPORT_TAG)
, m_kbd_misc_keys(*this, MISCKEYS_TAG)
, m_screen(*this, SCREEN_TAG)
, m_iowq_timer(nullptr)
, m_status_reg_3(0)
, m_iowq_timer(nullptr)
, m_status_reg_3(0)
, m_kbd_status_latch(0)
, m_refresh_address(0)
, m_screen_buf(nullptr)
@ -126,16 +126,16 @@ public:
, m_last_hpos(0)
, m_last_vpos(0)
, m_last_fraction(0.0)
{
{
}
virtual void machine_start() override;
virtual void machine_reset() override;
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
static const device_timer_id TIMER_IOWQ = 0;
static const device_timer_id TIMER_IOWQ = 0;
uint32_t screen_update_hazl1500(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
uint32_t screen_update_hazl1500(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
DECLARE_WRITE_LINE_MEMBER(com5016_fr_w);
@ -157,9 +157,9 @@ public:
DECLARE_WRITE8_MEMBER(refresh_address_w);
NETDEV_ANALOG_CALLBACK_MEMBER(video_out_cb);
NETDEV_ANALOG_CALLBACK_MEMBER(vblank_cb);
NETDEV_ANALOG_CALLBACK_MEMBER(tvinterq_cb);
NETDEV_ANALOG_CALLBACK_MEMBER(video_out_cb);
NETDEV_ANALOG_CALLBACK_MEMBER(vblank_cb);
NETDEV_ANALOG_CALLBACK_MEMBER(tvinterq_cb);
private:
required_device<cpu_device> m_maincpu;
@ -182,20 +182,20 @@ private:
required_device<netlist_ram_pointer_t> m_u27;
required_device<netlist_ram_pointer_t> m_u28;
required_device<netlist_ram_pointer_t> m_u29;
required_device<netlist_mame_logic_input_t> m_cpu_db0;
required_device<netlist_mame_logic_input_t> m_cpu_db1;
required_device<netlist_mame_logic_input_t> m_cpu_db2;
required_device<netlist_mame_logic_input_t> m_cpu_db3;
required_device<netlist_mame_logic_input_t> m_cpu_db4;
required_device<netlist_mame_logic_input_t> m_cpu_db5;
required_device<netlist_mame_logic_input_t> m_cpu_db6;
required_device<netlist_mame_logic_input_t> m_cpu_db7;
required_device<netlist_mame_logic_input_t> m_cpu_ba4;
required_device<netlist_mame_logic_input_t> m_cpu_iowq;
required_device<netlist_mame_analog_output_t> m_video_out;
required_device<netlist_mame_analog_output_t> m_vblank_out;
required_device<netlist_mame_analog_output_t> m_tvinterq_out;
required_device<ay31015_device> m_uart;
required_device<netlist_mame_logic_input_t> m_cpu_db0;
required_device<netlist_mame_logic_input_t> m_cpu_db1;
required_device<netlist_mame_logic_input_t> m_cpu_db2;
required_device<netlist_mame_logic_input_t> m_cpu_db3;
required_device<netlist_mame_logic_input_t> m_cpu_db4;
required_device<netlist_mame_logic_input_t> m_cpu_db5;
required_device<netlist_mame_logic_input_t> m_cpu_db6;
required_device<netlist_mame_logic_input_t> m_cpu_db7;
required_device<netlist_mame_logic_input_t> m_cpu_ba4;
required_device<netlist_mame_logic_input_t> m_cpu_iowq;
required_device<netlist_mame_analog_output_t> m_video_out;
required_device<netlist_mame_analog_output_t> m_vblank_out;
required_device<netlist_mame_analog_output_t> m_tvinterq_out;
required_device<ay31015_device> m_uart;
required_device<ay3600_device> m_kbdc;
required_ioport m_baud_dips;
required_region_ptr<uint8_t> m_baud_prom;
@ -204,16 +204,16 @@ private:
required_device<screen_device> m_screen;
emu_timer* m_iowq_timer;
emu_timer* m_iowq_timer;
uint8_t m_status_reg_3;
uint8_t m_status_reg_3;
uint8_t m_kbd_status_latch;
uint8_t m_refresh_address;
std::unique_ptr<float[]> m_screen_buf;
double m_last_beam;
double m_last_beam;
int m_last_hpos;
int m_last_vpos;
double m_last_fraction;
@ -223,10 +223,10 @@ void hazl1500_state::machine_start()
{
m_screen_buf = std::make_unique<float[]>(SCREEN_HTOTAL * SCREEN_VTOTAL);
m_iowq_timer = timer_alloc(TIMER_IOWQ);
m_iowq_timer->adjust(attotime::never);
m_iowq_timer = timer_alloc(TIMER_IOWQ);
m_iowq_timer->adjust(attotime::never);
save_item(NAME(m_status_reg_3));
save_item(NAME(m_status_reg_3));
save_item(NAME(m_kbd_status_latch));
save_item(NAME(m_refresh_address));
save_item(NAME(m_last_beam));
@ -243,8 +243,8 @@ void hazl1500_state::machine_reset()
void hazl1500_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
{
m_cpu_iowq->write(1);
m_cpu_ba4->write(1);
m_cpu_iowq->write(1);
m_cpu_ba4->write(1);
}
WRITE_LINE_MEMBER( hazl1500_state::com5016_fr_w )
@ -269,9 +269,9 @@ uint32_t hazl1500_state::screen_update_hazl1500(screen_device &screen, bitmap_rg
uint32_t *scanline = &bitmap.pix32(y);
pixindex = y * SCREEN_HTOTAL;
for (int x = 0; x < SCREEN_HTOTAL; x++)
//*scanline++ = 0xff000000 | (uint8_t(m_screen_buf[pixindex++] * 0.5) * 0x010101);
*scanline++ = 0xff000000 | (uint8_t(m_screen_buf[pixindex++] * 63.0) * 0x010101);
}
//*scanline++ = 0xff000000 | (uint8_t(m_screen_buf[pixindex++] * 0.5) * 0x010101);
*scanline++ = 0xff000000 | (uint8_t(m_screen_buf[pixindex++] * 63.0) * 0x010101);
}
return 0;
}
@ -297,11 +297,11 @@ READ8_MEMBER( hazl1500_state::ram_r )
WRITE8_MEMBER( hazl1500_state::ram_w )
{
uint8_t* chips[2][8] =
{
{ m_u29->ptr(), m_u28->ptr(), m_u27->ptr(), m_u26->ptr(), m_u25->ptr(), m_u24->ptr(), m_u23->ptr(), m_u22->ptr() },
{ m_u16->ptr(), m_u15->ptr(), m_u14->ptr(), m_u13->ptr(), m_u12->ptr(), m_u11->ptr(), m_u10->ptr(), m_u9->ptr() }
};
uint8_t* chips[2][8] =
{
{ m_u29->ptr(), m_u28->ptr(), m_u27->ptr(), m_u26->ptr(), m_u25->ptr(), m_u24->ptr(), m_u23->ptr(), m_u22->ptr() },
{ m_u16->ptr(), m_u15->ptr(), m_u14->ptr(), m_u13->ptr(), m_u12->ptr(), m_u11->ptr(), m_u10->ptr(), m_u9->ptr() }
};
int bank = ((offset & 0x400) != 0 ? 1 : 0);
const int byte_pos = (offset >> 3) & 0x7f;
@ -388,30 +388,30 @@ WRITE_LINE_MEMBER(hazl1500_state::ay3600_data_ready_w)
NETDEV_ANALOG_CALLBACK_MEMBER(hazl1500_state::vblank_cb)
{
synchronize();
if (int(data) > 1)
{
m_kbd_status_latch &= ~KBD_STATUS_TV_UB;
}
else
{
m_kbd_status_latch |= KBD_STATUS_TV_UB;
}
synchronize();
if (int(data) > 1)
{
m_kbd_status_latch &= ~KBD_STATUS_TV_UB;
}
else
{
m_kbd_status_latch |= KBD_STATUS_TV_UB;
}
}
NETDEV_ANALOG_CALLBACK_MEMBER(hazl1500_state::tvinterq_cb)
{
synchronize();
if (int(data) > 1)
{
m_kbd_status_latch &= ~KBD_STATUS_TV_INT;
m_maincpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
}
else
{
m_kbd_status_latch |= KBD_STATUS_TV_INT;
m_maincpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
}
synchronize();
if (int(data) > 1)
{
m_kbd_status_latch &= ~KBD_STATUS_TV_INT;
m_maincpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
}
else
{
m_kbd_status_latch |= KBD_STATUS_TV_INT;
m_maincpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
}
}
NETDEV_ANALOG_CALLBACK_MEMBER(hazl1500_state::video_out_cb)
@ -426,8 +426,8 @@ NETDEV_ANALOG_CALLBACK_MEMBER(hazl1500_state::video_out_cb)
pixel_index -= 16; // take back 16 clock cycles to honor the circuitry god whose ark this is
if (pixel_index < 0)
{
m_last_beam = float(data);
m_last_hpos = 0;
m_last_beam = float(data);
m_last_hpos = 0;
m_last_vpos = 0;
m_last_fraction = 0.0;
return;
@ -447,27 +447,27 @@ NETDEV_ANALOG_CALLBACK_MEMBER(hazl1500_state::video_out_cb)
m_screen_buf[last_index++] = float(m_last_beam);
}
m_last_beam = float(data);
m_last_hpos = hpos;
m_last_beam = float(data);
m_last_hpos = hpos;
m_last_vpos = vpos;
m_last_fraction = pixel_fraction;
}
WRITE8_MEMBER(hazl1500_state::refresh_address_w)
{
synchronize();
//printf("refresh: %02x, %d, %d\n", data, m_screen->hpos(), m_screen->vpos());
m_iowq_timer->adjust(attotime::from_hz(XTAL_18MHz/9));
m_cpu_iowq->write(0);
m_cpu_ba4->write(0);
m_cpu_db0->write((data >> 0) & 1);
m_cpu_db1->write((data >> 1) & 1);
m_cpu_db2->write((data >> 2) & 1);
m_cpu_db3->write((data >> 3) & 1);
m_cpu_db4->write((data >> 4) & 1);
m_cpu_db5->write((data >> 5) & 1);
m_cpu_db6->write((data >> 6) & 1);
m_cpu_db7->write((data >> 7) & 1);
synchronize();
//printf("refresh: %02x, %d, %d\n", data, m_screen->hpos(), m_screen->vpos());
m_iowq_timer->adjust(attotime::from_hz(XTAL_18MHz/9));
m_cpu_iowq->write(0);
m_cpu_ba4->write(0);
m_cpu_db0->write((data >> 0) & 1);
m_cpu_db1->write((data >> 1) & 1);
m_cpu_db2->write((data >> 2) & 1);
m_cpu_db3->write((data >> 3) & 1);
m_cpu_db4->write((data >> 4) & 1);
m_cpu_db5->write((data >> 5) & 1);
m_cpu_db6->write((data >> 6) & 1);
m_cpu_db7->write((data >> 7) & 1);
}
static ADDRESS_MAP_START(hazl1500_mem, AS_PROGRAM, 8, hazl1500_state)
@ -694,12 +694,12 @@ static MACHINE_CONFIG_START( hazl1500, hazl1500_state )
/* video hardware */
MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)
MCFG_SCREEN_UPDATE_DRIVER(hazl1500_state, screen_update_hazl1500)
//MCFG_SCREEN_RAW_PARAMS(XTAL_33_264MHz / 2,
// SCREEN_HTOTAL, SCREEN_HSTART, SCREEN_HSTART + SCREEN_HDISP,
// SCREEN_VTOTAL, SCREEN_VSTART, SCREEN_VSTART + SCREEN_VDISP); // TODO: Figure out exact visibility
MCFG_SCREEN_RAW_PARAMS(XTAL_33_264MHz / 2,
SCREEN_HTOTAL, 0, SCREEN_HTOTAL,
SCREEN_VTOTAL, 0, SCREEN_VTOTAL);
//MCFG_SCREEN_RAW_PARAMS(XTAL_33_264MHz / 2,
// SCREEN_HTOTAL, SCREEN_HSTART, SCREEN_HSTART + SCREEN_HDISP,
// SCREEN_VTOTAL, SCREEN_VSTART, SCREEN_VSTART + SCREEN_VDISP); // TODO: Figure out exact visibility
MCFG_SCREEN_RAW_PARAMS(XTAL_33_264MHz / 2,
SCREEN_HTOTAL, 0, SCREEN_HTOTAL,
SCREEN_VTOTAL, 0, SCREEN_VTOTAL);
MCFG_PALETTE_ADD_MONOCHROME("palette")
MCFG_GFXDECODE_ADD("gfxdecode", "palette", hazl1500)
@ -735,20 +735,20 @@ static MACHINE_CONFIG_START( hazl1500, hazl1500_state )
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u15", "u15")
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u16", "u16")
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_iowq", "cpu_iowq.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_ba4", "cpu_ba4.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db0", "cpu_db0.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db1", "cpu_db1.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db2", "cpu_db2.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db3", "cpu_db3.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db4", "cpu_db4.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db5", "cpu_db5.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db6", "cpu_db6.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db7", "cpu_db7.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_iowq", "cpu_iowq.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_ba4", "cpu_ba4.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db0", "cpu_db0.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db1", "cpu_db1.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db2", "cpu_db2.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db3", "cpu_db3.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db4", "cpu_db4.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db5", "cpu_db5.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db6", "cpu_db6.IN", 0)
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db7", "cpu_db7.IN", 0)
MCFG_NETLIST_ANALOG_OUTPUT(NETLIST_TAG, "video_out", "video_out", hazl1500_state, video_out_cb, "")
MCFG_NETLIST_ANALOG_OUTPUT(NETLIST_TAG, "vblank", "vblank", hazl1500_state, vblank_cb, "")
MCFG_NETLIST_ANALOG_OUTPUT(NETLIST_TAG, "tvinterq", "tvinterq", hazl1500_state, tvinterq_cb, "")
MCFG_NETLIST_ANALOG_OUTPUT(NETLIST_TAG, "video_out", "video_out", hazl1500_state, video_out_cb, "")
MCFG_NETLIST_ANALOG_OUTPUT(NETLIST_TAG, "vblank", "vblank", hazl1500_state, vblank_cb, "")
MCFG_NETLIST_ANALOG_OUTPUT(NETLIST_TAG, "tvinterq", "tvinterq", hazl1500_state, tvinterq_cb, "")
/* keyboard controller */
MCFG_DEVICE_ADD(KBDC_TAG, AY3600, 0)

12
src/mame/drivers/lwriter.cpp
View File

@ -5,7 +5,7 @@
Apple LaserWriter II NT driver
TODO:
- Figure out what VIA pins is connected to switch on front that selects LocalTalk
- Figure out what VIA pins is connected to switch on front that selects LocalTalk
- Let the board identify itself to a emulated mac driver so it displays the printer icon on the desktop
- Everything else
@ -13,11 +13,11 @@
/*
* Hardware: 68000@11.16 MHz
8530 SCC
6523 TPI or 6522 VIA on newer pcb:s
2MB DRAM
2KB SRAM
custom 335-0022 EEPROM
1MB ROM
6523 TPI or 6522 VIA on newer pcb:s
2MB DRAM
2KB SRAM
custom 335-0022 EEPROM
1MB ROM
+------------------------------------------------------------------------------------------------------------------------+=====+
| 1 2 3 4 5 6 7 8 9 10 11 | #

28
src/mame/drivers/mac128.cpp Executable file → Normal file
View File

@ -1517,7 +1517,7 @@ ROM_START( mac128k )
ROM_REGION16_BE(0x100000, "bootrom", 0)
// Apple used at least 3 manufacturers for these ROMs, but they're always Apple part numbers 342-0220-A and 342-0221-A
ROMX_LOAD("342-0220-a.u6d", 0x00000, 0x08000, CRC(198210ad) SHA1(2590ff4af5ac0361babdf0dc5da18e2eecad454a), ROM_SKIP(1) )
ROMX_LOAD("342-0221-a.u8d", 0x00001, 0x08000, CRC(fd2665c2) SHA1(8507932a854bd28196a17785c8b1851cb53eaf64), ROM_SKIP(1) )
ROMX_LOAD("342-0221-a.u8d", 0x00001, 0x08000, CRC(fd2665c2) SHA1(8507932a854bd28196a17785c8b1851cb53eaf64), ROM_SKIP(1) )
/* Labels seen in the wild:
VTi:
"<VTi logo along side> // 416 VH 2605 // 23256-1020 // 342-0220-A // (C)APPLE 83 // KOREA-AE"
@ -1624,21 +1624,21 @@ ROM_START( mac512ke ) // 512ke has been observed with any of the v3, v2 or v1 ma
*/
/* Labels seen in the wild:
v3/4d1f8172:
'ROM-HI' @ U6D:
"VLSI // 740 SA 1262 // 23512-1054 // 342-0341-C // (C)APPLE '83-'86 // KOREA A"
"342-0341-C // (C)APPLE 85,86 // (M)AMI 8849MBL // PHILLIPINES"
'ROM-LO' @ U8D:
"VLSI // 740 SA 1342 // 23512-1055 // 342-0342-B // (C)APPLE '83-'86 // KOREA A"
"<VLSI logo>VLSI // 8905AV 0 AS759 // 23512-1055 // 342-0342-B // (C)APPLE '85-'86"
'ROM-HI' @ U6D:
"VLSI // 740 SA 1262 // 23512-1054 // 342-0341-C // (C)APPLE '83-'86 // KOREA A"
"342-0341-C // (C)APPLE 85,86 // (M)AMI 8849MBL // PHILLIPINES"
'ROM-LO' @ U8D:
"VLSI // 740 SA 1342 // 23512-1055 // 342-0342-B // (C)APPLE '83-'86 // KOREA A"
"<VLSI logo>VLSI // 8905AV 0 AS759 // 23512-1055 // 342-0342-B // (C)APPLE '85-'86"
v2/4d1eeae1:
'ROM-HI' @ U6D:
"VTI // 624 V0 8636 // 23512-1010 // 342-0341-B // (C)APPLE '85 // MEXICO R"
'ROM-LO' @ U8D:
"VTI // 622 V0 B637 // 23512-1007 // 342-0342-A // (C)APPLE '83-'85 // KOREA A"
'ROM-HI' @ U6D:
"VTI // 624 V0 8636 // 23512-1010 // 342-0341-B // (C)APPLE '85 // MEXICO R"
'ROM-LO' @ U8D:
"VTI // 622 V0 B637 // 23512-1007 // 342-0342-A // (C)APPLE '83-'85 // KOREA A"
v1/4d1eeee1:
'ROM-HI' @ U6D:
GUESSED, since this ROM is very rare: "VTI // 62? V0 86?? // 23512-1008 // 342-0341-A // (C)APPLE '83-'85 // KOREA A"
'ROM-LO' @ U8D is same as v2/4d1eeae1 'ROM-LO' @ U8D
'ROM-HI' @ U6D:
GUESSED, since this ROM is very rare: "VTI // 62? V0 86?? // 23512-1008 // 342-0341-A // (C)APPLE '83-'85 // KOREA A"
'ROM-LO' @ U8D is same as v2/4d1eeae1 'ROM-LO' @ U8D
*/
ROM_END

6
src/mame/drivers/micro20.cpp Executable file → Normal file
View File

@ -22,9 +22,9 @@
#define MAINCPU_TAG "maincpu"
#define DUART_A_TAG "duarta"
#define DUART_B_TAG "duartb"
#define RTC_TAG "rtc"
#define FDC_TAG "fdc"
#define PIT_TAG "pit"
#define RTC_TAG "rtc"
#define FDC_TAG "fdc"
#define PIT_TAG "pit"
class micro20_state : public driver_device
{

40
src/mame/drivers/model1.cpp
View File

@ -1683,28 +1683,28 @@ READ16_MEMBER(model1_state::r360_r)
WRITE16_MEMBER(model1_state::r360_w)
{
/*
this uses the feedback board protocol
command group B - these seem to be gamestates
this uses the feedback board protocol
command group B - these seem to be gamestates
bf = init
be = attract
bd = setup #1 (lower safety bar etc.)
bc = setup #2 (push emergency button)
bb = ready to go
ba = ingame
b9 = game over
bf = init
be = attract
bd = setup #1 (lower safety bar etc.)
bc = setup #2 (push emergency button)
bb = ready to go
ba = ingame
b9 = game over
results:
40 = default status
41 = * (setup #1 ack)
42 = lowered safety bar
43 = closed belt
44 = lever up
45 = pushed button
46 = game start
47 = game over
48 = lever down
49 = released belt
results:
40 = default status
41 = * (setup #1 ack)
42 = lowered safety bar
43 = closed belt
44 = lever up
45 = pushed button
46 = game start
47 = game over
48 = lever down
49 = released belt
*/
switch (data & 0xff)
{

10
src/mame/drivers/model2.cpp
View File

@ -773,7 +773,7 @@ READ32_MEMBER(model2_state::copro_fifo_r)
else
{
// TODO
// printf("FIFO OUT read\n");
// printf("FIFO OUT read\n");
if (m_tgpx4->is_fifoout0_empty())
{
/* Reading from empty FIFO causes the i960 to enter wait state */
@ -840,7 +840,7 @@ WRITE32_MEMBER(model2_state::copro_fifo_w)
}
else
{
// printf("push %08X at %08X\n", data, space.device().safe_pc());
// printf("push %08X at %08X\n", data, space.device().safe_pc());
m_tgpx4->fifoin_w(data);
}
}
@ -3167,7 +3167,7 @@ ROM_START( srallycdx ) /* Sega Rally Championship DX Revision A, Model 2A - Sing
ROM_LOAD32_WORD( "mpr-17747.11", 0x000002, 0x200000, CRC(543593fd) SHA1(5ba63a77e9fc70569af21d50b3171bc8ff4522b8) )
ROM_LOAD32_WORD( "mpr-17744.8", 0x400000, 0x200000, CRC(71fed098) SHA1(1d187cad375121a45348d640edd3cc7dce658d28) )
ROM_LOAD32_WORD( "mpr-17745.9", 0x400002, 0x200000, CRC(8ecca705) SHA1(ed2b3298aad6f4e52dc672a0168183e457564b43) )
ROM_LOAD32_WORD( "mpr-17764a.6", 0x800000, 0x200000, CRC(dcb91e31) SHA1(2725268e97b9f4c14d56c040af38bc82f5020e3e) ) // IC 6 and 7 likely EPROMs
ROM_LOAD32_WORD( "mpr-17764a.6", 0x800000, 0x200000, CRC(dcb91e31) SHA1(2725268e97b9f4c14d56c040af38bc82f5020e3e) ) // IC 6 and 7 likely EPROMs
ROM_LOAD32_WORD( "mpr-17765a.7", 0x800002, 0x200000, CRC(b657dc48) SHA1(ae0f1bc6e2479fa51ca36f8be3a1785981c4dfe9) )
ROM_REGION( 0x800000, "tgp", 0 ) // TGP program? (COPRO socket)
@ -3221,8 +3221,8 @@ ROM_START( srallycdxa ) // Sega Rally Championship DX, Model 2A? - Single player
ROM_LOAD32_WORD( "epr-17765.7", 0x800002, 0x100000, CRC(81112ea5) SHA1(a0251b4f5f18ae2e2d0576087a687dd7c2e49c34) ) // NEC D27C8000D EPROM
ROM_REGION( 0x800000, "tgp", 0 ) // TGP program? (COPRO socket)
ROM_LOAD32_WORD( "mpr-17754.28", 0x000000, 0x200000, CRC(81a84f67) SHA1(c0a9b690523a529e4015e9af10dc3fb2a1726f08) ) // not present in this rev memory test, why ?
ROM_LOAD32_WORD( "mpr-17755.29", 0x000002, 0x200000, CRC(2a6e7da4) SHA1(e60803ae951489fe47d66731d15c32249ca547b4) ) //
ROM_LOAD32_WORD( "mpr-17754.28", 0x000000, 0x200000, CRC(81a84f67) SHA1(c0a9b690523a529e4015e9af10dc3fb2a1726f08) ) // not present in this rev memory test, why ?
ROM_LOAD32_WORD( "mpr-17755.29", 0x000002, 0x200000, CRC(2a6e7da4) SHA1(e60803ae951489fe47d66731d15c32249ca547b4) ) //
ROM_REGION( 0x010000, "drivecpu", 0 ) // Drive I/O program
ROM_LOAD( "epr-17762.ic12", 0x000000, 0x010000, NO_DUMP ) /* Need to verify actual EPR-xxxx number, might be EPR-17759 */

2
src/mame/drivers/nmk16.cpp
View File

@ -1134,7 +1134,7 @@ static ADDRESS_MAP_START( atombjt_map, AS_PROGRAM, 16, nmk16_state )
AM_RANGE(0x0c2014, 0x0c2015) AM_READ(atombjt_unkr_r)
AM_RANGE(0x0c2016, 0x0c2017) AM_READ_PORT("DSW1")
AM_RANGE(0x0c2018, 0x0c2019) AM_READ_PORT("DSW2")
// AM_RANGE(0x0c201c, 0x0c201d) // oki banking related?
// AM_RANGE(0x0c201c, 0x0c201d) // oki banking related?
AM_RANGE(0x0c201e, 0x0c201f) AM_DEVREADWRITE8("oki1", okim6295_device, read, write, 0x00ff)
AM_RANGE(0x0f0000, 0x0fffff) AM_RAM AM_SHARE("mainram")
AM_RANGE(0x100000, 0x101fff) AM_RAM

18
src/mame/drivers/pgm3.cpp
View File

@ -22,12 +22,12 @@
Offset(h) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
0C2000000 EB 3C 90 6D 6B 64 6F 73 66 73 00 00 02 04 04 00 ë<.mkdosfs......
0C2000010 02 00 02 00 00 F8 00 01 3F 00 FF 00 00 00 00 00 .....ø..?.ÿ.....
0C2000020 00 00 04 00 00 00 29 4C 88 BA 7C 20 20 20 20 20 ......)Lˆº|
0C2000000 EB 3C 90 6D 6B 64 6F 73 66 73 00 00 02 04 04 00 ë<.mkdosfs......
0C2000010 02 00 02 00 00 F8 00 01 3F 00 FF 00 00 00 00 00 .....ø..?.ÿ.....
0C2000020 00 00 04 00 00 00 29 4C 88 BA 7C 20 20 20 20 20 ......)L.º|
0C2000030 20 20 20 20 20 20 46 41 54 31 36 20 20 20 0E 1F FAT16 ..
0C2000040 BE 5B 7C AC 22 C0 74 0B 56 B4 0E BB 07 00 CD 10 ¾[|¬"Àt.V´.»..Í.
0C2000050 5E EB F0 32 E4 CD 16 CD 19 EB FE 54 68 69 73 20 ^ëð2äÍ.Í.ëþThis
0C2000040 BE 5B 7C AC 22 C0 74 0B 56 B4 0E BB 07 00 CD 10 ¾[|¬"Àt.V´.»..Í.
0C2000050 5E EB F0 32 E4 CD 16 CD 19 EB FE 54 68 69 73 20 ^ëð2äÍ.Í.ëþThis
0C2000060 69 73 20 6E 6F 74 20 61 20 62 6F 6F 74 61 62 6C is not a bootabl
0C2000070 65 20 64 69 73 6B 2E 20 20 50 6C 65 61 73 65 20 e disk. Please
0C2000080 69 6E 73 65 72 74 20 61 20 62 6F 6F 74 61 62 6C insert a bootabl
@ -41,10 +41,10 @@
DSW:
1: OFF = Game mode / ON = Test mode
2: OFF = JAMMA / ON = JVS
3: OFF = 16/9 (1280x720) / ON = 4/3 (800x600)
4: NO USE
1: OFF = Game mode / ON = Test mode
2: OFF = JAMMA / ON = JVS
3: OFF = 16/9 (1280x720) / ON = 4/3 (800x600)
4: NO USE
todo: add other hardware details?

2
src/mame/drivers/playmark.cpp
View File

@ -1307,7 +1307,7 @@ static MACHINE_CONFIG_START( wbeachvl, playmark_state )
MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
MCFG_PIC16C5x_WRITE_C_CB(WRITE8(playmark_state, playmark_snd_control_w))
// MCFG_PIC16C5x_WRITE_C_CB(WRITE8(playmark_state, hrdtimes_snd_control_w)) // probably closer to this, but this only supports 2 sample bank bits
// MCFG_PIC16C5x_WRITE_C_CB(WRITE8(playmark_state, hrdtimes_snd_control_w)) // probably closer to this, but this only supports 2 sample bank bits
MCFG_PIC16C5x_T0_CB(READLINE(playmark_state, PIC16C5X_T0_clk_r))
MCFG_EEPROM_SERIAL_93C46_ADD("eeprom")

16
src/mame/drivers/rainbow.cpp
View File

@ -61,7 +61,7 @@ To obtain pixel exact graphics use 'Graphics Only' in Video Options plus comman
Programs with initialization / redraw / reentrance problems (invocation order after reset matters in emulation):
- CANON (high resolution + vectors), Solitaire (SOLIT.EXE) and GDEMO (from GRPHCS.ARC, interactive graphics interpreter '85),
plus 'Monitor Aligment' (from the GDC test disk). Sloppy programming or a bug related to a) to e)...?
plus 'Monitor Aligment' (from the GDC test disk). Sloppy programming or a bug related to a) to e)...?
Quote from Haze: "if you have 2 screens running at different refresh rates one of them won't update properly
(the partial update system gets very confused because it expects both the screens to end at the same time
@ -329,7 +329,7 @@ W17 pulls J1 serial port pin 1 to GND when set (chassis to logical GND).
#define OLD_RAM_BOARD_PRESENT
#else
#define RTC_BASE 0xFC000 // (default configuration, also covers FE000+)
// #define RTC_BASE 0xF4000 // (alternate configuration) - ClikClok V1.0 / CLIKF4.COM
// #define RTC_BASE 0xF4000 // (alternate configuration) - ClikClok V1.0 / CLIKF4.COM
// DEC-100-B probes until a 'flaky' area is found (BOOT ROM around F400:0E04).
// It is no longer possible to key in the RAM size from within the 100-B BIOS.
@ -725,10 +725,10 @@ private:
// THIS MACRO * RESETS * the PATTERN TO DEFAULT.
// NOTE 2: m_patmult MUST BE LOADED BEFORE !!
#define OPTION_RESET_PATTERNS \
m_vpat = 0xff; \
m_vpat = 0xff; \
if(m_patmult == 0) m_patmult = 0x01;\
if(m_patcnt == 0) m_patcnt = m_patmult;\
if(m_patidx == 0) m_patidx = 7;
if(m_patidx == 0) m_patidx = 7;
// GDC RESET MACRO - used in "machine_reset" & GDC_EXTRA_REGISTER_w !
@ -741,11 +741,11 @@ m_color_map_changed = true; \
for(int i=0; i <256; i++) { m_GDC_SCROLL_BUFFER[i] = i; }; \
m_GDC_scroll_index = 0; \
m_GDC_write_buffer_index = 0; \
m_GDC_WRITE_MASK = 0x00; \
m_GDC_WRITE_MASK = 0x00; \
m_GDC_ALU_PS_REGISTER = 0x0F; \
m_GDC_FG_BG = 0xF0; \
m_GDC_MODE_REGISTER &= GDC_MODE_VECTOR | GDC_MODE_HIGHRES | GDC_MODE_ENABLE_WRITES | GDC_MODE_READONLY_SCROLL_MAP;\
m_GDC_MODE_REGISTER |= GDC_MODE_ENABLE_VIDEO; \
m_GDC_MODE_REGISTER |= GDC_MODE_ENABLE_VIDEO; \
printf("\n** OPTION GRFX. RESET **\n");
UPD7220_DISPLAY_PIXELS_MEMBER( rainbow_state::hgdc_display_pixels )
@ -1470,7 +1470,7 @@ WRITE8_MEMBER(rainbow_state::ext_ram_w)
// Version for 100-A plugs into NVRAM chip socket. There is a socket on the ClikClok for the NVRAM
// Requires a short program from the Suitable Solutions ClikClok distribution disk (CLIKA.COM)
// - also needed to set time/date (*). Reads $ed000, writes ed0fe/ed0ff.
// - also needed to set time/date (*). Reads $ed000, writes ed0fe/ed0ff.
WRITE8_MEMBER(rainbow_state::rtc_w)
{
if((m_inp11->read() == 0x01)) // if enabled...
@ -2237,7 +2237,7 @@ READ8_MEMBER(rainbow_state::z80_generalstat_r)
int fdc_write_gate = 0;
int last_dir = 0;
// printf("\nFLOPPY %02d - ", m_unit);
// printf("\nFLOPPY %02d - ", m_unit);
if (m_fdc)
{
track = m_fdc->track_r(space, 0);

2
src/mame/drivers/segas16b.cpp
View File

@ -6459,7 +6459,7 @@ ROM_START( goldnaxe2 )
difficult.
Calculated checksum: 5F8F
 File checksum: 5E8F */
 File checksum: 5E8F */
ROM_LOAD( "317-0112.c2", 0x00000, 0x1000, BAD_DUMP CRC(d8f2f1c0) SHA1(04594ed5558af63cde62de6cc4020b35b8a5889e) )
ROM_END

2
src/mame/drivers/seta.cpp
View File

@ -2003,7 +2003,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( zombraid_map, AS_PROGRAM, 16, seta_state )
AM_IMPORT_FROM( wrofaero_map )
AM_RANGE(0x300000, 0x30ffff) AM_RAM AM_SHARE("nvram") // actually 8K x8 SRAM
AM_RANGE(0x300000, 0x30ffff) AM_RAM AM_SHARE("nvram") // actually 8K x8 SRAM
ADDRESS_MAP_END
READ16_MEMBER(seta_state::zingzipbl_unknown_r)

28
src/mame/drivers/shootout.cpp
View File

@ -16,9 +16,9 @@
strangely features the same encryption as used on the DE-0219 board. It
also has some edited graphics.
The DE-0219 PCB seems to have only one 12 MHz XTAL, some images with recognizable XTAL value can be found here:
- http://www.jammarcade.net/images/2016/04/Shootout.jpg
- http://thumbs.picclick.com/00/s/MTIwMFgxNjAw/z/7iIAAOSw5ClXxbrB/$/Data-East-Shootout-Arcade-Video-Game-Pcb-Circuit-_57.jpg
The DE-0219 PCB seems to have only one 12 MHz XTAL, some images with recognizable XTAL value can be found here:
- http://www.jammarcade.net/images/2016/04/Shootout.jpg
- http://thumbs.picclick.com/00/s/MTIwMFgxNjAw/z/7iIAAOSw5ClXxbrB/$/Data-East-Shootout-Arcade-Video-Game-Pcb-Circuit-_57.jpg
Driver by:
@ -29,8 +29,8 @@
TODO:
- Lots of unmapped memory reads and writes (sprram or vram mirrors, perhaps...), bg_vram is also read.
- Does the korean bootleg really have the DECO 222 CPU? I think it should use the shootclr.003 prom to decrypt the opcodes.
Something like -> rom [addr] = (rom [addr] & 0x0F) | proms [rom [addr] >> 4]]);
- Does the korean bootleg really have the DECO 222 CPU? I think it should use the shootclr.003 prom to decrypt the opcodes.
Something like -> rom [addr] = (rom [addr] & 0x0F) | proms [rom [addr] >> 4]]);
*******************************************************************************/
@ -76,15 +76,15 @@ WRITE8_MEMBER(shootout_state::flipscreen_w)
}
/*
This is actually a double BCD counter (2 BCD digits packet in a byte)...
The first write is always 0x40, then when a coin is inserted it starts to count from 0x01 up to 0x99.
When it reaches 99 credits, 0x99 is always written...
This is actually a double BCD counter (2 BCD digits packet in a byte)...
The first write is always 0x40, then when a coin is inserted it starts to count from 0x01 up to 0x99.
When it reaches 99 credits, 0x99 is always written...
On the shootoutj and shootoutb sets, it works as above but it counts up to 0x09 instead of 0x99 (Single BCD digit).
On the shootoutj and shootoutb sets, it works as above but it counts up to 0x09 instead of 0x99 (Single BCD digit).
Note:
This should be an input for a BCD to 7-segment decoder (e.g. a 74LS47), but all the PCBs I've seen don't have 'onboard'
display(s), so this was implemented as normal "coin counter" (after all, they both have the same goal: count credits ;))
Note:
This should be an input for a BCD to 7-segment decoder (e.g. a 74LS47), but all the PCBs I've seen don't have 'onboard'
display(s), so this was implemented as normal "coin counter" (after all, they both have the same goal: count credits ;))
*/
WRITE8_MEMBER(shootout_state::coincounter_w)
{
@ -282,7 +282,7 @@ static MACHINE_CONFIG_START( shootout, shootout_state )
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
// Guessed parameters based on the 12 MHz XTAL, but they seem resonable (TODO: Real PCB measurements)
// Guessed parameters based on the 12 MHz XTAL, but they seem resonable (TODO: Real PCB measurements)
MCFG_SCREEN_RAW_PARAMS (XTAL_12MHz / 2, 384, 0, 256, 262, 8, 248)
MCFG_SCREEN_UPDATE_DRIVER(shootout_state, screen_update_shootout)
@ -312,7 +312,7 @@ static MACHINE_CONFIG_START( shootouj, shootout_state )
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
// Guessed parameters based on the 12 MHz XTAL, but they seem resonable (TODO: Real PCB measurements)
// Guessed parameters based on the 12 MHz XTAL, but they seem resonable (TODO: Real PCB measurements)
MCFG_SCREEN_RAW_PARAMS (XTAL_12MHz / 2, 384, 0, 256, 262, 8, 248)
MCFG_SCREEN_UPDATE_DRIVER(shootout_state, screen_update_shootouj)

4
src/mame/drivers/tail2nos.cpp
View File

@ -55,8 +55,8 @@ static ADDRESS_MAP_START( main_map, AS_PROGRAM, 16, tail2nos_state )
AM_RANGE(0xfff002, 0xfff003) AM_READ_PORT("IN1")
AM_RANGE(0xfff004, 0xfff005) AM_READ_PORT("DSW")
AM_RANGE(0xfff008, 0xfff009) AM_READWRITE8(sound_semaphore_r,sound_command_w,0x00ff)
// AM_RANGE(0xfff020, 0xfff023) V-System CRTC
// AM_RANGE(0xfff030, 0xfff031) link comms
// AM_RANGE(0xfff020, 0xfff023) V-System CRTC
// AM_RANGE(0xfff030, 0xfff031) link comms
ADDRESS_MAP_END
static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, tail2nos_state )

2
src/mame/drivers/tmnt.cpp
View File

@ -1696,7 +1696,7 @@ static INPUT_PORTS_START( ssriders )
INPUT_PORTS_END
static INPUT_PORTS_START( ssridr4p )
PORT_INCLUDE( ssriders )
PORT_INCLUDE( ssriders )
PORT_MODIFY("COINS")
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 )

78
src/mame/drivers/tnzs.cpp
View File

@ -763,8 +763,8 @@ static ADDRESS_MAP_START( tnzs_sub_map, AS_PROGRAM, 8, tnzs_mcu_state )
AM_RANGE(0xc000, 0xc001) AM_READWRITE(mcu_r, mcu_w) /* not present in insectx */
AM_RANGE(0xa000, 0xa000) AM_WRITE(bankswitch1_w)
AM_RANGE(0xf000, 0xf003) AM_READ(analog_r) /* paddles in arkanoid2/plumppop. The ports are */
/* read but not used by the other games, and are not read at */
/* all by insectx. */
/* read but not used by the other games, and are not read at */
/* all by insectx. */
AM_IMPORT_FROM(base_sub_map)
ADDRESS_MAP_END
@ -1697,49 +1697,49 @@ MACHINE_CONFIG_END
PCBs
***************************************************************************/
/* The TNZS/Seta hardware has a variety of somewhat different pcbs, all of
which have both Seta and Taito Part numbers.
All pcbs have Z80B processors and one 6264 mainram chip and an X1-001
and X1-002 video chip and an X1-004 I/O? Chip, and four PALs
/* The TNZS/Seta hardware has a variety of somewhat different pcbs, all of
which have both Seta and Taito Part numbers.
All pcbs have Z80B processors and one 6264 mainram chip and an X1-001
and X1-002 video chip and an X1-004 I/O? Chip, and four PALs
Seta# Taito#s CPUS RxM2 ROM1 MCU? Video ram PROMs SETA X1 GFXROMs QUADRATURE ESD. PROT Games Picture
P0-022-A K1100245A J1100108A 2xZ80B 512/256 512/256 8042 4x6116 Yes, 2 03 23c1000 uPD4701AC 3x X2-003 arkanoid2, plumppop(A) http://www.classicarcaderesource.com/RevengeOfDoh3.jpg
P0-025-A K1100241A J1100107A 2xZ80B 512/256 512/256 8042 4x6116 Yes, 2 03 23c1000 N/A 3x X2-003 drtoppel,extermatn,chukatai(B) http://arcade.ym2149.com/pcb/taito/drtoppel_pcb_partside.jpg
P0-028-A K1100416A J1100332A 2xZ80B 512/256 512/256 8042 4x6116 No 05,06 23c1000 N/A 3x X2-004 chukatai(B) http://i.ebayimg.com/images/g/AhoAAOSw-FZXj5A5/s-l1600.jpg
P0-038A M6100309A 3xZ80B 512/256 512/256 NONE 1x6164 No 05,06 23c1000 N/A 3x X2-003 kageki http://i.ebayimg.com/images/a/(KGrHqJ,!lwE6C8-G97lBOjOu9mwVw~~/s-l1600.jpg
P0-041-1 CA403001A 2xZ80B 61256 27c1000 8742 1x6164 No 05,06 27c1000 N/A 5x X2-005 tnzsop(C) http://arcade.ym2149.com/pcb/taito/tnzs_pcb3_partside.jpg
P0-041-A K1100356A J1100156A 2xZ80B 61256 27c1000 8042 1x6164 No 05,06 23c1000 N/A 5x X2-005 tnzs(j,u)o http://arcade.ym2149.com/pcb/taito/tnzs_pcb1_partside.jpg
P0-043A M6100356A 3xZ80B* 61256 27512** NONE 1x6164 No 05,06 LH534000(C) N/A 4x X2-004 tnzs(j,u), kabukiz http://arcade.ym2149.com/pcb/taito/tnzs_pcb2_mainboard_partside.jpg
P0-056A K1100476A J1100201A 3xZ80B EMPTY*3 27c1000 NONE 1x6164 No 05,06 LH534000 U43??? 5x X2-005 insectx(D) http://www.jammarcade.net/images/2014/04/InsectorX.jpg
Seta# Taito#s CPUS RxM2 ROM1 MCU? Video ram PROMs SETA X1 GFXROMs QUADRATURE ESD. PROT Games Picture
P0-022-A K1100245A J1100108A 2xZ80B 512/256 512/256 8042 4x6116 Yes, 2 03 23c1000 uPD4701AC 3x X2-003 arkanoid2, plumppop(A) http://www.classicarcaderesource.com/RevengeOfDoh3.jpg
P0-025-A K1100241A J1100107A 2xZ80B 512/256 512/256 8042 4x6116 Yes, 2 03 23c1000 N/A 3x X2-003 drtoppel,extermatn,chukatai(B) http://arcade.ym2149.com/pcb/taito/drtoppel_pcb_partside.jpg
P0-028-A K1100416A J1100332A 2xZ80B 512/256 512/256 8042 4x6116 No 05,06 23c1000 N/A 3x X2-004 chukatai(B) http://i.ebayimg.com/images/g/AhoAAOSw-FZXj5A5/s-l1600.jpg
P0-038A M6100309A 3xZ80B 512/256 512/256 NONE 1x6164 No 05,06 23c1000 N/A 3x X2-003 kageki http://i.ebayimg.com/images/a/(KGrHqJ,!lwE6C8-G97lBOjOu9mwVw~~/s-l1600.jpg
P0-041-1 CA403001A 2xZ80B 61256 27c1000 8742 1x6164 No 05,06 27c1000 N/A 5x X2-005 tnzsop(C) http://arcade.ym2149.com/pcb/taito/tnzs_pcb3_partside.jpg
P0-041-A K1100356A J1100156A 2xZ80B 61256 27c1000 8042 1x6164 No 05,06 23c1000 N/A 5x X2-005 tnzs(j,u)o http://arcade.ym2149.com/pcb/taito/tnzs_pcb1_partside.jpg
P0-043A M6100356A 3xZ80B* 61256 27512** NONE 1x6164 No 05,06 LH534000(C) N/A 4x X2-004 tnzs(j,u), kabukiz http://arcade.ym2149.com/pcb/taito/tnzs_pcb2_mainboard_partside.jpg
P0-056A K1100476A J1100201A 3xZ80B EMPTY*3 27c1000 NONE 1x6164 No 05,06 LH534000 U43??? 5x X2-005 insectx(D) http://www.jammarcade.net/images/2014/04/InsectorX.jpg
(A) It is very likely plumppop also uses this P0-022-A PCB, as the game reads
the quadratures the same way as arkanoid2 does.
arkanoid2 only has 1 x2-003 ESD protection resistor pack populated, but the
PCB can have 3, the other two (for more joysticks/buttons?) are not
populated. arkanoid2's second maincpu socket is also empty, but this is
clearly not the case for plumppop.
the quadratures the same way as arkanoid2 does.
arkanoid2 only has 1 x2-003 ESD protection resistor pack populated, but the
PCB can have 3, the other two (for more joysticks/buttons?) are not
populated. arkanoid2's second maincpu socket is also empty, but this is
clearly not the case for plumppop.
(B) chukatai has one set which unlike its earlier sets uses the P0-025-A
PCB, but with a daughterboard which converts four of the 23c1000 gfx ROM
sockets into 8 27c1000 eprom sockets, and DOES use color PROMs!
The other pcb set uses P0-028-A pcb and 23c1000 mask roms and color RAM,
but has lower rom id numbers. The higher numbered set was likely created
by Taito to 'use up' a stock of older P0-025-A pcbs.
PCB, but with a daughterboard which converts four of the 23c1000 gfx ROM
sockets into 8 27c1000 eprom sockets, and DOES use color PROMs!
The other pcb set uses P0-028-A pcb and 23c1000 mask roms and color RAM,
but has lower rom id numbers. The higher numbered set was likely created
by Taito to 'use up' a stock of older P0-025-A pcbs.
(C) This is a development/prototype PCB, hence it has 32 pin sockets for the
gfx ROMs as 27c1000 eproms, instead of 28 pin sockets for 23c1000 mask
ROMs. It also uses an (unprotected?) 8742 MCU.
Another curious thing is the Taito ID number may have accidentally been
printed in backwards order, i.e should be C1100304A which fits the pattern
of the other boards.
gfx ROMs as 27c1000 eproms, instead of 28 pin sockets for 23c1000 mask
ROMs. It also uses an (unprotected?) 8742 MCU.
Another curious thing is the Taito ID number may have accidentally been
printed in backwards order, i.e should be C1100304A which fits the pattern
of the other boards.
(D) InsectorX has a lot of rework on its PCB, two greenwires for each of the
two LH534000 mask ROMs, and four wires connected to the X1-004 I/O chip
pins 18, 19, 20, and 21, connecting it to 4 pins of a dip16 chip @ U43
with its markings sanded off. Is this chip at U43 a tiny MCU?
* tnzs(j,u) uses a sub board with a z80b and 23c1000 mask ROMs on it for gfx,
plugged into the four LH534000 mask ROM sockets and the 2nd z80 socket.
Like Kageki's P0-038A mainboard, this mainboard has a third z80 on it which
acts in place of the 8x42 mcu used by the older tnzs sets.
** This is a 28-pin 27512 in a 32-pin socket which alternately holds a 27c1000.
*3 This is unpopulated, but the pcb can accept a 61256 SRAM here.
two LH534000 mask ROMs, and four wires connected to the X1-004 I/O chip
pins 18, 19, 20, and 21, connecting it to 4 pins of a dip16 chip @ U43
with its markings sanded off. Is this chip at U43 a tiny MCU?
* tnzs(j,u) uses a sub board with a z80b and 23c1000 mask ROMs on it for gfx,
plugged into the four LH534000 mask ROM sockets and the 2nd z80 socket.
Like Kageki's P0-038A mainboard, this mainboard has a third z80 on it which
acts in place of the 8x42 mcu used by the older tnzs sets.
** This is a 28-pin 27512 in a 32-pin socket which alternately holds a 27c1000.
*3 This is unpopulated, but the pcb can accept a 61256 SRAM here.
*/

24
src/mame/drivers/tosh1000.cpp
View File

@ -4,16 +4,16 @@
Toshiba T1000 portable
80C88 CPU @ 5 MHz [OKI MSM80C88A-10GS-K (56 pin PQFP)]
512KB RAM + 16KB video RAM
32KB BIOS ROM [Toshiba TC54256AD]
256KB MS-DOS 2.11 ROM [Toshiba TC534000]
SuperIO chip (Toshiba T7885) = 82C84 + 82C88 + 82C59 + upd765 + 82C53 + 82C37 + 82C55
Real Time Clock chip: TC8521
Keyboard controller: 80C50
RS232C controller: 8250
80C88 CPU @ 5 MHz [OKI MSM80C88A-10GS-K (56 pin PQFP)]
512KB RAM + 16KB video RAM
32KB BIOS ROM [Toshiba TC54256AD]
256KB MS-DOS 2.11 ROM [Toshiba TC534000]
SuperIO chip (Toshiba T7885) = 82C84 + 82C88 + 82C59 + upd765 + 82C53 + 82C37 + 82C55
Real Time Clock chip: TC8521
Keyboard controller: 80C50
RS232C controller: 8250
NB: dumps of ROM-DOS and CGA chargen are missing.
NB: dumps of ROM-DOS and CGA chargen are missing.
***************************************************************************/
@ -80,8 +80,8 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( tosh1000_io, AS_IO, 8, tosh1000_state )
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x0000, 0x00ff) AM_DEVICE("mb", ibm5160_mb_device, map)
AM_RANGE(0x00c8, 0x00c8) AM_NOP // ROM-DOS page select [p. B-15]
AM_RANGE(0x00e0, 0x00ef) AM_NOP // ???
AM_RANGE(0x00c8, 0x00c8) AM_NOP // ROM-DOS page select [p. B-15]
AM_RANGE(0x00e0, 0x00ef) AM_NOP // ???
AM_RANGE(0x02c0, 0x02cf) AM_DEVREADWRITE("rtc", rp5c01_device, read, write)
ADDRESS_MAP_END
@ -112,7 +112,7 @@ static MACHINE_CONFIG_START( tosh1000, tosh1000_state )
MCFG_ISA8_SLOT_ADD("mb:isa", "isa3", pc_isa8_cards, "lpt", false)
MCFG_ISA8_SLOT_ADD("mb:isa", "isa4", pc_isa8_cards, "com", false)
// MCFG_SOFTWARE_LIST_ADD("flop_list","tosh1000")
// MCFG_SOFTWARE_LIST_ADD("flop_list","tosh1000")
MCFG_PC_KBDC_SLOT_ADD("mb:pc_kbdc", "kbd", pc_xt_keyboards, STR_KBD_KEYTRONIC_PC3270)

18
src/mame/drivers/zwackery.cpp
View File

@ -2,18 +2,18 @@
// copyright-holders: Aaron Giles, Bryan McPhail
/***************************************************************************
Zwackery
Zwackery
© 1984 Midway
© 1984 Midway
The hardware consists of the following boards:
- Venus CPU (B084-91668-A385)
- Venus Video (B084-91675-A385)
- Venus Background (B084-91672-A385)
- Artificial Artist (B084-91671-A385)
The hardware consists of the following boards:
- Venus CPU (B084-91668-A385)
- Venus Video (B084-91675-A385)
- Venus Background (B084-91672-A385)
- Artificial Artist (B084-91671-A385)
TODO:
- Accurate screen timings
TODO:
- Accurate screen timings
***************************************************************************/

2
src/mame/includes/playmark.h
View File

@ -53,7 +53,7 @@ public:
uint8_t m_oki_control;
uint8_t m_oki_command;
uint8_t m_dispenser_latch;
int m_oki_numbanks;
int m_oki_numbanks;
void configure_oki_banks();
/* devices */

2
src/mame/includes/tail2nos.h
View File

@ -34,7 +34,7 @@ public:
int m_txbank;
int m_txpalette;
int m_video_enable;
uint8_t m_pending_command;
uint8_t m_pending_command;
/* devices */
required_device<cpu_device> m_maincpu;

2
src/mame/includes/tnzs.h
View File

@ -88,7 +88,7 @@ protected:
required_ioport m_in2;
int m_input_select;
bool m_lockout_level;
bool m_lockout_level;
};
class tnzs_state : public tnzs_mcu_state

4
src/mame/machine/archimds.cpp
View File

@ -1121,10 +1121,10 @@ WRITE32_MEMBER(archimedes_state::archimedes_memc_w)
{
//printf("MEMC: Starting audio DMA at %d uSec, buffer from %x to %x\n", ((m_vidc_regs[0xc0]&0xff)-2)*8, m_vidc_sndstart, m_vidc_sndend);
#if 0 // more correct to manuals, but breaks ertictac/poizone
#if 0 // more correct to manuals, but breaks ertictac/poizone
m_snd_timer->adjust(attotime::zero, 0, attotime::from_usec(((m_vidc_regs[0xc0]&0xff)-2)*8));
#else // original formula, definitely wrong in at least some cases
#else // original formula, definitely wrong in at least some cases
double sndhz;
/* FIXME: is the frequency correct? */
sndhz = (250000.0 / 2) / (double)((m_vidc_regs[0xc0]&0xff)+2);

14
src/mame/machine/bublbobl.cpp
View File

@ -78,7 +78,7 @@ READ8_MEMBER(bublbobl_state::tokio_mcu_r)
m_mcu_sent = false;
// printf("%s: tokio_mcu_r %02x\n", space.machine().describe_context(), m_from_mcu);
// printf("%s: tokio_mcu_r %02x\n", space.machine().describe_context(), m_from_mcu);
return m_from_mcu;
}
@ -88,7 +88,7 @@ WRITE8_MEMBER(bublbobl_state::tokio_mcu_w)
if (!m_mcu)
return;
// printf("%s: tokio_mcu_w %02x\n", space.machine().describe_context(), data);
// printf("%s: tokio_mcu_w %02x\n", space.machine().describe_context(), data);
m_from_main = data;
m_main_sent = true;
@ -99,13 +99,13 @@ WRITE8_MEMBER(bublbobl_state::tokio_mcu_w)
READ8_MEMBER(bublbobl_state::tokio_mcu_porta_r)
{
// printf("tokio_mcu_porta_r\n");
// printf("tokio_mcu_porta_r\n");
return m_to_mcu_latch;
}
WRITE8_MEMBER(bublbobl_state::tokio_mcu_porta_w)
{
// printf("tokio_mcu_porta_w %02x\n", data);
// printf("tokio_mcu_porta_w %02x\n", data);
m_from_mcu_latch = data;
}
@ -121,7 +121,7 @@ READ8_MEMBER(bublbobl_state::tokio_mcu_portc_r)
ret ^= 0x3; // inverted logic compared to tigerh
// printf("%s: tokio_mcu_portc_r %02x\n", space.machine().describe_context(), ret);
// printf("%s: tokio_mcu_portc_r %02x\n", space.machine().describe_context(), ret);
return ret;
}
@ -129,7 +129,7 @@ READ8_MEMBER(bublbobl_state::tokio_mcu_portc_r)
WRITE8_MEMBER(bublbobl_state::tokio_mcu_portb_w)
{
// printf("tokio_mcu_portb_w %02x\n", data);
// printf("tokio_mcu_portb_w %02x\n", data);
if ((mem_mask & 0x02) && (~data & 0x02) && (m_old_portB & 0x02))
{
@ -143,7 +143,7 @@ WRITE8_MEMBER(bublbobl_state::tokio_mcu_portb_w)
{
m_from_mcu = m_from_mcu_latch;
m_mcu_sent = true;
// printf("sent %02x\n", m_from_mcu);
// printf("sent %02x\n", m_from_mcu);
}
m_old_portB = data;

6
src/mame/machine/m2comm.h
View File

@ -55,9 +55,9 @@ protected:
private:
uint8_t m_shared[0x4000]; // 16k shared memory
uint8_t m_zfg; // z80 flip gate - bit 0 switches memory banks, bit7 is connected to FG bit 0
uint8_t m_cn; // bit0 is used to enable/disable the comm board
uint8_t m_fg; // i960 flip gate - bit0 is stored, bit7 is connected to ZFG bit 0
uint8_t m_zfg; // z80 flip gate - bit 0 switches memory banks, bit7 is connected to FG bit 0
uint8_t m_cn; // bit0 is used to enable/disable the comm board
uint8_t m_fg; // i960 flip gate - bit0 is stored, bit7 is connected to ZFG bit 0
emu_file m_line_rx; // rx line - can be either differential, simple serial or toslink
emu_file m_line_tx; // tx line - is differential, simple serial and toslink

14
src/mame/machine/midwayic.cpp
View File

@ -223,43 +223,43 @@ void midway_serial_pic_emu_device::device_start()
READ_LINE_MEMBER(midway_serial_pic_emu_device::PIC16C5X_T0_clk_r)
{
// printf("%s: PIC16C5X_T0_clk_r\n", machine().describe_context());
// printf("%s: PIC16C5X_T0_clk_r\n", machine().describe_context());
return 0;
}
READ8_MEMBER(midway_serial_pic_emu_device::read_a)
{
// printf("%s: read_a\n", space.machine().describe_context());
// printf("%s: read_a\n", space.machine().describe_context());
return 0x00;
}
READ8_MEMBER(midway_serial_pic_emu_device::read_b)
{
// printf("%s: read_b\n", space.machine().describe_context());
// printf("%s: read_b\n", space.machine().describe_context());
return 0x00;
}
READ8_MEMBER(midway_serial_pic_emu_device::read_c)
{
// used
// printf("%s: read_c\n", space.machine().describe_context());
// printf("%s: read_c\n", space.machine().describe_context());
return 0x00;
}
WRITE8_MEMBER(midway_serial_pic_emu_device::write_a)
{
// printf("%s: write_a %02x\n", space.machine().describe_context(), data);
// printf("%s: write_a %02x\n", space.machine().describe_context(), data);
}
WRITE8_MEMBER(midway_serial_pic_emu_device::write_b)
{
// printf("%s: write_b %02x\n", space.machine().describe_context(), data);
// printf("%s: write_b %02x\n", space.machine().describe_context(), data);
}
WRITE8_MEMBER(midway_serial_pic_emu_device::write_c)
{
// used
// printf("%s: write_c %02x\n", space.machine().describe_context(), data);
// printf("%s: write_c %02x\n", space.machine().describe_context(), data);
}
static MACHINE_CONFIG_FRAGMENT( midway_pic )

8
src/mame/machine/naomigd.cpp
View File

@ -60,12 +60,12 @@ DIMM controller registers
c - unk, set to 1 in VxWorks, 0 in 1.02
d - unk, checked for == 1 in 1.02
2A 8bit possible DES decryption area size 8 MSB bits (16MB units number)
2A 8bit possible DES decryption area size 8 MSB bits (16MB units number)
VxWorks firmwares set this to ((DIMMsize >> 24) - 1), 1.02 set it to FF
2C 32bit SDRAM config
30 32bit DES key low
34 32bit DES key high
2C 32bit SDRAM config
30 32bit DES key low
34 32bit DES key high
SH4 IO port A bits
-------------------

94
src/mame/machine/nl_hazelvid.cpp
View File

@ -60,8 +60,8 @@ NETLIST_START(hazelvid)
ALIAS(vidbus, u72.Q6)
TTL_7404_INVERT(u59_5, u72.Q7)
TTL_7400_NAND(u83_1, high, vstrobe)
ALIAS(char_line_clk, u83_1.Q)
TTL_7400_NAND(u83_1, high, vstrobe)
ALIAS(char_line_clk, u83_1.Q)
/* Character line counter */
TTL_74161(u84, low, low, low, low, high, u83_3.Q, char_line_clk, high, high)
@ -72,25 +72,25 @@ NETLIST_START(hazelvid)
TTL_7400_NAND(u83_3, u84.QB, u84.QD)
TTL_7404_INVERT(u92_5, u90.QD)
TTL_7410_NAND(u89_3, u90.QD, u90.QC, u90.QA)
TTL_7410_NAND(u89_3, u90.QD, u90.QC, u90.QA)
/* Character row counter */
/* Character row counter */
TTL_74161(u90, low, low, low, low, high, u89_3.Q, u92_3.Q, high, high)
TTL_7404_INVERT(u92_3, u84.QD)
TTL_7404_INVERT(u92_1, u90.QB)
TTL_7404_INVERT(u92_1, u90.QB)
TTL_7474(u95_2, u92_5.Q, u95_2.QQ, high, high)
TTL_7411_AND(u91_3, u84.QA, u84.QD, u90.QB)
TTL_7411_AND(u91_1, u92_1.Q, u90.QA, u84.QC)
TTL_7411_AND(u91_3, u84.QA, u84.QD, u90.QB)
TTL_7411_AND(u91_1, u92_1.Q, u90.QA, u84.QC)
TTL_7404_INVERT(u92_2, u90.QC)
TTL_7411_AND(u91_2, u95_2.QQ, u92_2.Q, u92_5.Q)
TTL_7404_INVERT(u92_6, u91_2.Q)
TTL_7404_INVERT(u92_2, u90.QC)
TTL_7411_AND(u91_2, u95_2.QQ, u92_2.Q, u92_5.Q)
TTL_7404_INVERT(u92_6, u91_2.Q)
/* Vertical blanking and drive */
TTL_7473(u85_vdrive, char_line_clk, u91_1.Q, u91_3.Q, u85_vblankq.QQ)
TTL_7473(u85_vblankq, char_line_clk, u92_6.Q, u91_2.Q, high)
/* Vertical blanking and drive */
TTL_7473(u85_vdrive, char_line_clk, u91_1.Q, u91_3.Q, u85_vblankq.QQ)
TTL_7473(u85_vblankq, char_line_clk, u92_6.Q, u91_2.Q, high)
/* Outgoing signals */
TTL_7404_INVERT(u73_4, hdriveq)
@ -111,9 +111,9 @@ NETLIST_START(hazelvid)
TTL_7402_NOR(u60_2, hblank, u85_vblankq.QQ)
ALIAS(clr_vid_sr, u60_2.Q)
TTL_7404_INVERT(u92_4, u84.QB)
TTL_74260_NOR(u82_2, u85_vblankq.QQ, u92_3.Q, u84.QC, u92_4.Q, u84.QA)
TTL_7400_NAND(u83_2, vstrobe, u82_2.Q)
TTL_7404_INVERT(u92_4, u84.QB)
TTL_74260_NOR(u82_2, u85_vblankq.QQ, u92_3.Q, u84.QC, u92_4.Q, u84.QA)
TTL_7400_NAND(u83_2, vstrobe, u82_2.Q)
ALIAS(sync_bus_disable_q, u83_2.Q)
ALIAS(vdrive, u85_vdrive.Q)
@ -121,28 +121,28 @@ NETLIST_START(hazelvid)
ALIAS(vdriveq, u73_5.Q)
TTL_7474(u95_1, u84.QD, u85_vblankq.QQ, high, high)
ALIAS(vblank, u95_1.Q)
ALIAS(vblank, u95_1.Q)
TTL_74260_NOR(u82_1, u85_vblankq.QQ, u92_4.Q, u84.QD, u84.QC, low)
TTL_7404_INVERT(u61_3, u82_1.Q)
ALIAS(tvinterq, u61_3.Q)
TTL_74260_NOR(u82_1, u85_vblankq.QQ, u92_4.Q, u84.QD, u84.QC, low)
TTL_7404_INVERT(u61_3, u82_1.Q)
ALIAS(tvinterq, u61_3.Q)
TTL_INPUT(cpu_iowq, 1)
TTL_INPUT(cpu_ba4, 1)
TTL_7432_OR(u36_1, cpu_iowq, cpu_ba4)
TTL_INPUT(cpu_iowq, 1)
TTL_INPUT(cpu_ba4, 1)
TTL_7432_OR(u36_1, cpu_iowq, cpu_ba4)
/* Character address counter */
TTL_74193(u7, low, low, low, low, low, u36_1.Q, cntclk, high)
TTL_74193(u5, cpu_db0, cpu_db1, cpu_db2, cpu_db3, low, u36_1.Q, u7.CARRYQ, u7.BORROWQ)
TTL_74193(u3, cpu_db4, cpu_db5, cpu_db6, cpu_db7, low, u36_1.Q, u5.CARRYQ, u5.BORROWQ)
TTL_74365(u6, low, ncntbenq, u7.QA, u7.QB, u7.QC, u7.QD, u5.QA, u5.QB)
TTL_74365(u4, low, ncntbenq, u5.QC, u5.QD, u3.QA, u3.QB, u3.QC, low)
TTL_74365(u6, low, ncntbenq, u7.QA, u7.QB, u7.QC, u7.QD, u5.QA, u5.QB)
TTL_74365(u4, low, ncntbenq, u5.QC, u5.QD, u3.QA, u3.QB, u3.QC, low)
ALIAS(ba0, u6.Y1)
ALIAS(ba1, u6.Y2)
ALIAS(ba2, u6.Y3)
ALIAS(ba3, u6.Y4)
ALIAS(ba4, u6.Y5)
ALIAS(ba4, u6.Y5)
ALIAS(ba5, u6.Y6)
ALIAS(ba6, u4.Y1)
ALIAS(ba7, u4.Y2)
@ -151,17 +151,17 @@ NETLIST_START(hazelvid)
ALIAS(ba10, u4.Y5)
/* Video RAM */
TTL_INPUT(memwq, 1)
TTL_INPUT(mrq, 1)
TTL_INPUT(ba13, 0)
TTL_INPUT(memwq, 1)
TTL_INPUT(mrq, 1)
TTL_INPUT(ba13, 0)
TTL_7432_OR(u36_2, memwq, memwq)
TTL_7400_NAND(u37_2, u36_2.Q, mrq)
TTL_7400_NAND(u37_3, u37_2.Q, ba13)
TTL_7400_NAND(u37_4, u37_3.Q, ncntbenq)
TTL_7404_INVERT(u17_2, u4.Y5)
TTL_7400_NAND(u30_2, u17_2.Q, u37_4.Q)
TTL_7400_NAND(u37_1, u4.Y5, u37_4.Q)
TTL_7432_OR(u36_2, memwq, memwq)
TTL_7400_NAND(u37_2, u36_2.Q, mrq)
TTL_7400_NAND(u37_3, u37_2.Q, ba13)
TTL_7400_NAND(u37_4, u37_3.Q, ncntbenq)
TTL_7404_INVERT(u17_2, u4.Y5)
TTL_7400_NAND(u30_2, u17_2.Q, u37_4.Q)
TTL_7400_NAND(u37_1, u4.Y5, u37_4.Q)
TTL_INPUT(rwq, 1)
/* Lower 1K */
@ -182,18 +182,18 @@ NETLIST_START(hazelvid)
RAM_2102A(u13, u37_1.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u13.DO)
RAM_2102A(u14, u37_1.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u14.DO)
RAM_2102A(u15, u37_1.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u15.DO)
RAM_2102A(u16, u37_1.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u16.DO)
RAM_2102A(u16, u37_1.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u16.DO)
TTL_INPUT(cpu_db0, 0)
TTL_INPUT(cpu_db1, 0)
TTL_INPUT(cpu_db2, 0)
TTL_INPUT(cpu_db3, 0)
TTL_INPUT(cpu_db4, 0)
TTL_INPUT(cpu_db5, 0)
TTL_INPUT(cpu_db6, 0)
TTL_INPUT(cpu_db7, 0)
TTL_INPUT(cpu_db0, 0)
TTL_INPUT(cpu_db1, 0)
TTL_INPUT(cpu_db2, 0)
TTL_INPUT(cpu_db3, 0)
TTL_INPUT(cpu_db4, 0)
TTL_INPUT(cpu_db5, 0)
TTL_INPUT(cpu_db6, 0)
TTL_INPUT(cpu_db7, 0)
TTL_TRISTATE(db0, u30_2.Q, u29.DO, u37_1.Q, u16.DO)
TTL_TRISTATE(db0, u30_2.Q, u29.DO, u37_1.Q, u16.DO)
TTL_TRISTATE(db1, u30_2.Q, u28.DO, u37_1.Q, u15.DO)
TTL_TRISTATE(db2, u30_2.Q, u27.DO, u37_1.Q, u14.DO)
TTL_TRISTATE(db3, u30_2.Q, u26.DO, u37_1.Q, u13.DO)
@ -209,7 +209,7 @@ NETLIST_START(hazelvid)
TTL_74175(u58, dot, db4.Q, db5.Q, db6.Q, db7.Q, high) // most signifcant 4 bits of each character
TTL_AM2847(u57, lbc, u58.Q1, u58.Q2, u58.Q3, u58.Q4, sync_bus_disable_q, sync_bus_disable_q, sync_bus_disable_q, sync_bus_disable_q)
TTL_74174(u66, ndot, u67.OUTA, u67.OUTB, u67.OUTC, u67.OUTD, u57.OUTA, u57.OUTB, high)
TTL_74174(u66, ndot, u67.OUTA, u67.OUTB, u67.OUTC, u67.OUTD, u57.OUTA, u57.OUTB, high)
TTL_74175(u56, ndot, u57.OUTC, clr_vid_sr, u79_1.Q, u57.OUTD, high)
TTL_7400_NAND(u79_1, u56.Q4, clr_vid_sr)
ALIAS(fgbit_q, u56.Q3Q)

16
src/mame/mame.lst
View File

@ -9613,7 +9613,7 @@ cocoe // Color Computer (Extended BASIC 1.0)
cp400 // Prologica CP400
lzcolor64 // Digiponto LZ Color64
mx1600 // Dynacom MX-1600
t4426 // Terco T4426 CNC programming station
t4426 // Terco T4426 CNC programming station
@source:coco3.cpp
coco3 // Color Computer 3 (NTSC)
@ -11995,7 +11995,7 @@ sd1 // 1990 SD-1
sd132 // 1991 SD-1 32
sq1 // 1990 SQ-1
sqrack // 1990 SQ-Rack
sq2 // 1991 SQ-2
sq2 // 1991 SQ-2
vfx // 1989 VFX
vfxsd // 1989 VFX-SD
@ -13387,7 +13387,7 @@ gkigtez //
gkkey //
igtsc //
ms72c //
ms3 //
ms3 //
@source:gladiatr.cpp
gcastle // QB (c) 1986 Taito Corporation (prototype?)
@ -17331,7 +17331,7 @@ trojanr // 4/1986 (c) 1986 + Romstar
fball //
@source:lwriter.cpp
lwriter // Apple LaserWriter
lwriter // Apple LaserWriter
@source:lynx.cpp
lynx // Atari Lynx Handheld
@ -28864,7 +28864,7 @@ quizkofk // 0080 (c) 1995 Saurus
ragnagrd // 0218 (c) 1996 Saurus
rbff1 // 0095 (c) 1995 SNK
rbff1a // 0095 (c) 1995 SNK
rbff1k // 0095 (c) 1995 SNK
rbff1k // 0095 (c) 1995 SNK
rbff2 // 0240 (c) 1998 SNK
rbff2h // 0240 (c) 1998 SNK
rbff2k // 0140 Censored Korean release of rbff2
@ -29607,8 +29607,8 @@ ssam88s //
sx16 // Sanyo SX-16
zdsupers //
ncrpc4i // NCR PC4i
laser_turbo_xt // 1988 VTech Laser Turbo XT
laser_xt3 // 1989 VTech Laser XT/3
laser_turbo_xt // 1988 VTech Laser Turbo XT
laser_xt3 // 1989 VTech Laser XT/3
@source:pc100.cpp
pc100 //
@ -35841,7 +35841,7 @@ outzonecv // TP-O18 (c) 1990 Toaplan (TP-015 conversion)
rallybik // B45 / TP-O12 (c) 1988 Taito
samesame // TP-O17 (c) 1989 Toaplan
samesame2 // TP-O17 (c) 1989 Toaplan
samesamenh // hack
samesamenh // hack
truxton // B65 / TP-O13B (c) 1988 Taito
vimana // TP-O19 (c) 1991 Toaplan (+ Tecmo license when set to Japan)
vimanaj // TP-O19 (c) 1991 Toaplan (+ Tecmo license when set to Japan)