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vp101: Improved support for reduced-cost VP050 version. [R. Belmont]
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arbee
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@ -2,21 +2,102 @@
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// copyright-holders:R. Belmont
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/***************************************************************************
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Play Mechanix / Right Hand Tech "VP100" and "VP101" platforms
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Play Mechanix / Right Hand Tech "VP50", "VP100" and "VP101" platforms
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(PCBs are also marked "Raw Thrills" but all RT games appear to be on PC hardware)
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Boards:
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- VP101: Johnny Nero. The original (?)
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- VP100: Special Forces Elite Training. A not-quite-complete VP101; missing ATA DMA.
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- VP50 : Zoofari. Cost-reduced (?) with TX4925 SoC, much less complex FPGA.
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Preliminary driver by R. Belmont
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TODO:
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- All games: that formidable sounding 3D accelerator mentioned below.
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- All games: the sound system (the POST plays some example sounds)
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- Zoofari's framebuffer is 256 color but I don't know where the CLUT comes from.
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MIPS VR5500 at 300 to 400 MHz
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Xilinx Virtex-II FPGA with custom 3D hardware and 1 or 2 PowerPC 405 CPU cores
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AC97 audio with custom DMA frontend which streams 8 stereo channels
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PIC18c442 protection chip (not readable) on VP101 only (VP100 is unprotected?)
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To make the games go into a POST test, hold down START 1 while resetting.
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1 MB of VRAM at main RAM offset 0x07400000
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VP101 Features from http://web.archive.org/web/20041016000248/http://www.righthandtech.com/projects.htm
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MIPS VR5500 CPU
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The VR5500 operates at either at 300 or 400 MHz with 120MHz external bus
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MIPS 64-bit RISC architecture
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Two-way super-scalar super pipeline
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On-chip floating-point unit (FPU)
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High-speed translation look-aside buffer (TLB)(48 double-entries)
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On-chip primary cache memory (instruction/data: 32 KB each)
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2-way set associative, Supports line lock feature
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Conforms to MIPS I, II, III, and IV instruction sets. Also supports product-sum operation instruction, rotate instruction, register scan instruction
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Six execution units (ALU0, ALU1, FPU, FPU/MAC, BRU, and LSU)
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Employment of out-of-order execution mechanism
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Branch prediction mechanism - Branch history table with 4K entries
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Support for CPU emulator connection via JTAG/n-Wire port
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Unified Memory Architecture - DDR SDRAM bank
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Arbitrating DDR SDRAM Memory controller
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128Mbyte to 512Mbyte memory capacity
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120/240 MHz @ 64 bits - ~2GBytes/sec bandwidth
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3D Render Engine
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True color and 8-bit palette lookup textures
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8K byte texel cache for accelerated source texel selection.
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Perspective corrected rendering
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Bi-linear filter for source texel scaling
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256 Color Palette Lookup (888 RGB plus 8 bit Source Palette Alpha)
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True Color Source Textures (888 RGB plus 8 bit Alpha)
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24 bit Z-buffer structure in DDR SDRAM buffer
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Per-vertex colored lighting
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Alpha channel structure in DDR SDRAM buffer
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Pixel processing effects (fog, night, etc.)
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888 RGB Video DAC output section.
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Bitmap structure in DDR SDRAM with DMA for screen update
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Flexible CRT controller with X/Y gun interface counters
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Game I/O
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Standard JAMMA I/O interface, including player 3 and 4 connectors
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4 channel general purpose A to D interface (steering wheel and control pedals)
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100baseT Ethernet interface for debugging and/or inter game communications
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Forced-feedback “Wheel Driver Interface” for driving games
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High-current drivers for lamps or solenoids
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Gun interface I/O tightly coupled to the CRT controller
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Sound System
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AC97 codec for low cost of implementation and development
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TDA7375 40 Watt Integrated Amplifier
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Codec fed from the DDR bank via a 16 channel (8 channels of stereo) DMA engine.
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ATA/IDE Disk Drive Interface
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Standard ATA/IDE interface
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Ultra DMA 33/66/100/133 to the DDR SDRAM memory
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Video DAC
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RGB values at 8 bits per color
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RGB voltage level adjustable from 0-1.0 Vp-p to 0-4.0 Vp-p
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Flash Memory
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Minimum of 1MB of Flash memory – expandable to 4 MB
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Updateable Boot ROM
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Updateable FPGA configuration
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Battery Backed Up RAM
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32K bytes of non-volatile memory for static game configuration and high score table
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Non-volatile Real-Time clock
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Small Footprint
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Small outline design for easy kit retrofitting of existing cabinet
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12.2 in x 14.96 in
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Security Interface
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Security processor provides for a means to “unlock” the FPGA functions
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Enabled for software protection against piracy and unwarranted game updates
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Full populated and tested board is less than $500, including IDE hard disk.
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Small outline design for easy kit retrofitting of existing cabinets.
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****************************************************************************/
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#include "emu.h"
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#include "cpu/mips/mips3.h"
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#include "machine/ataintf.h"
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@ -31,26 +112,33 @@ public:
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: driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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m_mainram(*this, "mainram"),
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m_ata(*this, "ata")
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m_ata(*this, "ata"),
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m_in0(*this, "IN0")
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{ }
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virtual void machine_reset() override;
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virtual void machine_start() override;
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DECLARE_READ32_MEMBER(tty_ready_r);
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DECLARE_WRITE32_MEMBER(tty_w);
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DECLARE_READ32_MEMBER(test_r) { return 0xffffffff; }
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DECLARE_READ32_MEMBER(pic_r);
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DECLARE_WRITE32_MEMBER(pic_w);
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DECLARE_WRITE32_MEMBER(dmaaddr_w);
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DECLARE_WRITE_LINE_MEMBER(dmarq_w);
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DECLARE_READ32_MEMBER(tty_4925_rdy_r) { return 0x2; }
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DECLARE_READ32_MEMBER(spi_status_r) { return 0x8007; }
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DECLARE_READ32_MEMBER(spi_r);
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DECLARE_WRITE32_MEMBER(spi_w);
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uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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uint32_t vp50_screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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protected:
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@ -58,6 +146,7 @@ protected:
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required_device<mips3_device> m_maincpu;
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required_shared_ptr<uint32_t> m_mainram;
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required_device<ata_interface_device> m_ata;
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required_ioport m_in0;
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// driver_device overrides
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virtual void video_start() override;
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@ -65,6 +154,7 @@ protected:
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int pic_state;
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int m_dmarq_state;
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uint32_t m_dma_ptr;
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uint32_t m_spi_select;
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};
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void vp10x_state::machine_reset()
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@ -76,9 +166,9 @@ void vp10x_state::machine_reset()
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void vp10x_state::machine_start()
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{
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m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS);
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m_maincpu->add_fastram(0x00000000, 0x07ffffff, false, m_mainram);
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// m_maincpu->add_fastram(0x00000000, 0x03ffffff, false, m_mainram);
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}
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WRITE32_MEMBER(vp10x_state::dmaaddr_w)
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{
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m_dma_ptr = (data & 0x07ffffff);
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@ -89,18 +179,18 @@ WRITE_LINE_MEMBER(vp10x_state::dmarq_w)
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if (state != m_dmarq_state)
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{
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m_dmarq_state = state;
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if (state)
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{
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uint16_t *RAMbase = (uint16_t *)&m_mainram[0];
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uint16_t *RAM = &RAMbase[m_dma_ptr>>1];
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uint16_t *RAM = &RAMbase[m_dma_ptr>>1];
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m_ata->write_dmack(ASSERT_LINE);
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m_ata->write_dmack(ASSERT_LINE);
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while (m_dmarq_state)
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{
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*RAM++ = m_ata->read_dma();
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m_dma_ptr += 2; // pointer must advance
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m_dma_ptr += 2; // pointer must advance
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}
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m_ata->write_dmack(CLEAR_LINE);
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@ -108,7 +198,7 @@ WRITE_LINE_MEMBER(vp10x_state::dmarq_w)
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}
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}
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READ32_MEMBER(vp10x_state::pic_r)
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READ32_MEMBER(vp10x_state::pic_r)
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{
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static const uint8_t vers[5] = { 0x00, 0x01, 0x00, 0x00, 0x00 };
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static const uint8_t serial[10] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a };
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@ -118,15 +208,15 @@ READ32_MEMBER(vp10x_state::pic_r)
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{
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case 0x20:
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return vers[pic_state++];
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case 0x21:
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case 0x22:
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return serial[pic_state++];
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case 0x23: // this is the same for jnero and specfrce. great security!
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case 0x23: // this is the same for jnero and specfrce. great security!
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return magic[pic_state++];
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}
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return 0;
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}
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@ -141,6 +231,16 @@ WRITE32_MEMBER(vp10x_state::pic_w)
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pic_state = 0;
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}
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READ32_MEMBER(vp10x_state::spi_r)
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{
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return 0xffffffff;
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}
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WRITE32_MEMBER(vp10x_state::spi_w)
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{
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// printf("%d to SPI select\n", data);
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m_spi_select = data;
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}
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void vp10x_state::video_start()
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{
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@ -165,7 +265,33 @@ uint32_t vp10x_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap,
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*line++ = word;
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}
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}
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return 0;
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}
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// TODO: Palette is not at 0, where is it?
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uint32_t vp10x_state::vp50_screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
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{
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const uint8_t *video_ram;
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uint32_t *line;
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int y, x;
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int r,g,b;
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const uint16_t *pal_ram = (const uint16_t *) &m_mainram[0];
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for (y = 0; y < 240; y++)
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{
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line = &bitmap.pix32(y);
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video_ram = (const uint8_t *) &m_mainram[(0x10000/4)+(y * 100)];
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for (x = 0; x < 400; x++)
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{
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// assume 565
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r = pal_ram[video_ram[x]] >> 11;
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g = (pal_ram[video_ram[x]] >> 5) & 0x3f;
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b = pal_ram[video_ram[x]] & 0x1f;
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*line++ = (r << 19) | (g << 10) | (b << 3);
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}
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}
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return 0;
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}
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@ -178,41 +304,65 @@ WRITE32_MEMBER(vp10x_state::tty_w) // set breakpoint at bfc01430 to catch when
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{
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// uncomment to see startup messages - it says "RAM OK" and "EPI RSS Ver 4.5.1" followed by "<RSS active>" and then lots of dots
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// Special Forces also says "<inited tv_cap> = 00000032"
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printf("%c", data);
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// printf("%c", data);
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}
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static ADDRESS_MAP_START( main_map, AS_PROGRAM, 32, vp10x_state )
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AM_RANGE(0x00000000, 0x07ffffff) AM_RAM AM_SHARE("mainram") // this is a sufficient amount to get "RAM OK"
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AM_RANGE(0x00000000, 0x07ffffff) AM_RAM AM_SHARE("mainram")
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AM_RANGE(0x14000000, 0x14000003) AM_READ(test_r)
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AM_RANGE(0x1c000000, 0x1c000003) AM_WRITE(tty_w) // RSS OS code uses this one
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AM_RANGE(0x1c000014, 0x1c000017) AM_READ(tty_ready_r)
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AM_RANGE(0x1c400000, 0x1c400003) AM_WRITE(tty_w) // boot ROM code uses this one
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AM_RANGE(0x1c400014, 0x1c400017) AM_READ(tty_ready_r)
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AM_RANGE(0x1ca0000c, 0x1ca0000f) AM_READ_PORT("IN0")
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AM_RANGE(0x1ca00010, 0x1ca00013) AM_READ(test_r) // bits here cause various test mode stuff
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AM_RANGE(0x1ca00010, 0x1ca00013) AM_READ(test_r) // bits here cause various test mode stuff
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AM_RANGE(0x1cf00000, 0x1cf00003) AM_NOP AM_READNOP
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AM_RANGE(0x1d000030, 0x1d000033) AM_WRITE(dmaaddr_w) // ATA DMA destination address
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AM_RANGE(0x1d000030, 0x1d000033) AM_WRITE(dmaaddr_w) // ATA DMA destination address
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AM_RANGE(0x1d000040, 0x1d00005f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs0, write_cs0, 0x0000ffff)
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AM_RANGE(0x1d000060, 0x1d00007f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs1, write_cs1, 0x0000ffff)
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AM_RANGE(0x1f200000, 0x1f200003) AM_READWRITE(pic_r, pic_w)
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AM_RANGE(0x1f807000, 0x1f807fff) AM_RAM AM_SHARE("nvram")
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AM_RANGE(0x1f807000, 0x1f807fff) AM_RAM AM_SHARE("nvram")
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AM_RANGE(0x1fc00000, 0x1fffffff) AM_ROM AM_REGION("maincpu", 0)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( vp50_map, AS_PROGRAM, 32, vp10x_state )
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AM_RANGE(0x00000000, 0x03ffffff) AM_RAM AM_SHARE("mainram")
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AM_RANGE(0x1f000010, 0x1f00001f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs1, write_cs1, 0xffffffff)
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AM_RANGE(0x1f000020, 0x1f00002f) AM_DEVREADWRITE16("ata", ata_interface_device, read_cs0, write_cs0, 0xffffffff)
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AM_RANGE(0x1f400000, 0x1f400003) AM_NOP // FPGA bitstream download?
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AM_RANGE(0x1f400800, 0x1f400bff) AM_RAM AM_SHARE("nvram")
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AM_RANGE(0x1fc00000, 0x1fffffff) AM_ROM AM_REGION("maincpu", 0)
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// TX4925 peripherals
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AM_RANGE(0xff1ff40c, 0xff1ff40f) AM_READ(tty_4925_rdy_r)
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AM_RANGE(0xff1ff41c, 0xff1ff41f) AM_WRITE(tty_w)
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AM_RANGE(0xff1ff500, 0xff1ff503) AM_NOP
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AM_RANGE(0xff1ff814, 0xff1ff817) AM_READ(spi_status_r)
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AM_RANGE(0xff1ff818, 0xff1ff81b) AM_READWRITE(spi_r, spi_w)
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ADDRESS_MAP_END
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static INPUT_PORTS_START( vp101 )
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PORT_START("IN0")
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PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_COIN1 )
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PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_START1 )
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PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_COIN2 )
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PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_START2 )
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PORT_BIT( 0xfffffff0, IP_ACTIVE_HIGH, IPT_UNKNOWN )
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INPUT_PORTS_END
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static INPUT_PORTS_START( vp50 )
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PORT_START("IN0")
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PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_COIN1 )
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PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_START1 )
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PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_COIN2 )
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PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_START2 )
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PORT_BIT( 0xfffffff0, IP_ACTIVE_HIGH, IPT_UNKNOWN )
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INPUT_PORTS_END
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static MACHINE_CONFIG_START( vp101, vp10x_state )
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MCFG_CPU_ADD("maincpu", R5000LE, 400000000) /* actually VR5500 with added NEC VR-series custom instructions */
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MCFG_MIPS3_ICACHE_SIZE(32768)
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MCFG_CPU_ADD("maincpu", VR5500LE, 400000000)
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MCFG_MIPS3_DCACHE_SIZE(32768)
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MCFG_MIPS3_SYSTEM_CLOCK(100000000)
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MCFG_CPU_PROGRAM_MAP(main_map)
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@ -223,13 +373,30 @@ static MACHINE_CONFIG_START( vp101, vp10x_state )
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MCFG_SCREEN_UPDATE_DRIVER(vp10x_state, screen_update)
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MCFG_SCREEN_SIZE(320, 240)
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MCFG_SCREEN_VISIBLE_AREA(0, 319, 0, 239)
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MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", nullptr, false)
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MCFG_ATA_INTERFACE_DMARQ_HANDLER(WRITELINE(vp10x_state, dmarq_w))
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MCFG_NVRAM_ADD_0FILL("nvram")
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_START( vp50, vp10x_state )
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MCFG_CPU_ADD("maincpu", TX4925LE, 200000000)
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MCFG_MIPS3_DCACHE_SIZE(32768)
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MCFG_MIPS3_SYSTEM_CLOCK(100000000)
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MCFG_CPU_PROGRAM_MAP(vp50_map)
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MCFG_SCREEN_ADD("screen", RASTER)
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MCFG_SCREEN_REFRESH_RATE(60)
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MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
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MCFG_SCREEN_UPDATE_DRIVER(vp10x_state, vp50_screen_update)
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MCFG_SCREEN_SIZE(400, 240)
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MCFG_SCREEN_VISIBLE_AREA(0, 399, 0, 239)
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MCFG_ATA_INTERFACE_ADD("ata", ata_devices, "hdd", nullptr, false)
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MCFG_NVRAM_ADD_0FILL("nvram")
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MACHINE_CONFIG_END
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ROM_START(jnero)
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ROM_REGION(0x400000, "maincpu", 0) /* Boot ROM */
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@ -238,14 +405,15 @@ ROM_START(jnero)
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ROM_REGION(0x80000, "pic", 0) /* PIC18c422 program - read-protected, need dumped */
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ROM_LOAD( "8722a-1206.bin", 0x000000, 0x80000, NO_DUMP )
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DISK_REGION( "ata:0:hdd:image" )
|
||||
DISK_IMAGE_READONLY("jn010108", 0, SHA1(4f3e9c6349c9be59213df1236dba7d79e7cd704e) )
|
||||
DISK_REGION( "ata:0:hdd:image" ) /* ideally an IDENTIFY page from a real drive should be the IDTN metadata,
|
||||
but even factory-new boardsets came with a variety of HDD makes and models */
|
||||
DISK_IMAGE_READONLY("jn010108", 0, SHA1(5a27990478b65fca801c3a6518c519c5b4ca934d) )
|
||||
ROM_END
|
||||
|
||||
ROM_START(specfrce)
|
||||
ROM_REGION(0x400000, "maincpu", 0) /* Boot ROM */
|
||||
ROM_LOAD( "special_forces_boot_v3.4.u4", 0x000000, 0x100000, CRC(db4862ac) SHA1(a1e886d424cf7d26605e29d972d48e8d44ae2d58) )
|
||||
ROM_LOAD( "special_forces_boot_v3.5.u4", 0x000000, 0x100000, CRC(ae8dfdf0) SHA1(d64130e710d0c70095ad8ebd4e2194b8c461be4a) ) /* Newer, but keep both in driver */
|
||||
//ROM_LOAD( "special_forces_boot_v3.5.u4", 0x000000, 0x100000, CRC(ae8dfdf0) SHA1(d64130e710d0c70095ad8ebd4e2194b8c461be4a) ) /* Newer, but keep both in driver */
|
||||
|
||||
ROM_REGION(0x80000, "pic", 0) /* PIC18c422 I/P program - read-protected, need dumped */
|
||||
ROM_LOAD( "special_forces_et_u7_rev1.2.u7", 0x000000, 0x80000, NO_DUMP )
|
||||
@ -265,6 +433,6 @@ ROM_START(zoofari)
|
||||
DISK_IMAGE_READONLY("zoofari", 0, SHA1(8fb9cfb1ab2660f40b643fcd772243903bd69a6c) )
|
||||
ROM_END
|
||||
|
||||
GAME( 2002, specfrce, 0, vp101, vp101, driver_device, 0, ROT0, "ICE/Play Mechanix", "Special Forces Elite Training", MACHINE_IS_SKELETON )
|
||||
GAME( 2004, jnero, 0, vp101, vp101, driver_device, 0, ROT0, "ICE/Play Mechanix", "Johnny Nero Action Hero", MACHINE_IS_SKELETON )
|
||||
GAME( 2006, zoofari, 0, vp101, vp101, driver_device, 0, ROT0, "ICE/Play Mechanix", "Zoofari", MACHINE_IS_SKELETON )
|
||||
GAME( 2002, specfrce, 0, vp101, vp101, driver_device, 0, ROT0, "ICE/Play Mechanix", "Special Forces Elite Training", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
|
||||
GAME( 2004, jnero, 0, vp101, vp101, driver_device, 0, ROT0, "ICE/Play Mechanix", "Johnny Nero Action Hero", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
|
||||
GAME( 2006, zoofari, 0, vp50, vp50, driver_device, 0, ROT0, "ICE/Play Mechanix", "Zoofari", MACHINE_NOT_WORKING | MACHINE_NO_SOUND)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user