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netlist: Added devices CD4013, CD4069, CD4070

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This commit is contained in:
Frank Palazzolo 2020-05-15 16:14:05 -04:00 committed by GitHub
parent 0c094f8ede
commit 12ec6362bb
9 changed files with 279 additions and 15 deletions
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1
src/lib/netlist/build/makefile
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@ -145,6 +145,7 @@ NLOBJS := \
$(NLOBJ)/devices/nld_2716.o \
$(NLOBJ)/devices/nld_tms4800.o \
$(NLOBJ)/devices/nld_4006.o \
$(NLOBJ)/devices/nld_4013.o \
$(NLOBJ)/devices/nld_4020.o \
$(NLOBJ)/devices/nld_4066.o \
$(NLOBJ)/devices/nld_4316.o \

1
src/lib/netlist/buildVS/netlistlib.vcxproj
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@ -123,6 +123,7 @@
<ClCompile Include="..\devices\nld_7497.cpp" />
<ClCompile Include="..\devices\nld_schmitt.cpp" />
<ClCompile Include="..\devices\nld_tms4800.cpp" />
<ClCompile Include="..\devices\nld_4013.cpp" />
<ClCompile Include="..\devices\nld_4020.cpp" />
<ClCompile Include="..\devices\nld_4066.cpp" />
<ClCompile Include="..\devices\nld_4316.cpp" />

6
src/lib/netlist/buildVS/netlistlib.vcxproj.filters
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@ -105,6 +105,9 @@
<ClCompile Include="..\devices\nld_82S115.cpp">
<Filter>Source Files</Filter>
</ClCompile>
<ClCompile Include="..\devices\nld_4013.cpp">
<Filter>Source Files</Filter>
</ClCompile>
<ClCompile Include="..\devices\nld_4020.cpp">
<Filter>Source Files</Filter>
</ClCompile>
@ -473,6 +476,9 @@
<ClInclude Include="..\devices\nlid_cmos.h">
<Filter>Header Files</Filter>
</ClInclude>
<ClInclude Include="..\devices\nld_4013.h">
<Filter>Header Files</Filter>
</ClInclude>
<ClInclude Include="..\devices\nld_4020.h">
<Filter>Header Files</Filter>
</ClInclude>

1
src/lib/netlist/devices/net_lib.h
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@ -48,6 +48,7 @@
#include "nld_2102A.h"
#include "nld_2716.h"
#include "nld_4006.h"
#include "nld_4013.h"
#include "nld_4020.h"
#include "nld_4066.h"
#include "nld_4316.h"

143
src/lib/netlist/devices/nld_4013.cpp Normal file
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@ -0,0 +1,143 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_4013.c
*
*/
#include "nld_4013.h"
#include "netlist/nl_base.h"
#include "nlid_system.h"
#include <array>
namespace netlist
{
namespace devices
{
NETLIB_OBJECT(4013)
{
NETLIB_CONSTRUCTOR(4013)
, m_D(*this, "DATA")
, m_RESET(*this, "RESET")
, m_SET(*this, "SET")
, m_CLK(*this, "CLOCK", NETLIB_DELEGATE(4013, clk))
, m_Q(*this, "Q")
, m_QQ(*this, "QQ")
, m_nextD(*this, "m_nextD", 0)
, m_power_pins(*this)
{
}
private:
NETLIB_RESETI();
NETLIB_UPDATEI();
NETLIB_HANDLERI(clk);
logic_input_t m_D;
logic_input_t m_RESET;
logic_input_t m_SET;
logic_input_t m_CLK;
logic_output_t m_Q;
logic_output_t m_QQ;
state_var<netlist_sig_t> m_nextD;
nld_power_pins m_power_pins;
void newstate_clk(const netlist_sig_t stateQ)
{
static constexpr delay = NLTIME_FROM_NS(150);
m_Q.push(stateQ, delay);
m_QQ.push(!stateQ, delay);
}
void newstate_setreset(const netlist_sig_t stateQ, const netlist_sig_t stateQQ)
{
// Q: 150 ns, QQ: 200 ns
static constexpr const std::array<netlist_time, 2> delay = { NLTIME_FROM_NS(150), NLTIME_FROM_NS(200) };
m_Q.push(stateQ, delay[0]);
m_QQ.push(stateQQ, delay[1]);
}
};
NETLIB_OBJECT(4013_dip)
{
NETLIB_CONSTRUCTOR(4013_dip)
NETLIB_FAMILY("CD4XXX")
, m_A(*this, "A")
, m_B(*this, "B")
{
register_subalias("1", "A.Q");
register_subalias("2", "A.QQ");
register_subalias("3", "A.CLOCK");
register_subalias("4", "A.RESET");
register_subalias("5", "A.DATA");
register_subalias("6", "A.SET");
register_subalias("7", "A.VSS");
register_subalias("8", "B.SET");
register_subalias("9", "B.DATA");
register_subalias("10", "B.RESET");
register_subalias("11", "B.CLOCK");
register_subalias("12", "B.QQ");
register_subalias("13", "B.Q");
register_subalias("14", "A.VDD");
connect("A.VSS", "B.VSS");
connect("A.VDD", "B.VDD");
}
NETLIB_UPDATEI();
NETLIB_RESETI();
private:
NETLIB_SUB(4013) m_A;
NETLIB_SUB(4013) m_B;
};
NETLIB_HANDLER(4013, clk)
{
newstate_clk(m_nextD);
m_CLK.inactivate();
}
NETLIB_UPDATE(4013)
{
const auto set(m_SET());
const auto reset(m_RESET());
if ((set ^ 1) & (reset ^ 1))
{
m_D.activate();
m_nextD = m_D();
m_CLK.activate_lh();
}
else
{
newstate_setreset(set, reset);
m_CLK.inactivate();
m_D.inactivate();
}
}
NETLIB_RESET(4013)
{
m_CLK.set_state(logic_t::STATE_INP_LH);
m_D.set_state(logic_t::STATE_INP_ACTIVE);
m_nextD = 0;
}
NETLIB_RESET(4013_dip)
{
}
NETLIB_UPDATE(4013_dip)
{
}
NETLIB_DEVICE_IMPL(CD4013, "CD4013", "+CLOCK,+DATA,+RESET,+SET,@VDD,@VSS")
NETLIB_DEVICE_IMPL(CD4013_DIP, "CD4013_DIP", "")
} //namespace devices
} // namespace netlist

59
src/lib/netlist/devices/nld_4013.h Normal file
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@ -0,0 +1,59 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_4013.h
*
* CD4013: Dual Positive-Edge-Triggered D Flip-Flops
* with Set, Reset and Complementary Outputs
*
* +--------------+
* Q1 |1 ++ 14| VDD
* Q1Q |2 13| Q2
* CLOCK1 |3 12| Q2Q
* RESET1 |4 4013 11| CLOCK2
* DATA1 |5 10| RESET2
* SET1 |6 9| DATA2
* VSS |7 8| SET2
* +--------------+
*
* +-----+-----+-----+---++---+-----+
* | SET | RES | CLK | D || Q | QQ |
* +=====+=====+=====+===++===+=====+
* | 1 | 0 | X | X || 1 | 0 |
* | 0 | 1 | X | X || 0 | 1 |
* | 1 | 1 | X | X || 1 | 1 | (*)
* | 0 | 0 | R | 1 || 1 | 0 |
* | 0 | 0 | R | 0 || 0 | 1 |
* | 0 | 0 | 0 | X || Q0| Q0Q |
* +-----+-----+-----+---++---+-----+
*
* (*) This configuration is not stable, i.e. it will not persist
* when either the preset and or clear inputs return to their inactive (high) level
*
* Q0 The output logic level of Q before the indicated input conditions were established
*
* R: 0 -. 1
*
* Naming conventions follow National Semiconductor datasheet
*
* FIXME: Check that (*) is emulated properly
*/
#ifndef NLD_4013_H_
#define NLD_4013_H_
#include "netlist/nl_setup.h"
#define CD4013(name, cCLOCK, cDATA, cRESET, cSET) \
NET_REGISTER_DEV(CD4013, name) \
NET_CONNECT(name, VSS, VSS) \
NET_CONNECT(name, VDD, VDD) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, DATA, cDATA) \
NET_CONNECT(name, SET, cSET) \
NET_CONNECT(name, RESET, cRESET)
#define CD4013_DIP(name) \
NET_REGISTER_DEV(CD4013_DIP, name)
#endif /* NLD_4013_H_ */

3
src/lib/netlist/devices/nld_devinc.h
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@ -906,6 +906,9 @@
#define CD4070_GATE(name) \
NET_REGISTER_DEVEXT(CD4070_GATE, name)
#define CD4069_GATE(name) \
NET_REGISTER_DEVEXT(CD4069_GATE, name)
#define CD4001_DIP(name) \
NET_REGISTER_DEVEXT(CD4001_DIP, name)

74
src/lib/netlist/macro/nlm_cd4xxx.cpp
View File

@ -7,13 +7,13 @@
* CD4001BC: Quad 2-Input NOR Buffered B Series Gate
*
* +--------------+
* A1 |1 ++ 14| VCC
* A1 |1 ++ 14| VDD
* B1 |2 13| A6
* A2 |3 12| Y6
* Y2 |4 4001 11| A5
* A3 |5 10| Y5
* Y3 |6 9| A4
* GND |7 8| Y4
* VSS |7 8| Y4
* +--------------+
*
*/
@ -24,16 +24,16 @@ static NETLIST_START(CD4001_DIP)
CD4001_GATE(s3)
CD4001_GATE(s4)
NET_C(s1.VCC, s2.VCC, s3.VCC, s4.VCC)
NET_C(s1.GND, s2.GND, s3.GND, s4.GND)
NET_C(s1.VDD, s2.VDD, s3.VDD, s4.VDD)
NET_C(s1.VSS, s2.VSS, s3.VSS, s4.VSS)
DIPPINS( /* +--------------+ */
s1.A, /* A1 |1 ++ 14| VDD */ s1.VCC,
s1.A, /* A1 |1 ++ 14| VDD */ s1.VDD,
s1.B, /* B1 |2 13| A6 */ s4.B,
s1.Q, /* A2 |3 12| Y6 */ s4.A,
s2.Q, /* Y2 |4 4001 11| A5 */ s4.Q,
s2.A, /* A3 |5 10| Y5 */ s3.Q,
s2.B, /* Y3 |6 9| A4 */ s3.B,
s1.GND, /* VSS |7 8| Y4 */ s3.A
s1.VSS, /* VSS |7 8| Y4 */ s3.A
/* +--------------+ */
)
@ -149,7 +149,45 @@ static NETLIST_START(CD4016_DIP)
NETLIST_END()
/*
* DM7486: Quad 2-Input Exclusive-OR Gates
* CD4069: Hex Inverter
* _
* Y = A
* +---++---+
* | A || Y |
* +===++===+
* | 0 || 1 |
* | 1 || 0 |
* +---++---+
*
* Naming conventions follow National Semiconductor datasheet
*
*/
static NETLIST_START(CD4069_DIP)
CD4069_GATE(A)
CD4069_GATE(B)
CD4069_GATE(C)
CD4069_GATE(D)
CD4069_GATE(E)
CD4069_GATE(F)
NET_C(A.VDD, B.VDD, C.VDD, D.VDD, E.VDD, E.VDD)
NET_C(A.VSS, B.VSS, C.VSS, D.VSS, E.VSS, F.VSS)
DIPPINS( /* +--------------+ */
A.A, /* A1 |1 ++ 14| VDD */ A.VDD,
A.Q, /* Y1 |2 13| A6 */ F.A,
B.A, /* A2 |3 12| Y6 */ F.Q,
B.Q, /* Y2 |4 4069 11| A5 */ E.A,
C.A, /* A3 |5 10| Y5 */ E.Q,
C.Q, /* Y3 |6 9| A4 */ D.A,
A.VSS,/* VSS |7 8| Y4 */ D.Q
/* +--------------+ */
)
NETLIST_END()
/*
* CD4070: Quad 2-Input Exclusive-OR Gates
*
* Y = A+B
* +---+---++---+
@ -161,8 +199,6 @@ NETLIST_END()
* | 1 | 1 || 0 |
* +---+---++---+
*
* Naming conventions follow National Semiconductor datasheet
*
*/
static NETLIST_START(CD4070_DIP)
@ -171,17 +207,17 @@ static NETLIST_START(CD4070_DIP)
CD4070_GATE(C)
CD4070_GATE(D)
NET_C(A.VCC, B.VCC, C.VCC, D.VCC)
NET_C(A.GND, B.GND, C.GND, D.GND)
NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
DIPPINS( /* +--------------+ */
A.A, /* A1 |1 ++ 14| VCC */ A.VCC,
A.A, /* A1 |1 ++ 14| VDD */ A.VDD,
A.B, /* B1 |2 13| B4 */ D.B,
A.Q, /* Y1 |3 12| A4 */ D.A,
B.Q, /* Y2 |4 7486 11| Y4 */ D.Q,
B.Q, /* Y2 |4 4070 11| Y4 */ D.Q,
B.A, /* A2 |5 10| Y3 */ C.Q,
B.B, /* B2 |6 9| B3 */ C.B,
A.GND,/* GND |7 8| A3 */ C.A
A.VSS,/* VSS |7 8| A3 */ C.A
/* +--------------+ */
)
NETLIST_END()
@ -220,12 +256,19 @@ NETLIST_START(CD4XXX_lib)
TRUTHTABLE_START(CD4001_GATE, 2, 1, "")
TT_HEAD("A , B | Q ")
TT_LINE("0,0|1|85")
TT_LINE("0,0|1|110")
TT_LINE("X,1|0|120")
TT_LINE("1,X|0|120")
TT_FAMILY("CD4XXX")
TRUTHTABLE_END()
TRUTHTABLE_START(CD4069_GATE, 1, 1, "")
TT_HEAD("A|Q ")
TT_LINE("0|1|55")
TT_LINE("1|0|55")
TT_FAMILY("CD4XXX")
TRUTHTABLE_END()
TRUTHTABLE_START(CD4070_GATE, 2, 1, "")
TT_HEAD("A,B|Q ")
TT_LINE("0,0|0|15")
@ -236,6 +279,7 @@ NETLIST_START(CD4XXX_lib)
TRUTHTABLE_END()
LOCAL_LIB_ENTRY(CD4001_DIP)
LOCAL_LIB_ENTRY(CD4069_DIP)
LOCAL_LIB_ENTRY(CD4070_DIP)
/* DIP ONLY */

6
src/lib/netlist/macro/nlm_cd4xxx.h
View File

@ -33,6 +33,12 @@
#define CD4001_DIP(name) \
NET_REGISTER_DEV(CD4001_DIP, name)
#define CD4069_GATE(name) \
NET_REGISTER_DEV(CD4069_GATE, name)
#define CD4069_DIP(name) \
NET_REGISTER_DEV(CD4069_DIP, name)
#define CD4070_GATE(name) \
NET_REGISTER_DEV(CD4070_GATE, name)