mirror of
https://github.com/holub/mame
synced 2025-05-16 10:52:43 +03:00
other two statics gone. nw.
This commit is contained in:
Fabio Priuli
parent
56ad9c1a60
commit
12ed314551
@ -682,6 +682,8 @@ public:
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void hdma_update(address_space &space, int dma);
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void hirq_tick();
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DECLARE_READ8_MEMBER(snes_io_dma_r);
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DECLARE_WRITE8_MEMBER(snes_io_dma_w);
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TIMER_CALLBACK_MEMBER(snes_nmi_tick);
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TIMER_CALLBACK_MEMBER(snes_hirq_tick_callback);
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TIMER_CALLBACK_MEMBER(snes_reset_oam_address);
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@ -31,12 +31,9 @@
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/* -- Globals -- */
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UINT8 *snes_ram = NULL; /* 65816 ram */
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static DECLARE_READ8_HANDLER(snes_io_dma_r);
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static DECLARE_WRITE8_HANDLER(snes_io_dma_w);
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struct snes_cart_info snes_cart;
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#define DMA_REG(a) state->m_dma_regs[a - 0x4300] // regs 0x4300-0x437f
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#define DMA_REG(a) m_dma_regs[a - 0x4300] // regs 0x4300-0x437f
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// add-on chip emulators
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#include "machine/snesobc1.c"
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@ -272,108 +269,104 @@ READ8_HANDLER( snes_open_bus_r )
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}
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/* read & write to DMA addresses are defined separately, to be called by snessdd1 handlers */
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static READ8_HANDLER( snes_io_dma_r )
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READ8_MEMBER( snes_state::snes_io_dma_r )
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{
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snes_state *state = space.machine().driver_data<snes_state>();
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switch (offset)
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{
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case DMAP0: case DMAP1: case DMAP2: case DMAP3: /*0x43n0*/
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case DMAP4: case DMAP5: case DMAP6: case DMAP7:
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return state->m_dma_channel[(offset >> 4) & 0x07].dmap;
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return m_dma_channel[(offset >> 4) & 0x07].dmap;
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case BBAD0: case BBAD1: case BBAD2: case BBAD3: /*0x43n1*/
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case BBAD4: case BBAD5: case BBAD6: case BBAD7:
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return state->m_dma_channel[(offset >> 4) & 0x07].dest_addr;
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return m_dma_channel[(offset >> 4) & 0x07].dest_addr;
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case A1T0L: case A1T1L: case A1T2L: case A1T3L: /*0x43n2*/
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case A1T4L: case A1T5L: case A1T6L: case A1T7L:
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return state->m_dma_channel[(offset >> 4) & 0x07].src_addr & 0xff;
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return m_dma_channel[(offset >> 4) & 0x07].src_addr & 0xff;
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case A1T0H: case A1T1H: case A1T2H: case A1T3H: /*0x43n3*/
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case A1T4H: case A1T5H: case A1T6H: case A1T7H:
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return (state->m_dma_channel[(offset >> 4) & 0x07].src_addr >> 8) & 0xff;
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return (m_dma_channel[(offset >> 4) & 0x07].src_addr >> 8) & 0xff;
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case A1B0: case A1B1: case A1B2: case A1B3: /*0x43n4*/
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case A1B4: case A1B5: case A1B6: case A1B7:
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return state->m_dma_channel[(offset >> 4) & 0x07].bank;
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return m_dma_channel[(offset >> 4) & 0x07].bank;
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case DAS0L: case DAS1L: case DAS2L: case DAS3L: /*0x43n5*/
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case DAS4L: case DAS5L: case DAS6L: case DAS7L:
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return state->m_dma_channel[(offset >> 4) & 0x07].trans_size & 0xff;
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return m_dma_channel[(offset >> 4) & 0x07].trans_size & 0xff;
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case DAS0H: case DAS1H: case DAS2H: case DAS3H: /*0x43n6*/
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case DAS4H: case DAS5H: case DAS6H: case DAS7H:
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return (state->m_dma_channel[(offset >> 4) & 0x07].trans_size >> 8) & 0xff;
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return (m_dma_channel[(offset >> 4) & 0x07].trans_size >> 8) & 0xff;
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case DSAB0: case DSAB1: case DSAB2: case DSAB3: /*0x43n7*/
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case DSAB4: case DSAB5: case DSAB6: case DSAB7:
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return state->m_dma_channel[(offset >> 4) & 0x07].ibank;
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return m_dma_channel[(offset >> 4) & 0x07].ibank;
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case A2A0L: case A2A1L: case A2A2L: case A2A3L: /*0x43n8*/
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case A2A4L: case A2A5L: case A2A6L: case A2A7L:
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return state->m_dma_channel[(offset >> 4) & 0x07].hdma_addr & 0xff;
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return m_dma_channel[(offset >> 4) & 0x07].hdma_addr & 0xff;
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case A2A0H: case A2A1H: case A2A2H: case A2A3H: /*0x43n9*/
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case A2A4H: case A2A5H: case A2A6H: case A2A7H:
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return (state->m_dma_channel[(offset >> 4) & 0x07].hdma_addr >> 8) & 0xff;
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return (m_dma_channel[(offset >> 4) & 0x07].hdma_addr >> 8) & 0xff;
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case NTRL0: case NTRL1: case NTRL2: case NTRL3: /*0x43na*/
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case NTRL4: case NTRL5: case NTRL6: case NTRL7:
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return state->m_dma_channel[(offset >> 4) & 0x07].hdma_line_counter;
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return m_dma_channel[(offset >> 4) & 0x07].hdma_line_counter;
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case 0x430b: case 0x431b: case 0x432b: case 0x433b: /* according to bsnes, this does not return open_bus (even if its precise effect is unknown) */
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case 0x434b: case 0x435b: case 0x436b: case 0x437b:
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return state->m_dma_channel[(offset >> 4) & 0x07].unk;
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return m_dma_channel[(offset >> 4) & 0x07].unk;
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}
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/* we should never arrive here */
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return snes_open_bus_r(space, 0);
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}
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static WRITE8_HANDLER( snes_io_dma_w )
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WRITE8_HANDLER( snes_state::snes_io_dma_w )
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{
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snes_state *state = space.machine().driver_data<snes_state>();
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switch (offset)
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{
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/* Below is all DMA related */
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case DMAP0: case DMAP1: case DMAP2: case DMAP3: /*0x43n0*/
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case DMAP4: case DMAP5: case DMAP6: case DMAP7:
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state->m_dma_channel[(offset >> 4) & 0x07].dmap = data;
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m_dma_channel[(offset >> 4) & 0x07].dmap = data;
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break;
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case BBAD0: case BBAD1: case BBAD2: case BBAD3: /*0x43n1*/
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case BBAD4: case BBAD5: case BBAD6: case BBAD7:
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state->m_dma_channel[(offset >> 4) & 0x07].dest_addr = data;
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m_dma_channel[(offset >> 4) & 0x07].dest_addr = data;
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break;
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case A1T0L: case A1T1L: case A1T2L: case A1T3L: /*0x43n2*/
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case A1T4L: case A1T5L: case A1T6L: case A1T7L:
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state->m_dma_channel[(offset >> 4) & 0x07].src_addr = (state->m_dma_channel[(offset >> 4) & 0x07].src_addr & 0xff00) | (data << 0);
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m_dma_channel[(offset >> 4) & 0x07].src_addr = (m_dma_channel[(offset >> 4) & 0x07].src_addr & 0xff00) | (data << 0);
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break;
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case A1T0H: case A1T1H: case A1T2H: case A1T3H: /*0x43n3*/
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case A1T4H: case A1T5H: case A1T6H: case A1T7H:
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state->m_dma_channel[(offset >> 4) & 0x07].src_addr = (state->m_dma_channel[(offset >> 4) & 0x07].src_addr & 0x00ff) | (data << 8);
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m_dma_channel[(offset >> 4) & 0x07].src_addr = (m_dma_channel[(offset >> 4) & 0x07].src_addr & 0x00ff) | (data << 8);
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break;
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case A1B0: case A1B1: case A1B2: case A1B3: /*0x43n4*/
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case A1B4: case A1B5: case A1B6: case A1B7:
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state->m_dma_channel[(offset >> 4) & 0x07].bank = data;
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m_dma_channel[(offset >> 4) & 0x07].bank = data;
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break;
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case DAS0L: case DAS1L: case DAS2L: case DAS3L: /*0x43n5*/
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case DAS4L: case DAS5L: case DAS6L: case DAS7L:
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state->m_dma_channel[(offset >> 4) & 0x07].trans_size = (state->m_dma_channel[(offset >> 4) & 0x07].trans_size & 0xff00) | (data << 0);
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m_dma_channel[(offset >> 4) & 0x07].trans_size = (m_dma_channel[(offset >> 4) & 0x07].trans_size & 0xff00) | (data << 0);
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break;
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case DAS0H: case DAS1H: case DAS2H: case DAS3H: /*0x43n6*/
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case DAS4H: case DAS5H: case DAS6H: case DAS7H:
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state->m_dma_channel[(offset >> 4) & 0x07].trans_size = (state->m_dma_channel[(offset >> 4) & 0x07].trans_size & 0x00ff) | (data << 8);
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m_dma_channel[(offset >> 4) & 0x07].trans_size = (m_dma_channel[(offset >> 4) & 0x07].trans_size & 0x00ff) | (data << 8);
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break;
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case DSAB0: case DSAB1: case DSAB2: case DSAB3: /*0x43n7*/
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case DSAB4: case DSAB5: case DSAB6: case DSAB7:
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state->m_dma_channel[(offset >> 4) & 0x07].ibank = data;
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m_dma_channel[(offset >> 4) & 0x07].ibank = data;
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break;
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case A2A0L: case A2A1L: case A2A2L: case A2A3L: /*0x43n8*/
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case A2A4L: case A2A5L: case A2A6L: case A2A7L:
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state->m_dma_channel[(offset >> 4) & 0x07].hdma_addr = (state->m_dma_channel[(offset >> 4) & 0x07].hdma_addr & 0xff00) | (data << 0);
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m_dma_channel[(offset >> 4) & 0x07].hdma_addr = (m_dma_channel[(offset >> 4) & 0x07].hdma_addr & 0xff00) | (data << 0);
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break;
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case A2A0H: case A2A1H: case A2A2H: case A2A3H: /*0x43n9*/
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case A2A4H: case A2A5H: case A2A6H: case A2A7H:
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state->m_dma_channel[(offset >> 4) & 0x07].hdma_addr = (state->m_dma_channel[(offset >> 4) & 0x07].hdma_addr & 0x00ff) | (data << 8);
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m_dma_channel[(offset >> 4) & 0x07].hdma_addr = (m_dma_channel[(offset >> 4) & 0x07].hdma_addr & 0x00ff) | (data << 8);
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break;
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case NTRL0: case NTRL1: case NTRL2: case NTRL3: /*0x43na*/
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case NTRL4: case NTRL5: case NTRL6: case NTRL7:
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state->m_dma_channel[(offset >> 4) & 0x07].hdma_line_counter = data;
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m_dma_channel[(offset >> 4) & 0x07].hdma_line_counter = data;
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break;
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case 0x430b: case 0x431b: case 0x432b: case 0x433b:
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case 0x434b: case 0x435b: case 0x436b: case 0x437b:
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state->m_dma_channel[(offset >> 4) & 0x07].unk = data;
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m_dma_channel[(offset >> 4) & 0x07].unk = data;
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break;
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}
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@ -406,7 +399,7 @@ READ8_HANDLER( snes_r_io )
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// DMA accesses are from 4300 to 437f
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if (offset >= DMAP0 && offset < 0x4380)
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{
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return snes_io_dma_r(space, offset);
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return state->snes_io_dma_r(space, offset);
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}
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/* offset is from 0x000000 */
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@ -509,7 +502,7 @@ WRITE8_HANDLER( snes_w_io )
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// DMA accesses are from 4300 to 437f
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if (offset >= DMAP0 && offset < 0x4380)
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{
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snes_io_dma_w(space, offset, data);
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state->snes_io_dma_w(space, offset, data);
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return;
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}
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