mirror of
https://github.com/holub/mame
synced 2025-05-22 21:58:57 +03:00
Switched m68000 core to new memory functions
This commit is contained in:
Couriersud
parent
a46691cd90
commit
13bd16a090
@ -465,7 +465,7 @@ OP_HANDLER( swi )
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PUSHBYTE(B);
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PUSHBYTE(CC);
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SEI;
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PCD = RM16(0xfffa);
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PCD = RM16(m68_state, 0xfffa);
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CHANGE_PC(m68_state);
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}
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@ -1108,7 +1108,7 @@ OP_HANDLER( sts_im )
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CLR_NZV;
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SET_NZ16(S);
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IMM16;
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WM16(EAD,&m68_state->s);
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WM16(m68_state, EAD,&m68_state->s);
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}
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/* $90 SUBA direct ?**** */
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@ -1275,7 +1275,7 @@ OP_HANDLER( sts_di )
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CLR_NZV;
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SET_NZ16(S);
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DIRECT;
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WM16(EAD,&m68_state->s);
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WM16(m68_state, EAD,&m68_state->s);
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}
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/* $a0 SUBA indexed ?**** */
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@ -1450,7 +1450,7 @@ OP_HANDLER( sts_ix )
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CLR_NZV;
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SET_NZ16(S);
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INDEXED;
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WM16(EAD,&m68_state->s);
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WM16(m68_state, EAD,&m68_state->s);
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}
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/* $b0 SUBA extended ?**** */
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@ -1627,7 +1627,7 @@ OP_HANDLER( sts_ex )
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CLR_NZV;
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SET_NZ16(S);
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EXTENDED;
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WM16(EAD,&m68_state->s);
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WM16(m68_state, EAD,&m68_state->s);
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}
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/* $c0 SUBB immediate ?**** */
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@ -1772,7 +1772,7 @@ OP_HANDLER( std_im )
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IMM16;
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CLR_NZV;
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SET_NZ16(D);
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WM16(EAD,&m68_state->d);
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WM16(m68_state, EAD,&m68_state->d);
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}
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/* $ce LDX immediate -**0- */
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@ -1789,7 +1789,7 @@ OP_HANDLER( stx_im )
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CLR_NZV;
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SET_NZ16(X);
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IMM16;
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WM16(EAD,&m68_state->x);
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WM16(m68_state, EAD,&m68_state->x);
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}
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/* $d0 SUBB direct ?**** */
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@ -1932,7 +1932,7 @@ OP_HANDLER( std_di )
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DIRECT;
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CLR_NZV;
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SET_NZ16(D);
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WM16(EAD,&m68_state->d);
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WM16(m68_state, EAD,&m68_state->d);
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}
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/* $de LDX direct -**0- */
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@ -1949,7 +1949,7 @@ OP_HANDLER( stx_di )
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CLR_NZV;
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SET_NZ16(X);
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DIRECT;
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WM16(EAD,&m68_state->x);
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WM16(m68_state, EAD,&m68_state->x);
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}
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/* $e0 SUBB indexed ?**** */
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@ -2104,7 +2104,7 @@ OP_HANDLER( std_ix )
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INDEXED;
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CLR_NZV;
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SET_NZ16(D);
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WM16(EAD,&m68_state->d);
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WM16(m68_state, EAD,&m68_state->d);
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}
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/* $ee LDX indexed -**0- */
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@ -2121,7 +2121,7 @@ OP_HANDLER( stx_ix )
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CLR_NZV;
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SET_NZ16(X);
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INDEXED;
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WM16(EAD,&m68_state->x);
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WM16(m68_state, EAD,&m68_state->x);
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}
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/* $f0 SUBB extended ?**** */
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@ -2277,7 +2277,7 @@ OP_HANDLER( std_ex )
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EXTENDED;
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CLR_NZV;
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SET_NZ16(D);
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WM16(EAD,&m68_state->d);
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WM16(m68_state, EAD,&m68_state->d);
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}
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/* $fe LDX extended -**0- */
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@ -2294,5 +2294,5 @@ OP_HANDLER( stx_ex )
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CLR_NZV;
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SET_NZ16(X);
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EXTENDED;
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WM16(EAD,&m68_state->x);
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WM16(m68_state, EAD,&m68_state->x);
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}
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@ -73,6 +73,8 @@ TODO:
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*/
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#define NO_LEGACY_MEMORY_HANDLERS 1
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#include "debugger.h"
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#include "deprecat.h"
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#include "m6800.h"
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@ -113,6 +115,12 @@ struct _m68_state_t
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cpu_irq_callback irq_callback;
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const device_config *device;
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/* Memory spaces */
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const address_space *program;
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const address_space *data;
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const address_space *io;
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int extra_cycles; /* cycles used for interrupts */
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void (* const * insn)(m68_state_t *); /* instruction table */
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const UINT8 *cycles; /* clock cycle of instruction table */
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@ -189,26 +197,26 @@ static UINT32 timer_next;
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/****************************************************************************/
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/* Read a byte from given memory location */
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/****************************************************************************/
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#define RM(Addr) ((unsigned)program_read_byte_8be(Addr))
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#define RM(Addr) ((unsigned)memory_read_byte_8be(m68_state->program, Addr))
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/****************************************************************************/
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/* Write a byte to given memory location */
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/****************************************************************************/
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#define WM(Addr,Value) (program_write_byte_8be(Addr,Value))
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#define WM(Addr,Value) (memory_write_byte_8be(m68_state->program, Addr,Value))
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/****************************************************************************/
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/* M6800_RDOP() is identical to M6800_RDMEM() except it is used for reading */
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/* opcodes. In case of system with memory mapped I/O, this function can be */
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/* used to greatly speed up emulation */
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/****************************************************************************/
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#define M_RDOP(Addr) ((unsigned)program_decrypted_read_byte(Addr))
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#define M_RDOP(Addr) ((unsigned)memory_decrypted_read_byte(m68_state->program, Addr))
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/****************************************************************************/
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/* M6800_RDOP_ARG() is identical to M6800_RDOP() but it's used for reading */
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/* opcode arguments. This difference can be used to support systems that */
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/* use different encoding mechanisms for opcodes and opcode arguments */
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/****************************************************************************/
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#define M_RDOP_ARG(Addr) ((unsigned)program_raw_read_byte(Addr))
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#define M_RDOP_ARG(Addr) ((unsigned)memory_raw_read_byte(m68_state->program, Addr))
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/* macros to access memory */
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#define IMMBYTE(b) b = M_RDOP_ARG(PCD); PC++
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@ -400,12 +408,12 @@ static const UINT8 flags8d[256]= /* decrement */
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/* macros for convenience */
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#define DIRBYTE(b) {DIRECT;b=RM(EAD);}
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#define DIRWORD(w) {DIRECT;w.d=RM16(EAD);}
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#define DIRWORD(w) {DIRECT;w.d=RM16(m68_state, EAD);}
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#define EXTBYTE(b) {EXTENDED;b=RM(EAD);}
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#define EXTWORD(w) {EXTENDED;w.d=RM16(EAD);}
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#define EXTWORD(w) {EXTENDED;w.d=RM16(m68_state, EAD);}
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#define IDXBYTE(b) {INDEXED;b=RM(EAD);}
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#define IDXWORD(w) {INDEXED;w.d=RM16(EAD);}
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#define IDXWORD(w) {INDEXED;w.d=RM16(m68_state, EAD);}
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/* Macros for branch instructions */
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#define CHANGE_PC(m68_state) change_pc(PCD)
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@ -513,13 +521,13 @@ static const UINT8 cycles_nsc8105[] =
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} \
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}
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INLINE UINT32 RM16( UINT32 Addr )
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INLINE UINT32 RM16(m68_state_t *m68_state, UINT32 Addr )
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{
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UINT32 result = RM(Addr) << 8;
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return result | RM((Addr+1)&0xffff);
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}
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INLINE void WM16( UINT32 Addr, PAIR *p )
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INLINE void WM16(m68_state_t *m68_state, UINT32 Addr, PAIR *p )
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{
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WM( Addr, p->b.h );
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WM( (Addr+1)&0xffff, p->b.l );
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@ -545,7 +553,7 @@ static void enter_interrupt(m68_state_t *m68_state, const char *message,UINT16 i
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m68_state->extra_cycles += 12;
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}
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SEI;
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PCD = RM16( irq_vector );
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PCD = RM16(m68_state, irq_vector );
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CHANGE_PC(m68_state);
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}
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@ -642,15 +650,15 @@ static void m6800_tx(m68_state_t *m68_state, int value)
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m68_state->port2_data = (m68_state->port2_data & 0xef) | (value << 4);
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if(m68_state->port2_ddr == 0xff)
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io_write_byte_8be(M6803_PORT2,m68_state->port2_data);
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memory_write_byte_8be(m68_state->io, M6803_PORT2,m68_state->port2_data);
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else
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io_write_byte_8be(M6803_PORT2,(m68_state->port2_data & m68_state->port2_ddr)
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| (io_read_byte_8be(M6803_PORT2) & (m68_state->port2_ddr ^ 0xff)));
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memory_write_byte_8be(m68_state->io, M6803_PORT2,(m68_state->port2_data & m68_state->port2_ddr)
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| (memory_read_byte_8be(m68_state->io, M6803_PORT2) & (m68_state->port2_ddr ^ 0xff)));
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}
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static int m6800_rx(m68_state_t *m68_state)
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{
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return (io_read_byte_8be(M6803_PORT2) & M6800_PORT2_IO3) >> 3;
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return (memory_read_byte_8be(m68_state->io, M6803_PORT2) & M6800_PORT2_IO3) >> 3;
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}
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static TIMER_CALLBACK(m6800_tx_tick)
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@ -881,7 +889,12 @@ static void state_register(m68_state_t *m68_state, const char *type)
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static CPU_INIT( m6800 )
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{
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m68_state_t *m68_state = device->token;
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// m68_state->subtype = SUBTYPE_M6800;
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m68_state->program = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM);
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m68_state->data = cpu_get_address_space(device, ADDRESS_SPACE_DATA);
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m68_state->io = cpu_get_address_space(device, ADDRESS_SPACE_IO);
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// m68_state->subtype = SUBTYPE_M6800;
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m68_state->insn = m6800_insn;
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m68_state->cycles = cycles_6800;
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m68_state->irq_callback = irqcallback;
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@ -894,7 +907,7 @@ static CPU_RESET( m6800 )
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m68_state_t *m68_state = device->token;
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SEI; /* IRQ disabled */
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PCD = RM16( 0xfffe );
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PCD = RM16(m68_state, 0xfffe );
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CHANGE_PC(m68_state);
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m68_state->wai_state = 0;
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@ -1311,6 +1324,10 @@ static CPU_INIT( m6801 )
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m68_state->irq_callback = irqcallback;
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m68_state->device = device;
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m68_state->program = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM);
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m68_state->data = cpu_get_address_space(device, ADDRESS_SPACE_DATA);
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m68_state->io = cpu_get_address_space(device, ADDRESS_SPACE_IO);
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m68_state->clock = clock;
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m68_state->m6800_rx_timer = timer_alloc(m6800_rx_tick, m68_state);
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m68_state->m6800_tx_timer = timer_alloc(m6800_tx_tick, m68_state);
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@ -1331,6 +1348,11 @@ static CPU_INIT( m6802 )
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m68_state->cycles = cycles_6800;
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m68_state->irq_callback = irqcallback;
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m68_state->device = device;
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m68_state->program = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM);
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m68_state->data = cpu_get_address_space(device, ADDRESS_SPACE_DATA);
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m68_state->io = cpu_get_address_space(device, ADDRESS_SPACE_IO);
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state_register(m68_state, "m6802");
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}
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#endif
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@ -1348,6 +1370,10 @@ static CPU_INIT( m6803 )
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m68_state->irq_callback = irqcallback;
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m68_state->device = device;
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m68_state->program = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM);
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m68_state->data = cpu_get_address_space(device, ADDRESS_SPACE_DATA);
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m68_state->io = cpu_get_address_space(device, ADDRESS_SPACE_IO);
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m68_state->clock = clock;
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m68_state->m6800_rx_timer = timer_alloc(m6800_rx_tick, m68_state);
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m68_state->m6800_tx_timer = timer_alloc(m6800_tx_tick, m68_state);
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@ -1686,6 +1712,11 @@ static CPU_INIT( m6808 )
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m68_state->cycles = cycles_6800;
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m68_state->irq_callback = irqcallback;
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m68_state->device = device;
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m68_state->program = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM);
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m68_state->data = cpu_get_address_space(device, ADDRESS_SPACE_DATA);
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m68_state->io = cpu_get_address_space(device, ADDRESS_SPACE_IO);
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state_register(m68_state, "m6808");
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}
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#endif
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@ -1704,6 +1735,10 @@ static CPU_INIT( hd63701 )
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m68_state->irq_callback = irqcallback;
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m68_state->device = device;
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m68_state->program = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM);
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m68_state->data = cpu_get_address_space(device, ADDRESS_SPACE_DATA);
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m68_state->io = cpu_get_address_space(device, ADDRESS_SPACE_IO);
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m68_state->clock = clock;
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m68_state->m6800_rx_timer = timer_alloc(m6800_rx_tick, m68_state);
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m68_state->m6800_tx_timer = timer_alloc(m6800_tx_tick, m68_state);
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@ -2051,6 +2086,12 @@ static CPU_INIT( nsc8105 )
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{
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m68_state_t *m68_state = device->token;
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// m68_state->subtype = SUBTYPE_NSC8105;
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m68_state->device = device;
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m68_state->program = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM);
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m68_state->data = cpu_get_address_space(device, ADDRESS_SPACE_DATA);
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m68_state->io = cpu_get_address_space(device, ADDRESS_SPACE_IO);
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m68_state->insn = nsc8105_insn;
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m68_state->cycles = cycles_nsc8105;
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state_register(m68_state, "nsc8105");
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@ -2374,20 +2415,20 @@ static READ8_HANDLER( m6803_internal_registers_r )
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case 0x01:
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return m68_state->port2_ddr;
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case 0x02:
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return (io_read_byte_8be(M6803_PORT1) & (m68_state->port1_ddr ^ 0xff))
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return (memory_read_byte_8be(m68_state->io, M6803_PORT1) & (m68_state->port1_ddr ^ 0xff))
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| (m68_state->port1_data & m68_state->port1_ddr);
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case 0x03:
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return (io_read_byte_8be(M6803_PORT2) & (m68_state->port2_ddr ^ 0xff))
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return (memory_read_byte_8be(m68_state->io, M6803_PORT2) & (m68_state->port2_ddr ^ 0xff))
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| (m68_state->port2_data & m68_state->port2_ddr);
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case 0x04:
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return m68_state->port3_ddr;
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case 0x05:
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return m68_state->port4_ddr;
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case 0x06:
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return (io_read_byte_8be(M6803_PORT3) & (m68_state->port3_ddr ^ 0xff))
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return (memory_read_byte_8be(m68_state->io, M6803_PORT3) & (m68_state->port3_ddr ^ 0xff))
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| (m68_state->port3_data & m68_state->port3_ddr);
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case 0x07:
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return (io_read_byte_8be(M6803_PORT4) & (m68_state->port4_ddr ^ 0xff))
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return (memory_read_byte_8be(m68_state->io, M6803_PORT4) & (m68_state->port4_ddr ^ 0xff))
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| (m68_state->port4_data & m68_state->port4_ddr);
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case 0x08:
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m68_state->pending_tcsr = 0;
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@ -2472,10 +2513,10 @@ static WRITE8_HANDLER( m6803_internal_registers_w )
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{
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m68_state->port1_ddr = data;
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if(m68_state->port1_ddr == 0xff)
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io_write_byte_8be(M6803_PORT1,m68_state->port1_data);
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memory_write_byte_8be(m68_state->io, M6803_PORT1,m68_state->port1_data);
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else
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io_write_byte_8be(M6803_PORT1,(m68_state->port1_data & m68_state->port1_ddr)
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| (io_read_byte_8be(M6803_PORT1) & (m68_state->port1_ddr ^ 0xff)));
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memory_write_byte_8be(m68_state->io, M6803_PORT1,(m68_state->port1_data & m68_state->port1_ddr)
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| (memory_read_byte_8be(m68_state->io, M6803_PORT1) & (m68_state->port1_ddr ^ 0xff)));
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}
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break;
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case 0x01:
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@ -2483,10 +2524,10 @@ static WRITE8_HANDLER( m6803_internal_registers_w )
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{
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m68_state->port2_ddr = data;
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if(m68_state->port2_ddr == 0xff)
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io_write_byte_8be(M6803_PORT2,m68_state->port2_data);
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memory_write_byte_8be(m68_state->io, M6803_PORT2,m68_state->port2_data);
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else
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io_write_byte_8be(M6803_PORT2,(m68_state->port2_data & m68_state->port2_ddr)
|
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| (io_read_byte_8be(M6803_PORT2) & (m68_state->port2_ddr ^ 0xff)));
|
||||
memory_write_byte_8be(m68_state->io, M6803_PORT2,(m68_state->port2_data & m68_state->port2_ddr)
|
||||
| (memory_read_byte_8be(m68_state->io, M6803_PORT2) & (m68_state->port2_ddr ^ 0xff)));
|
||||
|
||||
if (m68_state->port2_ddr & 2)
|
||||
logerror("CPU #%d PC %04x: warning - port 2 bit 1 set as output (OLVL) - not supported\n",cpunum_get_active(),cpu_get_pc(space->cpu));
|
||||
@ -2495,10 +2536,10 @@ static WRITE8_HANDLER( m6803_internal_registers_w )
|
||||
case 0x02:
|
||||
m68_state->port1_data = data;
|
||||
if(m68_state->port1_ddr == 0xff)
|
||||
io_write_byte_8be(M6803_PORT1,m68_state->port1_data);
|
||||
memory_write_byte_8be(m68_state->io, M6803_PORT1,m68_state->port1_data);
|
||||
else
|
||||
io_write_byte_8be(M6803_PORT1,(m68_state->port1_data & m68_state->port1_ddr)
|
||||
| (io_read_byte_8be(M6803_PORT1) & (m68_state->port1_ddr ^ 0xff)));
|
||||
memory_write_byte_8be(m68_state->io, M6803_PORT1,(m68_state->port1_data & m68_state->port1_ddr)
|
||||
| (memory_read_byte_8be(m68_state->io, M6803_PORT1) & (m68_state->port1_ddr ^ 0xff)));
|
||||
break;
|
||||
case 0x03:
|
||||
if (m68_state->trcsr & M6800_TRCSR_TE)
|
||||
@ -2510,20 +2551,20 @@ static WRITE8_HANDLER( m6803_internal_registers_w )
|
||||
m68_state->port2_data = data;
|
||||
}
|
||||
if(m68_state->port2_ddr == 0xff)
|
||||
io_write_byte_8be(M6803_PORT2,m68_state->port2_data);
|
||||
memory_write_byte_8be(m68_state->io, M6803_PORT2,m68_state->port2_data);
|
||||
else
|
||||
io_write_byte_8be(M6803_PORT2,(m68_state->port2_data & m68_state->port2_ddr)
|
||||
| (io_read_byte_8be(M6803_PORT2) & (m68_state->port2_ddr ^ 0xff)));
|
||||
memory_write_byte_8be(m68_state->io, M6803_PORT2,(m68_state->port2_data & m68_state->port2_ddr)
|
||||
| (memory_read_byte_8be(m68_state->io, M6803_PORT2) & (m68_state->port2_ddr ^ 0xff)));
|
||||
break;
|
||||
case 0x04:
|
||||
if (m68_state->port3_ddr != data)
|
||||
{
|
||||
m68_state->port3_ddr = data;
|
||||
if(m68_state->port3_ddr == 0xff)
|
||||
io_write_byte_8be(M6803_PORT3,m68_state->port3_data);
|
||||
memory_write_byte_8be(m68_state->io, M6803_PORT3,m68_state->port3_data);
|
||||
else
|
||||
io_write_byte_8be(M6803_PORT3,(m68_state->port3_data & m68_state->port3_ddr)
|
||||
| (io_read_byte_8be(M6803_PORT3) & (m68_state->port3_ddr ^ 0xff)));
|
||||
memory_write_byte_8be(m68_state->io, M6803_PORT3,(m68_state->port3_data & m68_state->port3_ddr)
|
||||
| (memory_read_byte_8be(m68_state->io, M6803_PORT3) & (m68_state->port3_ddr ^ 0xff)));
|
||||
}
|
||||
break;
|
||||
case 0x05:
|
||||
@ -2531,27 +2572,27 @@ static WRITE8_HANDLER( m6803_internal_registers_w )
|
||||
{
|
||||
m68_state->port4_ddr = data;
|
||||
if(m68_state->port4_ddr == 0xff)
|
||||
io_write_byte_8be(M6803_PORT4,m68_state->port4_data);
|
||||
memory_write_byte_8be(m68_state->io, M6803_PORT4,m68_state->port4_data);
|
||||
else
|
||||
io_write_byte_8be(M6803_PORT4,(m68_state->port4_data & m68_state->port4_ddr)
|
||||
| (io_read_byte_8be(M6803_PORT4) & (m68_state->port4_ddr ^ 0xff)));
|
||||
memory_write_byte_8be(m68_state->io, M6803_PORT4,(m68_state->port4_data & m68_state->port4_ddr)
|
||||
| (memory_read_byte_8be(m68_state->io, M6803_PORT4) & (m68_state->port4_ddr ^ 0xff)));
|
||||
}
|
||||
break;
|
||||
case 0x06:
|
||||
m68_state->port3_data = data;
|
||||
if(m68_state->port3_ddr == 0xff)
|
||||
io_write_byte_8be(M6803_PORT3,m68_state->port3_data);
|
||||
memory_write_byte_8be(m68_state->io, M6803_PORT3,m68_state->port3_data);
|
||||
else
|
||||
io_write_byte_8be(M6803_PORT3,(m68_state->port3_data & m68_state->port3_ddr)
|
||||
| (io_read_byte_8be(M6803_PORT3) & (m68_state->port3_ddr ^ 0xff)));
|
||||
memory_write_byte_8be(m68_state->io, M6803_PORT3,(m68_state->port3_data & m68_state->port3_ddr)
|
||||
| (memory_read_byte_8be(m68_state->io, M6803_PORT3) & (m68_state->port3_ddr ^ 0xff)));
|
||||
break;
|
||||
case 0x07:
|
||||
m68_state->port4_data = data;
|
||||
if(m68_state->port4_ddr == 0xff)
|
||||
io_write_byte_8be(M6803_PORT4,m68_state->port4_data);
|
||||
memory_write_byte_8be(m68_state->io, M6803_PORT4,m68_state->port4_data);
|
||||
else
|
||||
io_write_byte_8be(M6803_PORT4,(m68_state->port4_data & m68_state->port4_ddr)
|
||||
| (io_read_byte_8be(M6803_PORT4) & (m68_state->port4_ddr ^ 0xff)));
|
||||
memory_write_byte_8be(m68_state->io, M6803_PORT4,(m68_state->port4_data & m68_state->port4_ddr)
|
||||
| (memory_read_byte_8be(m68_state->io, M6803_PORT4) & (m68_state->port4_ddr ^ 0xff)));
|
||||
break;
|
||||
case 0x08:
|
||||
m68_state->tcsr = data;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user