mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
-hazeltin: Added netlist-based video board emulation. [Ryan Holtz]
This commit is contained in:
therealmogminer@gmail.com
parent
2987115966
commit
1410c438b7
@ -1094,6 +1094,8 @@ files {
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MAME_DIR .. "src/mame/machine/nl_pongd.h",
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MAME_DIR .. "src/mame/machine/nl_breakout.cpp",
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MAME_DIR .. "src/mame/machine/nl_breakout.h",
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MAME_DIR .. "src/mame/machine/nl_hazelvid.cpp",
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MAME_DIR .. "src/mame/machine/nl_hazelvid.h",
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MAME_DIR .. "src/mame/drivers/poolshrk.cpp",
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MAME_DIR .. "src/mame/includes/poolshrk.h",
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MAME_DIR .. "src/mame/audio/poolshrk.cpp",
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@ -112,6 +112,8 @@ files{
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MAME_DIR .. "src/mame/machine/nl_pongd.h",
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MAME_DIR .. "src/mame/machine/nl_breakout.cpp",
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MAME_DIR .. "src/mame/machine/nl_breakout.h",
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MAME_DIR .. "src/mame/machine/nl_hazelvid.cpp",
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MAME_DIR .. "src/mame/machine/nl_hazelvid.h",
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MAME_DIR .. "src/mame/drivers/1942.cpp",
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MAME_DIR .. "src/mame/includes/1942.h",
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@ -7,8 +7,16 @@
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perliminary driver by Ryan Holtz
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TODO:
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- pretty much everything
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TODO (roughly in order of importance):
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- Figure out the correct keyboard decoding.
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- Proper RS232 hookup.
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- Iron out proper horizontal and vertical start/end values.
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- Hook up /FGBIT, REV FLD FRAME, and REV VIDEO SELECT lines on video
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board.
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- Reimplement logic probe (since removed) as a netlist device so other
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devs can use it.
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- Implement /BRESET line in netlist to possibly smooth out some sync
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issues.
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References:
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[1]: Hazeltine_1500_Series_Maintenance_Manual_Dec77.pdf, on Bitsavers
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@ -17,64 +25,35 @@ References:
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#include "emu.h"
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#include "cpu/i8085/i8085.h"
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#include "machine/7400.h"
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#include "machine/7404.h"
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#include "machine/7474.h"
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#include "machine/74161.h"
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#include "machine/74175.h"
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#include "machine/82s129.h"
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#include "machine/am2847.h"
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#include "machine/ay31015.h"
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#include "machine/clock.h"
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#include "machine/com8116.h"
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#include "machine/dm9334.h"
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#include "machine/kb3600.h"
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#include "machine/netlist.h"
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#include "machine/nl_hazelvid.h"
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#include "netlist/devices/net_lib.h"
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#define CPU_TAG "maincpu"
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#define NETLIST_TAG "videobrd"
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#define UART_TAG "uart"
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#define BAUDGEN_TAG "baudgen"
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#define KBDC_TAG "ay53600"
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#define CHARRAM_TAG "chrram"
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#define CHARROM_TAG "chargen"
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#define BAUDPORT_TAG "baud"
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#define MISCPORT_TAG "misc"
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#define MISCKEYS_TAG "misc_keys"
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#define SCREEN_TAG "screen"
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#define TMS3409A_TAG "u67"
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#define TMS3409B_TAG "u57"
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#define DOTCLK_TAG "dotclk"
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#define DOTCLK_DISP_TAG "dotclk_dispatch"
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#define CHAR_CTR_CLK_TAG "ch_bucket_ctr_clk"
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#define U58_TAG "u58"
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#define U59_TAG "u59"
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#define VID_PROM_ADDR_RESET_TAG "u59_y5"
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#define U61_TAG "u61"
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#define U68_TAG "u68"
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#define U69_PROMMSB_TAG "u69"
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#define U70_PROMLSB_TAG "u70"
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#define U70_TC_LINE_TAG "u70_tc"
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#define U71_PROM_TAG "u71"
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#define U72_PROMDEC_TAG "u72"
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#define U81_TAG "u81"
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#define U83_TAG "u83"
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#define U84_DIV11_TAG "u84"
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#define U85_VERT_DR_UB_TAG "u85"
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#define U87_TAG "u87"
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#define U88_DIV9_TAG "u88"
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#define U90_DIV14_TAG "u90"
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#define BAUD_PROM_TAG "u39"
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#define NL_PROM_TAG "videobrd:u71"
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#define NL_EPROM_TAG "videobrd:u78"
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#define VIDEO_PROM_TAG "u71"
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#define CHAR_EPROM_TAG "u78"
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#define VIDEO_OUT_TAG "videobrd:video_out"
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#define VBLANK_OUT_TAG "videobrd:vblank"
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#define TVINTERQ_OUT_TAG "videobrd:tvinterq"
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// Number of cycles to burn when fetching the next row of characters into the line buffer:
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// CPU clock is 18MHz / 9
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// Dot clock is 33.264MHz / 2
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// 9 dots per character
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// 80 visible characters per line
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// Total duration of fetch: 1440 33.264MHz clock cycles
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//
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// 2*9*80 1 1440 * XTAL_2MHz
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// -------------- divided by --------- = ---------------- = 86.5 main CPU cycles per line fetch
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// XTAL_33_264MHz XTAL_2MHz XTAL_33_264MHz
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#define LINE_FETCH_CYCLES (87)
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#define VIDEO_CLOCK (XTAL_33_264MHz/2)
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#define VIDEOBRD_CLOCK (XTAL_33_264MHz*30)
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#define SR2_FULL_DUPLEX (0x01)
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#define SR2_UPPER_ONLY (0x08)
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@ -91,9 +70,7 @@ References:
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#define SCREEN_VTOTAL (28*11)
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#define SCREEN_VDISP (24*11)
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#define SCREEN_VSTART (0)
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#define VERT_UB_LINE (24*11+8)
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#define SCREEN_VSTART (3*11)
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class hazl1500_state : public driver_device
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{
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@ -101,53 +78,70 @@ public:
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hazl1500_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag)
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, m_maincpu(*this, CPU_TAG)
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, m_uart(*this, UART_TAG)
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, m_video_board(*this, NETLIST_TAG)
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, m_u71(*this, NL_PROM_TAG)
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, m_u78(*this, NL_EPROM_TAG)
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, m_u9(*this, "videobrd:u9")
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, m_u10(*this, "videobrd:u10")
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, m_u11(*this, "videobrd:u11")
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, m_u12(*this, "videobrd:u12")
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, m_u13(*this, "videobrd:u13")
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, m_u14(*this, "videobrd:u14")
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, m_u15(*this, "videobrd:u15")
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, m_u16(*this, "videobrd:u16")
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, m_u22(*this, "videobrd:u22")
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, m_u23(*this, "videobrd:u23")
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, m_u24(*this, "videobrd:u24")
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, m_u25(*this, "videobrd:u25")
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, m_u26(*this, "videobrd:u26")
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, m_u27(*this, "videobrd:u27")
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, m_u28(*this, "videobrd:u28")
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, m_u29(*this, "videobrd:u29")
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, m_cpu_db0(*this, "videobrd:cpu_db0")
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, m_cpu_db1(*this, "videobrd:cpu_db1")
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, m_cpu_db2(*this, "videobrd:cpu_db2")
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, m_cpu_db3(*this, "videobrd:cpu_db3")
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, m_cpu_db4(*this, "videobrd:cpu_db4")
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, m_cpu_db5(*this, "videobrd:cpu_db5")
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, m_cpu_db6(*this, "videobrd:cpu_db6")
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, m_cpu_db7(*this, "videobrd:cpu_db7")
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, m_cpu_ba4(*this, "videobrd:cpu_ba4")
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, m_cpu_iowq(*this, "videobrd:cpu_iowq")
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, m_video_out(*this, VIDEO_OUT_TAG)
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, m_vblank_out(*this, VBLANK_OUT_TAG)
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, m_tvinterq_out(*this, TVINTERQ_OUT_TAG)
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, m_uart(*this, UART_TAG)
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, m_kbdc(*this, KBDC_TAG)
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, m_baud_dips(*this, BAUDPORT_TAG)
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, m_baud_prom(*this, BAUD_PROM_TAG)
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, m_misc_dips(*this, MISCPORT_TAG)
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, m_kbd_misc_keys(*this, MISCKEYS_TAG)
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, m_char_ram(*this, CHARRAM_TAG)
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, m_char_rom(*this, CHARROM_TAG)
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, m_line_buffer_lsb(*this, TMS3409A_TAG)
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, m_line_buffer_msb(*this, TMS3409B_TAG)
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, m_dotclk(*this, DOTCLK_TAG)
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, m_vid_prom_msb(*this, U69_PROMMSB_TAG)
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, m_vid_prom_lsb(*this, U70_PROMLSB_TAG)
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, m_vid_prom(*this, U71_PROM_TAG)
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, m_u59(*this, U59_TAG)
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, m_u83(*this, U83_TAG)
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, m_char_y(*this, U84_DIV11_TAG)
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, m_char_x(*this, U88_DIV9_TAG)
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, m_vid_div14(*this, U90_DIV14_TAG)
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, m_vid_decode(*this, U72_PROMDEC_TAG)
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, m_u58(*this, U58_TAG)
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, m_u68(*this, U68_TAG)
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, m_u81(*this, U81_TAG)
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, m_u87(*this, U87_TAG)
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, m_u61(*this, U61_TAG)
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, m_screen(*this, SCREEN_TAG)
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, m_hblank_timer(nullptr)
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, m_scanline_timer(nullptr)
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, m_status_reg_3(0)
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, m_iowq_timer(nullptr)
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, m_status_reg_3(0)
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, m_kbd_status_latch(0)
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, m_refresh_address(0)
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, m_vpos(0)
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, m_hblank(false)
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, m_vblank(false)
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, m_delayed_vblank(false)
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{
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, m_screen_buf(nullptr)
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, m_last_beam(0.0)
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, m_last_hpos(0)
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, m_last_vpos(0)
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, m_last_fraction(0.0)
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{
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}
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//m_maincpu->adjust_icount(-14);
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virtual void machine_start() override;
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virtual void machine_reset() override;
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virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
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uint32_t screen_update_hazl1500(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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static const device_timer_id TIMER_IOWQ = 0;
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uint32_t screen_update_hazl1500(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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DECLARE_WRITE_LINE_MEMBER(com5016_fr_w);
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DECLARE_READ8_MEMBER(ram_r);
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DECLARE_WRITE8_MEMBER(ram_w);
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DECLARE_READ8_MEMBER(system_test_r); // noted as "for use with auto test equip" in flowchart on pg. 30, ref[1], jumps to 0x8000 if bit 0 is unset
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DECLARE_READ8_MEMBER(status_reg_2_r);
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DECLARE_WRITE8_MEMBER(status_reg_3_w);
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@ -162,101 +156,96 @@ public:
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DECLARE_WRITE_LINE_MEMBER(ay3600_data_ready_w);
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DECLARE_WRITE8_MEMBER(refresh_address_w);
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virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
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static const device_timer_id TIMER_HBLANK = 0;
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static const device_timer_id TIMER_SCANLINE = 1;
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NETDEV_ANALOG_CALLBACK_MEMBER(video_out_cb);
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NETDEV_ANALOG_CALLBACK_MEMBER(vblank_cb);
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NETDEV_ANALOG_CALLBACK_MEMBER(tvinterq_cb);
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private:
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void check_tv_interrupt();
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void update_tv_unblank();
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void scanline_tick();
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void draw_scanline(uint32_t *pix);
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required_device<cpu_device> m_maincpu;
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required_device<ay31015_device> m_uart;
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required_device<netlist_mame_device_t> m_video_board;
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required_device<netlist_mame_rom_t> m_u71;
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required_device<netlist_mame_rom_t> m_u78;
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required_device<netlist_ram_pointer_t> m_u9;
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required_device<netlist_ram_pointer_t> m_u10;
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required_device<netlist_ram_pointer_t> m_u11;
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required_device<netlist_ram_pointer_t> m_u12;
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required_device<netlist_ram_pointer_t> m_u13;
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required_device<netlist_ram_pointer_t> m_u14;
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required_device<netlist_ram_pointer_t> m_u15;
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required_device<netlist_ram_pointer_t> m_u16;
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required_device<netlist_ram_pointer_t> m_u22;
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required_device<netlist_ram_pointer_t> m_u23;
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required_device<netlist_ram_pointer_t> m_u24;
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required_device<netlist_ram_pointer_t> m_u25;
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required_device<netlist_ram_pointer_t> m_u26;
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required_device<netlist_ram_pointer_t> m_u27;
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required_device<netlist_ram_pointer_t> m_u28;
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required_device<netlist_ram_pointer_t> m_u29;
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required_device<netlist_mame_logic_input_t> m_cpu_db0;
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required_device<netlist_mame_logic_input_t> m_cpu_db1;
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required_device<netlist_mame_logic_input_t> m_cpu_db2;
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required_device<netlist_mame_logic_input_t> m_cpu_db3;
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required_device<netlist_mame_logic_input_t> m_cpu_db4;
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required_device<netlist_mame_logic_input_t> m_cpu_db5;
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required_device<netlist_mame_logic_input_t> m_cpu_db6;
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required_device<netlist_mame_logic_input_t> m_cpu_db7;
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required_device<netlist_mame_logic_input_t> m_cpu_ba4;
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required_device<netlist_mame_logic_input_t> m_cpu_iowq;
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required_device<netlist_mame_analog_output_t> m_video_out;
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required_device<netlist_mame_analog_output_t> m_vblank_out;
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required_device<netlist_mame_analog_output_t> m_tvinterq_out;
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required_device<ay31015_device> m_uart;
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required_device<ay3600_device> m_kbdc;
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required_ioport m_baud_dips;
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required_region_ptr<uint8_t> m_baud_prom;
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required_ioport m_misc_dips;
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required_ioport m_kbd_misc_keys;
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required_shared_ptr<uint8_t> m_char_ram;
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required_region_ptr<uint8_t> m_char_rom;
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required_device<tms3409_device> m_line_buffer_lsb;
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required_device<tms3409_device> m_line_buffer_msb;
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required_device<clock_device> m_dotclk;
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required_device<ttl74161_device> m_vid_prom_msb;
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required_device<ttl74161_device> m_vid_prom_lsb;
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required_device<prom82s129_device> m_vid_prom;
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required_device<ttl7404_device> m_u59;
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required_device<ttl7400_device> m_u83;
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required_device<ttl74161_device> m_char_y;
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required_device<ttl74161_device> m_char_x;
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required_device<ttl74161_device> m_vid_div14;
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required_device<dm9334_device> m_vid_decode;
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required_device<ttl74175_device> m_u58;
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required_device<ttl74175_device> m_u68;
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required_device<ttl74175_device> m_u81;
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required_device<ttl7404_device> m_u87;
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required_device<ttl7404_device> m_u61;
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required_device<screen_device> m_screen;
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std::unique_ptr<uint32_t[]> m_screen_pixbuf;
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emu_timer* m_iowq_timer;
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emu_timer *m_hblank_timer;
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emu_timer *m_scanline_timer;
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uint8_t m_status_reg_3;
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uint8_t m_status_reg_3;
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uint8_t m_kbd_status_latch;
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uint8_t m_refresh_address;
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uint16_t m_vpos;
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bool m_hblank;
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bool m_vblank;
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bool m_delayed_vblank;
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std::unique_ptr<float[]> m_screen_buf;
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double m_last_beam;
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int m_last_hpos;
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int m_last_vpos;
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double m_last_fraction;
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};
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void hazl1500_state::machine_start()
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{
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m_hblank_timer = timer_alloc(TIMER_HBLANK);
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m_hblank_timer->adjust(attotime::never);
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m_screen_buf = std::make_unique<float[]>(SCREEN_HTOTAL * SCREEN_VTOTAL);
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m_scanline_timer = timer_alloc(TIMER_SCANLINE);
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m_scanline_timer->adjust(attotime::never);
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m_iowq_timer = timer_alloc(TIMER_IOWQ);
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m_iowq_timer->adjust(attotime::never);
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m_screen_pixbuf = std::make_unique<uint32_t[]>(SCREEN_HTOTAL * SCREEN_VTOTAL);
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save_item(NAME(m_status_reg_3));
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save_item(NAME(m_status_reg_3));
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save_item(NAME(m_kbd_status_latch));
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save_item(NAME(m_refresh_address));
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save_item(NAME(m_vpos));
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save_item(NAME(m_hblank));
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save_item(NAME(m_vblank));
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save_item(NAME(m_delayed_vblank));
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save_item(NAME(m_last_beam));
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save_item(NAME(m_last_hpos));
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save_item(NAME(m_last_vpos));
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save_item(NAME(m_last_fraction));
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}
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void hazl1500_state::machine_reset()
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{
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m_status_reg_3 = 0;
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m_kbd_status_latch = 0;
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m_refresh_address = 0;
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m_screen->reset_origin(0, 0);
|
||||
m_vpos = m_screen->vpos();
|
||||
m_vblank = (m_vpos >= SCREEN_VDISP);
|
||||
m_delayed_vblank = m_vpos < VERT_UB_LINE;
|
||||
if (!m_vblank)
|
||||
m_kbd_status_latch |= KBD_STATUS_TV_UB;
|
||||
m_hblank = true;
|
||||
m_hblank_timer->adjust(m_screen->time_until_pos(m_vpos, SCREEN_HSTART));
|
||||
m_scanline_timer->adjust(m_screen->time_until_pos(m_vpos + 1, 0));
|
||||
|
||||
m_vid_prom_lsb->p_w(generic_space(), 0, 0);
|
||||
m_vid_prom_msb->p_w(generic_space(), 0, 0);
|
||||
}
|
||||
|
||||
void hazl1500_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
|
||||
{
|
||||
m_cpu_iowq->write(1);
|
||||
m_cpu_ba4->write(1);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( hazl1500_state::com5016_fr_w )
|
||||
{
|
||||
@ -266,10 +255,65 @@ WRITE_LINE_MEMBER( hazl1500_state::com5016_fr_w )
|
||||
|
||||
uint32_t hazl1500_state::screen_update_hazl1500(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
|
||||
{
|
||||
memcpy(&bitmap.pix32(0), &m_screen_pixbuf[0], sizeof(uint32_t) * SCREEN_HTOTAL * SCREEN_VTOTAL);
|
||||
int last_index = m_last_vpos * SCREEN_HTOTAL + m_last_hpos;
|
||||
while (last_index < SCREEN_HTOTAL * SCREEN_VTOTAL)
|
||||
{
|
||||
m_screen_buf[last_index++] = m_last_beam;
|
||||
}
|
||||
m_last_hpos = 0;
|
||||
m_last_vpos = 0;
|
||||
|
||||
uint32_t pixindex = 0;
|
||||
for (int y = 0; y < SCREEN_VTOTAL; y++)
|
||||
{
|
||||
uint32_t *scanline = &bitmap.pix32(y);
|
||||
pixindex = y * SCREEN_HTOTAL;
|
||||
for (int x = 0; x < SCREEN_HTOTAL; x++)
|
||||
//*scanline++ = 0xff000000 | (uint8_t(m_screen_buf[pixindex++] * 0.5) * 0x010101);
|
||||
*scanline++ = 0xff000000 | (uint8_t(m_screen_buf[pixindex++] * 63.0) * 0x010101);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
READ8_MEMBER( hazl1500_state::ram_r )
|
||||
{
|
||||
const uint8_t* chips[2][8] =
|
||||
{
|
||||
{ m_u29->ptr(), m_u28->ptr(), m_u27->ptr(), m_u26->ptr(), m_u25->ptr(), m_u24->ptr(), m_u23->ptr(), m_u22->ptr() },
|
||||
{ m_u16->ptr(), m_u15->ptr(), m_u14->ptr(), m_u13->ptr(), m_u12->ptr(), m_u11->ptr(), m_u10->ptr(), m_u9->ptr() }
|
||||
};
|
||||
|
||||
int bank = ((offset & 0x400) != 0 ? 1 : 0);
|
||||
const int byte_pos = (offset >> 3) & 0x7f;
|
||||
const int bit_pos = offset & 7;
|
||||
|
||||
uint8_t ret = 0;
|
||||
for (std::size_t bit = 0; bit < 8; bit++)
|
||||
ret |= ((chips[bank][bit][byte_pos] >> bit_pos) & 1) << bit;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( hazl1500_state::ram_w )
|
||||
{
|
||||
uint8_t* chips[2][8] =
|
||||
{
|
||||
{ m_u29->ptr(), m_u28->ptr(), m_u27->ptr(), m_u26->ptr(), m_u25->ptr(), m_u24->ptr(), m_u23->ptr(), m_u22->ptr() },
|
||||
{ m_u16->ptr(), m_u15->ptr(), m_u14->ptr(), m_u13->ptr(), m_u12->ptr(), m_u11->ptr(), m_u10->ptr(), m_u9->ptr() }
|
||||
};
|
||||
|
||||
int bank = ((offset & 0x400) != 0 ? 1 : 0);
|
||||
const int byte_pos = (offset >> 3) & 0x7f;
|
||||
const int bit_pos = offset & 7;
|
||||
|
||||
for (std::size_t bit = 0; bit < 8; bit++)
|
||||
{
|
||||
chips[bank][bit][byte_pos] &= ~(1 << bit_pos);
|
||||
chips[bank][bit][byte_pos] |= ((data >> bit) & 1) << bit_pos;
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER( hazl1500_state::system_test_r )
|
||||
{
|
||||
return 0xff;
|
||||
@ -305,7 +349,6 @@ WRITE8_MEMBER( hazl1500_state::uart_w )
|
||||
|
||||
READ8_MEMBER( hazl1500_state::kbd_status_latch_r )
|
||||
{
|
||||
//printf("m_kbd_status_latch r: %02x\n", m_kbd_status_latch);
|
||||
return m_kbd_status_latch;
|
||||
}
|
||||
|
||||
@ -343,124 +386,94 @@ WRITE_LINE_MEMBER(hazl1500_state::ay3600_data_ready_w)
|
||||
m_kbd_status_latch &= ~KBD_STATUS_KBDR;
|
||||
}
|
||||
|
||||
void hazl1500_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
|
||||
NETDEV_ANALOG_CALLBACK_MEMBER(hazl1500_state::vblank_cb)
|
||||
{
|
||||
switch(id)
|
||||
{
|
||||
case TIMER_HBLANK:
|
||||
if (m_hblank)
|
||||
{
|
||||
m_hblank_timer->adjust(m_screen->time_until_pos(m_vpos, SCREEN_HSTART + SCREEN_HDISP));
|
||||
}
|
||||
else
|
||||
{
|
||||
m_hblank_timer->adjust(m_screen->time_until_pos((m_vpos + 1) % SCREEN_VTOTAL, SCREEN_HSTART));
|
||||
}
|
||||
m_hblank ^= 1;
|
||||
break;
|
||||
synchronize();
|
||||
if (int(data) > 1)
|
||||
{
|
||||
m_kbd_status_latch &= ~KBD_STATUS_TV_UB;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_kbd_status_latch |= KBD_STATUS_TV_UB;
|
||||
}
|
||||
}
|
||||
|
||||
case TIMER_SCANLINE:
|
||||
{
|
||||
scanline_tick();
|
||||
break;
|
||||
}
|
||||
NETDEV_ANALOG_CALLBACK_MEMBER(hazl1500_state::tvinterq_cb)
|
||||
{
|
||||
synchronize();
|
||||
if (int(data) > 1)
|
||||
{
|
||||
m_kbd_status_latch &= ~KBD_STATUS_TV_INT;
|
||||
m_maincpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_kbd_status_latch |= KBD_STATUS_TV_INT;
|
||||
m_maincpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE);
|
||||
}
|
||||
}
|
||||
|
||||
NETDEV_ANALOG_CALLBACK_MEMBER(hazl1500_state::video_out_cb)
|
||||
{
|
||||
synchronize();
|
||||
attotime second_fraction(0, time.attoseconds());
|
||||
attotime frame_fraction(0, (second_fraction * 60).attoseconds());
|
||||
attotime pixel_time = frame_fraction * (SCREEN_HTOTAL * SCREEN_VTOTAL);
|
||||
int32_t pixel_index = (frame_fraction * (SCREEN_HTOTAL * SCREEN_VTOTAL)).seconds();
|
||||
double pixel_fraction = ATTOSECONDS_TO_DOUBLE(pixel_time.attoseconds());
|
||||
|
||||
pixel_index -= 16; // take back 16 clock cycles to honor the circuitry god whose ark this is
|
||||
if (pixel_index < 0)
|
||||
{
|
||||
m_last_beam = float(data);
|
||||
m_last_hpos = 0;
|
||||
m_last_vpos = 0;
|
||||
m_last_fraction = 0.0;
|
||||
return;
|
||||
}
|
||||
|
||||
const int hpos = pixel_index % SCREEN_HTOTAL;//m_screen->hpos();
|
||||
const int vpos = pixel_index / SCREEN_HTOTAL;//m_screen->vpos();
|
||||
const int curr_index = vpos * SCREEN_HTOTAL + hpos;
|
||||
|
||||
int last_index = m_last_vpos * SCREEN_HTOTAL + m_last_hpos;
|
||||
if (last_index != curr_index)
|
||||
{
|
||||
m_screen_buf[last_index] *= m_last_fraction;
|
||||
m_screen_buf[last_index] += float(m_last_beam * (1.0 - m_last_fraction));
|
||||
last_index++;
|
||||
while (last_index <= curr_index)
|
||||
m_screen_buf[last_index++] = float(m_last_beam);
|
||||
}
|
||||
|
||||
m_last_beam = float(data);
|
||||
m_last_hpos = hpos;
|
||||
m_last_vpos = vpos;
|
||||
m_last_fraction = pixel_fraction;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(hazl1500_state::refresh_address_w)
|
||||
{
|
||||
m_refresh_address = data;
|
||||
//printf("m_refresh_address %x, vpos %d, screen vpos %d\n", m_refresh_address, m_vpos, m_screen->vpos());
|
||||
}
|
||||
|
||||
void hazl1500_state::check_tv_interrupt()
|
||||
{
|
||||
uint8_t char_row = m_vpos % 11;
|
||||
bool bit_match = char_row == 2 || char_row == 3;
|
||||
bool tv_interrupt = bit_match && !m_delayed_vblank;
|
||||
//printf("interrupt for line %d (%d): %s\n", m_vpos, char_row, tv_interrupt ? "yes" : "no");
|
||||
|
||||
m_kbd_status_latch &= ~KBD_STATUS_TV_INT;
|
||||
m_kbd_status_latch |= tv_interrupt ? KBD_STATUS_TV_INT : 0;
|
||||
|
||||
m_maincpu->set_input_line(INPUT_LINE_IRQ0, tv_interrupt ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
|
||||
void hazl1500_state::update_tv_unblank()
|
||||
{
|
||||
if (!m_vblank)
|
||||
{
|
||||
m_kbd_status_latch |= KBD_STATUS_TV_UB;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_kbd_status_latch &= ~KBD_STATUS_TV_UB;
|
||||
}
|
||||
}
|
||||
|
||||
void hazl1500_state::scanline_tick()
|
||||
{
|
||||
uint16_t old_vpos = m_vpos;
|
||||
m_vpos = (m_vpos + 1) % SCREEN_VTOTAL;
|
||||
m_vblank = (m_vpos >= SCREEN_VDISP);
|
||||
m_delayed_vblank = m_vpos >= VERT_UB_LINE;
|
||||
|
||||
check_tv_interrupt();
|
||||
update_tv_unblank();
|
||||
|
||||
draw_scanline(&m_screen_pixbuf[old_vpos * SCREEN_HTOTAL + SCREEN_HSTART]);
|
||||
|
||||
m_scanline_timer->adjust(m_screen->time_until_pos((m_vpos + 1) % SCREEN_VTOTAL, 0));
|
||||
}
|
||||
|
||||
void hazl1500_state::draw_scanline(uint32_t *pix)
|
||||
{
|
||||
static const uint32_t palette[4] = { 0xff000000, 0xff006000, 0xff000000, 0xff00c000 };
|
||||
|
||||
uint16_t ram_offset = m_refresh_address << 4;
|
||||
uint8_t char_row = m_vpos % 11;
|
||||
uint8_t recycle = (char_row != 10 ? 0xff : 0x00);
|
||||
m_line_buffer_lsb->rc_w(recycle & 0xf);
|
||||
m_line_buffer_msb->rc_w(recycle >> 4);
|
||||
|
||||
if (recycle == 0)
|
||||
m_maincpu->adjust_icount(-LINE_FETCH_CYCLES);
|
||||
|
||||
for (uint16_t x = 0; x < 80; x++)
|
||||
{
|
||||
uint8_t in = 0;
|
||||
if (!m_vblank)
|
||||
in = m_char_ram[ram_offset + x];
|
||||
|
||||
m_line_buffer_lsb->in_w(in & 0xf);
|
||||
m_line_buffer_lsb->cp_w(1);
|
||||
m_line_buffer_lsb->cp_w(0);
|
||||
|
||||
m_line_buffer_msb->in_w(in >> 4);
|
||||
m_line_buffer_msb->cp_w(1);
|
||||
m_line_buffer_msb->cp_w(0);
|
||||
|
||||
const uint8_t chr = (m_line_buffer_msb->out_r() << 4) | m_line_buffer_lsb->out_r();
|
||||
const uint16_t chr_addr = (chr & 0x7f) << 4;
|
||||
const uint8_t gfx = m_char_rom[chr_addr | char_row];
|
||||
const uint8_t bright = (chr & 0x80) >> 6;
|
||||
|
||||
*pix++ = palette[0];
|
||||
*pix++ = palette[BIT(gfx, 6) | bright];
|
||||
*pix++ = palette[BIT(gfx, 5) | bright];
|
||||
*pix++ = palette[BIT(gfx, 4) | bright];
|
||||
*pix++ = palette[BIT(gfx, 3) | bright];
|
||||
*pix++ = palette[BIT(gfx, 2) | bright];
|
||||
*pix++ = palette[BIT(gfx, 1) | bright];
|
||||
*pix++ = palette[BIT(gfx, 0) | bright];
|
||||
*pix++ = palette[0];
|
||||
}
|
||||
synchronize();
|
||||
//printf("refresh: %02x, %d, %d\n", data, m_screen->hpos(), m_screen->vpos());
|
||||
m_iowq_timer->adjust(attotime::from_hz(XTAL_18MHz/9));
|
||||
m_cpu_iowq->write(0);
|
||||
m_cpu_ba4->write(0);
|
||||
m_cpu_db0->write((data >> 0) & 1);
|
||||
m_cpu_db1->write((data >> 1) & 1);
|
||||
m_cpu_db2->write((data >> 2) & 1);
|
||||
m_cpu_db3->write((data >> 3) & 1);
|
||||
m_cpu_db4->write((data >> 4) & 1);
|
||||
m_cpu_db5->write((data >> 5) & 1);
|
||||
m_cpu_db6->write((data >> 6) & 1);
|
||||
m_cpu_db7->write((data >> 7) & 1);
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START(hazl1500_mem, AS_PROGRAM, 8, hazl1500_state)
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
AM_RANGE(0x0000, 0x07ff) AM_ROM
|
||||
AM_RANGE(0x3000, 0x377f) AM_RAM AM_SHARE(CHARRAM_TAG)
|
||||
AM_RANGE(0x3000, 0x377f) AM_READWRITE(ram_r, ram_w)
|
||||
AM_RANGE(0x3780, 0x37ff) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
|
||||
@ -668,7 +681,7 @@ static const gfx_layout hazl1500_charlayout =
|
||||
};
|
||||
|
||||
static GFXDECODE_START( hazl1500 )
|
||||
GFXDECODE_ENTRY( "chargen", 0x0000, hazl1500_charlayout, 0, 1 )
|
||||
GFXDECODE_ENTRY( CHAR_EPROM_TAG, 0x0000, hazl1500_charlayout, 0, 1 )
|
||||
GFXDECODE_END
|
||||
|
||||
static MACHINE_CONFIG_START( hazl1500, hazl1500_state )
|
||||
@ -679,11 +692,14 @@ static MACHINE_CONFIG_START( hazl1500, hazl1500_state )
|
||||
MCFG_QUANTUM_PERFECT_CPU(CPU_TAG)
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_ADD_MONOCHROME(SCREEN_TAG, RASTER, rgb_t::green())
|
||||
MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)
|
||||
MCFG_SCREEN_UPDATE_DRIVER(hazl1500_state, screen_update_hazl1500)
|
||||
MCFG_SCREEN_RAW_PARAMS(XTAL_33_264MHz/2,
|
||||
SCREEN_HTOTAL, SCREEN_HSTART, SCREEN_HSTART + SCREEN_HDISP,
|
||||
SCREEN_VTOTAL, SCREEN_VSTART, SCREEN_VSTART + SCREEN_VDISP);
|
||||
//MCFG_SCREEN_RAW_PARAMS(XTAL_33_264MHz / 2,
|
||||
// SCREEN_HTOTAL, SCREEN_HSTART, SCREEN_HSTART + SCREEN_HDISP,
|
||||
// SCREEN_VTOTAL, SCREEN_VSTART, SCREEN_VSTART + SCREEN_VDISP); // TODO: Figure out exact visibility
|
||||
MCFG_SCREEN_RAW_PARAMS(XTAL_33_264MHz / 2,
|
||||
SCREEN_HTOTAL, 0, SCREEN_HTOTAL,
|
||||
SCREEN_VTOTAL, 0, SCREEN_VTOTAL);
|
||||
|
||||
MCFG_PALETTE_ADD_MONOCHROME("palette")
|
||||
MCFG_GFXDECODE_ADD("gfxdecode", "palette", hazl1500)
|
||||
@ -693,74 +709,46 @@ static MACHINE_CONFIG_START( hazl1500, hazl1500_state )
|
||||
|
||||
MCFG_DEVICE_ADD(UART_TAG, AY51013, 0)
|
||||
|
||||
MCFG_TMS3409_ADD(TMS3409A_TAG)
|
||||
MCFG_TMS3409_ADD(TMS3409B_TAG)
|
||||
MCFG_DEVICE_ADD(NETLIST_TAG, NETLIST_CPU, VIDEOBRD_CLOCK)
|
||||
MCFG_NETLIST_SETUP(hazelvid)
|
||||
|
||||
MCFG_CLOCK_ADD(DOTCLK_TAG, XTAL_33_264MHz/2)
|
||||
MCFG_CLOCK_SIGNAL_HANDLER(DEVWRITELINE(DOTCLK_DISP_TAG, devcb_line_dispatch_device<2>, in_w))
|
||||
MCFG_NETLIST_ROM_REGION(NETLIST_TAG, VIDEO_PROM_TAG, VIDEO_PROM_TAG, VIDEO_PROM_TAG)
|
||||
MCFG_NETLIST_ROM_REGION(NETLIST_TAG, CHAR_EPROM_TAG, CHAR_EPROM_TAG, CHAR_EPROM_TAG)
|
||||
|
||||
MCFG_LINE_DISPATCH_ADD(DOTCLK_DISP_TAG, 2)
|
||||
MCFG_LINE_DISPATCH_FWD_CB(0, 2, DEVWRITELINE(U81_TAG, ttl74175_device, clock_w))
|
||||
MCFG_LINE_DISPATCH_FWD_CB(1, 2, DEVWRITELINE(U88_DIV9_TAG, ttl74161_device, clock_w))
|
||||
// First 1K
|
||||
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u22", "u22")
|
||||
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u23", "u23")
|
||||
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u24", "u24")
|
||||
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u25", "u25")
|
||||
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u26", "u26")
|
||||
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u27", "u27")
|
||||
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u28", "u28")
|
||||
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u29", "u29")
|
||||
|
||||
MCFG_74161_ADD(U70_PROMLSB_TAG)
|
||||
MCFG_7416x_QA_CB(DEVWRITELINE(U71_PROM_TAG, prom82s129_device, a0_w))
|
||||
MCFG_7416x_QB_CB(DEVWRITELINE(U71_PROM_TAG, prom82s129_device, a1_w))
|
||||
MCFG_7416x_QC_CB(DEVWRITELINE(U71_PROM_TAG, prom82s129_device, a2_w))
|
||||
MCFG_7416x_QD_CB(DEVWRITELINE(U71_PROM_TAG, prom82s129_device, a3_w))
|
||||
MCFG_7416x_TC_CB(DEVWRITELINE(U70_TC_LINE_TAG, devcb_line_dispatch_device<2>, in_w))
|
||||
// Second 1K
|
||||
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u9", "u9")
|
||||
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u10", "u10")
|
||||
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u11", "u11")
|
||||
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u12", "u12")
|
||||
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u13", "u13")
|
||||
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u14", "u14")
|
||||
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u15", "u15")
|
||||
MCFG_NETLIST_RAM_POINTER(NETLIST_TAG, "u16", "u16")
|
||||
|
||||
MCFG_LINE_DISPATCH_ADD(U70_TC_LINE_TAG, 2)
|
||||
MCFG_LINE_DISPATCH_FWD_CB(0, 2, DEVWRITELINE(U69_PROMMSB_TAG, ttl74161_device, cet_w))
|
||||
MCFG_LINE_DISPATCH_FWD_CB(1, 2, DEVWRITELINE(U69_PROMMSB_TAG, ttl74161_device, cep_w))
|
||||
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_iowq", "cpu_iowq.IN", 0)
|
||||
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_ba4", "cpu_ba4.IN", 0)
|
||||
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db0", "cpu_db0.IN", 0)
|
||||
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db1", "cpu_db1.IN", 0)
|
||||
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db2", "cpu_db2.IN", 0)
|
||||
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db3", "cpu_db3.IN", 0)
|
||||
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db4", "cpu_db4.IN", 0)
|
||||
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db5", "cpu_db5.IN", 0)
|
||||
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db6", "cpu_db6.IN", 0)
|
||||
MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cpu_db7", "cpu_db7.IN", 0)
|
||||
|
||||
MCFG_74161_ADD(U69_PROMMSB_TAG)
|
||||
MCFG_7416x_QA_CB(DEVWRITELINE(U71_PROM_TAG, prom82s129_device, a4_w))
|
||||
MCFG_7416x_QB_CB(DEVWRITELINE(U71_PROM_TAG, prom82s129_device, a5_w))
|
||||
MCFG_7416x_QC_CB(DEVWRITELINE(U71_PROM_TAG, prom82s129_device, a6_w))
|
||||
|
||||
//MCFG_LINE_DISPATCH_ADD(CHAR_LINE_CNT_CLK_TAG, 3)
|
||||
//MCFG_LINE_DISPATCH_FWD_CB(0, 3, DEVWRITELINE(U85_VERT_DR_UB_TAG, ttl7473_device, clk1_w))
|
||||
//MCFG_LINE_DISPATCH_FWD_CB(1, 3, DEVWRITELINE(U85_VERT_DR_UB_TAG, ttl7473_device, clk2_w))
|
||||
//MCFG_LINE_DISPATCH_FWD_CB(2, 3, DEVWRITELINE(U84_DIV11_TAG, ttl74161_device, clock_w))
|
||||
|
||||
MCFG_7400_ADD(U83_TAG)
|
||||
//MCFG_7400_Y1_CB(DEVWRITELINE(CHAR_LINE_CNT_CLK_TAG, devcb_line_dispatch_device<4>, in_w))
|
||||
|
||||
MCFG_74161_ADD(U84_DIV11_TAG)
|
||||
MCFG_74161_ADD(U90_DIV14_TAG)
|
||||
|
||||
MCFG_74161_ADD(U88_DIV9_TAG)
|
||||
MCFG_7416x_QC_CB(DEVWRITELINE(U81_TAG, ttl74175_device, d4_w))
|
||||
MCFG_7416x_TC_CB(DEVWRITELINE(U81_TAG, ttl74175_device, d1_w))
|
||||
|
||||
MCFG_LINE_DISPATCH_ADD(CHAR_CTR_CLK_TAG, 2)
|
||||
MCFG_LINE_DISPATCH_FWD_CB(0, 2, DEVWRITELINE(U70_PROMLSB_TAG, ttl74161_device, clock_w))
|
||||
MCFG_LINE_DISPATCH_FWD_CB(1, 2, DEVWRITELINE(U69_PROMMSB_TAG, ttl74161_device, clock_w))
|
||||
|
||||
MCFG_74175_ADD(U58_TAG)
|
||||
MCFG_74175_ADD(U68_TAG)
|
||||
MCFG_74175_ADD(U81_TAG)
|
||||
MCFG_74175_Q1_CB(DEVWRITELINE(U81_TAG, ttl74175_device, d2_w))
|
||||
MCFG_74175_NOT_Q2_CB(DEVWRITELINE(CHAR_CTR_CLK_TAG, devcb_line_dispatch_device<2>, in_w))
|
||||
|
||||
MCFG_DM9334_ADD(U72_PROMDEC_TAG)
|
||||
MCFG_DM9334_Q4_CB(DEVWRITELINE(U83_TAG, ttl7400_device, b1_w))
|
||||
|
||||
MCFG_82S129_ADD(U71_PROM_TAG)
|
||||
MCFG_82S129_O1_CB(DEVWRITELINE(U72_PROMDEC_TAG, dm9334_device, a0_w))
|
||||
MCFG_82S129_O2_CB(DEVWRITELINE(U72_PROMDEC_TAG, dm9334_device, a1_w))
|
||||
MCFG_82S129_O3_CB(DEVWRITELINE(U72_PROMDEC_TAG, dm9334_device, a2_w))
|
||||
MCFG_82S129_O4_CB(DEVWRITELINE(U72_PROMDEC_TAG, dm9334_device, d_w))
|
||||
|
||||
MCFG_7404_ADD(U61_TAG)
|
||||
MCFG_7404_ADD(U87_TAG)
|
||||
MCFG_7404_ADD(U59_TAG)
|
||||
MCFG_7404_Y5_CB(DEVWRITELINE(VID_PROM_ADDR_RESET_TAG, devcb_line_dispatch_device<2>, in_w))
|
||||
|
||||
MCFG_LINE_DISPATCH_ADD(VID_PROM_ADDR_RESET_TAG, 2)
|
||||
MCFG_LINE_DISPATCH_FWD_CB(0, 2, DEVWRITELINE(U70_PROMLSB_TAG, ttl74161_device, pe_w))
|
||||
MCFG_LINE_DISPATCH_FWD_CB(1, 2, DEVWRITELINE(U69_PROMMSB_TAG, ttl74161_device, pe_w))
|
||||
MCFG_NETLIST_ANALOG_OUTPUT(NETLIST_TAG, "video_out", "video_out", hazl1500_state, video_out_cb, "")
|
||||
MCFG_NETLIST_ANALOG_OUTPUT(NETLIST_TAG, "vblank", "vblank", hazl1500_state, vblank_cb, "")
|
||||
MCFG_NETLIST_ANALOG_OUTPUT(NETLIST_TAG, "tvinterq", "tvinterq", hazl1500_state, tvinterq_cb, "")
|
||||
|
||||
/* keyboard controller */
|
||||
MCFG_DEVICE_ADD(KBDC_TAG, AY3600, 0)
|
||||
@ -780,16 +768,18 @@ MACHINE_CONFIG_END
|
||||
|
||||
|
||||
ROM_START( hazl1500 )
|
||||
ROM_REGION( 0x10000, NETLIST_TAG, ROMREGION_ERASE00 )
|
||||
|
||||
ROM_REGION( 0x10000, CPU_TAG, ROMREGION_ERASEFF )
|
||||
ROM_LOAD( "h15s-00I-10-3.bin", 0x0000, 0x0800, CRC(a2015f72) SHA1(357cde517c3dcf693de580881add058c7b26dfaa))
|
||||
|
||||
ROM_REGION( 0x800, CHARROM_TAG, ROMREGION_ERASEFF )
|
||||
ROM_REGION( 0x800, CHAR_EPROM_TAG, ROMREGION_ERASEFF )
|
||||
ROM_LOAD( "u83_chr.bin", 0x0000, 0x0800, CRC(e0c6b734) SHA1(7c42947235c66c41059fd4384e09f4f3a17c9857))
|
||||
|
||||
ROM_REGION( 0x100, BAUD_PROM_TAG, ROMREGION_ERASEFF )
|
||||
ROM_LOAD( "u43_702129_82s129.bin", 0x0000, 0x0100, CRC(b35aea2b) SHA1(4702620cdef72b32a397580c22b75df36e24ac74))
|
||||
|
||||
ROM_REGION( 0x100, U71_PROM_TAG, ROMREGION_ERASEFF )
|
||||
ROM_REGION( 0x100, VIDEO_PROM_TAG, ROMREGION_ERASEFF )
|
||||
ROM_LOAD( "u90_702128_82s129.bin", 0x0000, 0x0100, CRC(277bc424) SHA1(528a0de3b54d159bc14411961961706bf9ec41bf))
|
||||
ROM_END
|
||||
|
||||
|
||||
244
src/mame/machine/nl_hazelvid.cpp
Normal file
244
src/mame/machine/nl_hazelvid.cpp
Normal file
@ -0,0 +1,244 @@
|
||||
// license:BSD-3-Clause
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Ryan Holtz
|
||||
|
||||
/***************************************************************************
|
||||
|
||||
Netlist (hazelvid) included from hazeltin.cpp
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#include "netlist/devices/net_lib.h"
|
||||
|
||||
#define FAST_CLOCK (1)
|
||||
|
||||
#ifndef __PLIB_PREPROCESSOR__
|
||||
#endif
|
||||
|
||||
NETLIST_START(hazelvid)
|
||||
|
||||
SOLVER(Solver, 48000)
|
||||
PARAM(Solver.PARALLEL, 0) // Don't do parallel solvers
|
||||
PARAM(Solver.ACCURACY, 1e-4) // works and is sufficient
|
||||
PARAM(NETLIST.USE_DEACTIVATE, 1)
|
||||
|
||||
ANALOG_INPUT(V5, 5)
|
||||
|
||||
TTL_INPUT(high, 1)
|
||||
TTL_INPUT(low, 0)
|
||||
|
||||
MAINCLOCK(video_clk, 16632000.0)
|
||||
|
||||
/* Character line counter, divide-by-9 */
|
||||
TTL_74161(u88, high, high, high, low, high, u87_6.Q, video_clk, high, high)
|
||||
|
||||
TTL_7404_INVERT(u87_6, u88.RCO)
|
||||
|
||||
TTL_74175(u81, video_clk, u88.RCO, u81.Q1, low, u88.QC, high)
|
||||
|
||||
TTL_7404_INVERT(u87_5, u81.Q1)
|
||||
ALIAS(ndot, u87_5.Q)
|
||||
TTL_7404_INVERT(u59_4, u81.Q1Q)
|
||||
ALIAS(dot, u59_4.Q)
|
||||
|
||||
/* Character bucket counter */
|
||||
|
||||
/* least significant 4 bits */
|
||||
TTL_74161(u70, low, low, low, low, high, u59_5.Q, u81.Q2Q, high, high)
|
||||
|
||||
/* most significant 4 bits */
|
||||
TTL_74161(u69, low, low, low, low, high, u59_5.Q, u81.Q2Q, u70.RCO, u70.RCO)
|
||||
/* Horizontal/Vertical timing signals */
|
||||
|
||||
/* signal lookup PROM */
|
||||
TTL_82S126(u71, high, high, u70.QA, u70.QB, u70.QC, u70.QD, u69.QA, u69.QB, u69.QC, low)
|
||||
|
||||
/* signal decoding */
|
||||
TTL_DM9334(u72, high, u81.Q1Q, u71.O4, u71.O1, u71.O2, u71.O3)
|
||||
ALIAS(hms, u72.Q1)
|
||||
ALIAS(hmsd, u72.Q2)
|
||||
ALIAS(hblank, u72.Q3)
|
||||
ALIAS(vstrobe, u72.Q4)
|
||||
ALIAS(hdriveq, u72.Q5)
|
||||
ALIAS(vidbus, u72.Q6)
|
||||
TTL_7404_INVERT(u59_5, u72.Q7)
|
||||
|
||||
TTL_7400_NAND(u83_1, high, vstrobe)
|
||||
ALIAS(char_line_clk, u83_1.Q)
|
||||
|
||||
/* Character line counter */
|
||||
TTL_74161(u84, low, low, low, low, high, u83_3.Q, char_line_clk, high, high)
|
||||
ALIAS(lc20, u84.QA)
|
||||
ALIAS(lc21, u84.QB)
|
||||
ALIAS(lc22, u84.QC)
|
||||
ALIAS(lc23, u84.QD)
|
||||
TTL_7400_NAND(u83_3, u84.QB, u84.QD)
|
||||
TTL_7404_INVERT(u92_5, u90.QD)
|
||||
|
||||
TTL_7410_NAND(u89_3, u90.QD, u90.QC, u90.QA)
|
||||
|
||||
/* Character row counter */
|
||||
TTL_74161(u90, low, low, low, low, high, u89_3.Q, u92_3.Q, high, high)
|
||||
TTL_7404_INVERT(u92_3, u84.QD)
|
||||
TTL_7404_INVERT(u92_1, u90.QB)
|
||||
|
||||
TTL_7474(u95_2, u92_5.Q, u95_2.QQ, high, high)
|
||||
|
||||
TTL_7411_AND(u91_3, u84.QA, u84.QD, u90.QB)
|
||||
TTL_7411_AND(u91_1, u92_1.Q, u90.QA, u84.QC)
|
||||
|
||||
TTL_7404_INVERT(u92_2, u90.QC)
|
||||
TTL_7411_AND(u91_2, u95_2.QQ, u92_2.Q, u92_5.Q)
|
||||
TTL_7404_INVERT(u92_6, u91_2.Q)
|
||||
|
||||
/* Vertical blanking and drive */
|
||||
TTL_7473(u85_vdrive, char_line_clk, u91_1.Q, u91_3.Q, u85_vblankq.QQ)
|
||||
TTL_7473(u85_vblankq, char_line_clk, u92_6.Q, u91_2.Q, high)
|
||||
|
||||
/* Outgoing signals */
|
||||
TTL_7404_INVERT(u73_4, hdriveq)
|
||||
ALIAS(hdrive, u73_4.Q)
|
||||
|
||||
TTL_7404_INVERT(u61_6, hmsd)
|
||||
TTL_7402_NOR(u60_1, u61_6.Q, u81.Q4)
|
||||
ALIAS(lbc, u60_1.Q)
|
||||
|
||||
TTL_7404_INVERT(u74_1, u84.QB)
|
||||
TTL_7410_NAND(u89_2, vidbus, vidbus, u82_2.Q)
|
||||
ALIAS(ncntbenq, u89_2.Q)
|
||||
|
||||
TTL_7410_NAND(u89_1, u81.Q2, hmsd, u82_2.Q)
|
||||
TTL_7400_NAND(u83_4, u89_1.Q, high)
|
||||
ALIAS(cntclk, u83_4.Q)
|
||||
|
||||
TTL_7402_NOR(u60_2, hblank, u85_vblankq.QQ)
|
||||
ALIAS(clr_vid_sr, u60_2.Q)
|
||||
|
||||
TTL_7404_INVERT(u92_4, u84.QB)
|
||||
TTL_74260_NOR(u82_2, u85_vblankq.QQ, u92_3.Q, u84.QC, u92_4.Q, u84.QA)
|
||||
TTL_7400_NAND(u83_2, vstrobe, u82_2.Q)
|
||||
ALIAS(sync_bus_disable_q, u83_2.Q)
|
||||
|
||||
ALIAS(vdrive, u85_vdrive.Q)
|
||||
TTL_7404_INVERT(u73_5, vdrive)
|
||||
ALIAS(vdriveq, u73_5.Q)
|
||||
|
||||
TTL_7474(u95_1, u84.QD, u85_vblankq.QQ, high, high)
|
||||
ALIAS(vblank, u95_1.Q)
|
||||
|
||||
TTL_74260_NOR(u82_1, u85_vblankq.QQ, u92_4.Q, u84.QD, u84.QC, low)
|
||||
TTL_7404_INVERT(u61_3, u82_1.Q)
|
||||
ALIAS(tvinterq, u61_3.Q)
|
||||
|
||||
TTL_INPUT(cpu_iowq, 1)
|
||||
TTL_INPUT(cpu_ba4, 1)
|
||||
TTL_7432_OR(u36_1, cpu_iowq, cpu_ba4)
|
||||
|
||||
/* Character address counter */
|
||||
TTL_74193(u7, low, low, low, low, low, u36_1.Q, cntclk, high)
|
||||
TTL_74193(u5, cpu_db0, cpu_db1, cpu_db2, cpu_db3, low, u36_1.Q, u7.CARRYQ, u7.BORROWQ)
|
||||
TTL_74193(u3, cpu_db4, cpu_db5, cpu_db6, cpu_db7, low, u36_1.Q, u5.CARRYQ, u5.BORROWQ)
|
||||
|
||||
TTL_74365(u6, low, ncntbenq, u7.QA, u7.QB, u7.QC, u7.QD, u5.QA, u5.QB)
|
||||
TTL_74365(u4, low, ncntbenq, u5.QC, u5.QD, u3.QA, u3.QB, u3.QC, low)
|
||||
ALIAS(ba0, u6.Y1)
|
||||
ALIAS(ba1, u6.Y2)
|
||||
ALIAS(ba2, u6.Y3)
|
||||
ALIAS(ba3, u6.Y4)
|
||||
ALIAS(ba4, u6.Y5)
|
||||
ALIAS(ba5, u6.Y6)
|
||||
ALIAS(ba6, u4.Y1)
|
||||
ALIAS(ba7, u4.Y2)
|
||||
ALIAS(ba8, u4.Y3)
|
||||
ALIAS(ba9, u4.Y4)
|
||||
ALIAS(ba10, u4.Y5)
|
||||
|
||||
/* Video RAM */
|
||||
TTL_INPUT(memwq, 1)
|
||||
TTL_INPUT(mrq, 1)
|
||||
TTL_INPUT(ba13, 0)
|
||||
|
||||
TTL_7432_OR(u36_2, memwq, memwq)
|
||||
TTL_7400_NAND(u37_2, u36_2.Q, mrq)
|
||||
TTL_7400_NAND(u37_3, u37_2.Q, ba13)
|
||||
TTL_7400_NAND(u37_4, u37_3.Q, ncntbenq)
|
||||
TTL_7404_INVERT(u17_2, u4.Y5)
|
||||
TTL_7400_NAND(u30_2, u17_2.Q, u37_4.Q)
|
||||
TTL_7400_NAND(u37_1, u4.Y5, u37_4.Q)
|
||||
TTL_INPUT(rwq, 1)
|
||||
|
||||
/* Lower 1K */
|
||||
RAM_2102A(u22, u30_2.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u22.DO)
|
||||
RAM_2102A(u23, u30_2.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u23.DO)
|
||||
RAM_2102A(u24, u30_2.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u24.DO)
|
||||
RAM_2102A(u25, u30_2.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u25.DO)
|
||||
RAM_2102A(u26, u30_2.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u26.DO)
|
||||
RAM_2102A(u27, u30_2.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u27.DO)
|
||||
RAM_2102A(u28, u30_2.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u28.DO)
|
||||
RAM_2102A(u29, u30_2.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u29.DO)
|
||||
|
||||
/* Upper 1K */
|
||||
RAM_2102A(u9, u37_1.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u9.DO)
|
||||
RAM_2102A(u10, u37_1.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u10.DO)
|
||||
RAM_2102A(u11, u37_1.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u11.DO)
|
||||
RAM_2102A(u12, u37_1.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u12.DO)
|
||||
RAM_2102A(u13, u37_1.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u13.DO)
|
||||
RAM_2102A(u14, u37_1.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u14.DO)
|
||||
RAM_2102A(u15, u37_1.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u15.DO)
|
||||
RAM_2102A(u16, u37_1.Q, ba0, ba1, ba2, ba3, ba4, ba5, ba6, ba7, ba8, ba9, rwq, u16.DO)
|
||||
|
||||
TTL_INPUT(cpu_db0, 0)
|
||||
TTL_INPUT(cpu_db1, 0)
|
||||
TTL_INPUT(cpu_db2, 0)
|
||||
TTL_INPUT(cpu_db3, 0)
|
||||
TTL_INPUT(cpu_db4, 0)
|
||||
TTL_INPUT(cpu_db5, 0)
|
||||
TTL_INPUT(cpu_db6, 0)
|
||||
TTL_INPUT(cpu_db7, 0)
|
||||
|
||||
TTL_TRISTATE(db0, u30_2.Q, u29.DO, u37_1.Q, u16.DO)
|
||||
TTL_TRISTATE(db1, u30_2.Q, u28.DO, u37_1.Q, u15.DO)
|
||||
TTL_TRISTATE(db2, u30_2.Q, u27.DO, u37_1.Q, u14.DO)
|
||||
TTL_TRISTATE(db3, u30_2.Q, u26.DO, u37_1.Q, u13.DO)
|
||||
TTL_TRISTATE(db4, u30_2.Q, u25.DO, u37_1.Q, u12.DO)
|
||||
TTL_TRISTATE(db5, u30_2.Q, u24.DO, u37_1.Q, u11.DO)
|
||||
TTL_TRISTATE(db6, u30_2.Q, u23.DO, u37_1.Q, u10.DO)
|
||||
TTL_TRISTATE(db7, u30_2.Q, u22.DO, u37_1.Q, u9.DO)
|
||||
|
||||
/* Character generation */
|
||||
TTL_74175(u68, dot, db0.Q, db1.Q, db2.Q, db3.Q, high) // least significant 4 bits of each character
|
||||
TTL_AM2847(u67, lbc, u68.Q1, u68.Q2, u68.Q3, u68.Q4, sync_bus_disable_q, sync_bus_disable_q, sync_bus_disable_q, sync_bus_disable_q)
|
||||
|
||||
TTL_74175(u58, dot, db4.Q, db5.Q, db6.Q, db7.Q, high) // most signifcant 4 bits of each character
|
||||
TTL_AM2847(u57, lbc, u58.Q1, u58.Q2, u58.Q3, u58.Q4, sync_bus_disable_q, sync_bus_disable_q, sync_bus_disable_q, sync_bus_disable_q)
|
||||
|
||||
TTL_74174(u66, ndot, u67.OUTA, u67.OUTB, u67.OUTC, u67.OUTD, u57.OUTA, u57.OUTB, high)
|
||||
TTL_74175(u56, ndot, u57.OUTC, clr_vid_sr, u79_1.Q, u57.OUTD, high)
|
||||
TTL_7400_NAND(u79_1, u56.Q4, clr_vid_sr)
|
||||
ALIAS(fgbit_q, u56.Q3Q)
|
||||
|
||||
EPROM_2716(u78, low, low, lc20, lc21, lc22, lc23, u66.Q1, u66.Q2, u66.Q3, u66.Q4, u66.Q5, u66.Q6, u56.Q1)
|
||||
|
||||
TTL_74166(u77, video_clk, low, ndot, low, u78.D0, u78.D1, u78.D2, u78.D3, u78.D4, u78.D5, u78.D6, low, clr_vid_sr)
|
||||
ALIAS(raw_dot, u77.QH)
|
||||
|
||||
TTL_7400_NAND(u79_4, fgbit_q, fgbit_q)
|
||||
ALIAS(highlight, u79_4.Q)
|
||||
|
||||
ALIAS(video_out, raw_dot)
|
||||
|
||||
/* Highlight and contrast - not yet hooked up */
|
||||
RES(R40, 160)
|
||||
RES(R41, 270)
|
||||
POT(R21_POT, 500)
|
||||
|
||||
NET_C(R40.1, V5)
|
||||
NET_C(R40.2, R21_POT.1)
|
||||
NET_C(raw_dot, R21_POT.1)
|
||||
NET_C(highlight, R41.1)
|
||||
NET_C(R41.2, R21_POT.1)
|
||||
|
||||
NET_C(R21_POT.3, GND)
|
||||
NET_C(R21_POT.2, GND)
|
||||
|
||||
NETLIST_END()
|
||||
4
src/mame/machine/nl_hazelvid.h
Normal file
4
src/mame/machine/nl_hazelvid.h
Normal file
@ -0,0 +1,4 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Ryan Holtz
|
||||
|
||||
NETLIST_EXTERNAL(hazelvid)
|
||||
Loading…
Reference in New Issue
Block a user