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SH-2 CPU core timing changes [notaz]

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- JMP should be 2 cycles, according to the manual.
- OR #imm,R0 should be 1 cycle and OR #imm,@(R0,GBR) should be 3 to
match the manual and other ops.
This commit is contained in:
Scott Stone 2013-07-16 17:51:23 +00:00
parent 963e34d3f7
commit 1432dfec7f
1 changed files with 2 additions and 1 deletions
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3
src/emu/cpu/sh2/sh2.c
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@ -865,6 +865,7 @@ INLINE void JMP(sh2_state *sh2, UINT32 m)
{ {
sh2->delay = sh2->pc; sh2->delay = sh2->pc;
sh2->pc = sh2->ea = sh2->r[m]; sh2->pc = sh2->ea = sh2->r[m];
sh2->icount--;
} }
/* JSR @Rm */ /* JSR @Rm */
@ -1428,7 +1429,6 @@ INLINE void OR(sh2_state *sh2, UINT32 m, UINT32 n)
INLINE void ORI(sh2_state *sh2, UINT32 i) INLINE void ORI(sh2_state *sh2, UINT32 i)
{ {
sh2->r[0] |= i; sh2->r[0] |= i;
sh2->icount -= 2;
} }
/* OR.B #imm,@(R0,GBR) */ /* OR.B #imm,@(R0,GBR) */
@ -1440,6 +1440,7 @@ INLINE void ORM(sh2_state *sh2, UINT32 i)
temp = RB( sh2, sh2->ea ); temp = RB( sh2, sh2->ea );
temp |= i; temp |= i;
WB( sh2, sh2->ea, temp ); WB( sh2, sh2->ea, temp );
sh2->icount -= 2;
} }
/* ROTCL Rn */ /* ROTCL Rn */