converted lot of TRUE/FALSE to real boolean and updated types (nw)

src/devices/bus/a7800/a78_slot.cpp

@@ -351,8 +351,8 @@ image_init_result a78_cart_slot_device::call_load()
 		if (software_entry() != nullptr)
 		{
 			const char *pcb_name;
-			bool has_ram = get_software_region("ram") ? TRUE : FALSE;
+			bool has_ram = get_software_region("ram") ? true : false;
-			bool has_nvram = get_software_region("nvram") ? TRUE : FALSE;
+			bool has_nvram = get_software_region("nvram") ? true : false;
 			len = get_software_region_length("rom");
 
 			m_cart->rom_alloc(len, tag());
@@ -389,7 +389,7 @@ image_init_result a78_cart_slot_device::call_load()
 			}
 
 			// let's try to auto-fix some common errors in the header
-			mapper = validate_header((head[53] << 8) | head[54], TRUE);
+			mapper = validate_header((head[53] << 8) | head[54], true);
 
 			switch (mapper & 0x2e)
 			{
@@ -530,7 +530,7 @@ std::string a78_cart_slot_device::get_default_card_software()
 		m_file->read(&head[0], 128);
 
 		// let's try to auto-fix some common errors in the header
-		mapper = validate_header((head[53] << 8) | head[54], FALSE);
+		mapper = validate_header((head[53] << 8) | head[54], false);
 
 		switch (mapper & 0x2e)
 		{

src/devices/bus/centronics/printer.cpp

@@ -60,13 +60,13 @@ void centronics_printer_device::device_timer(emu_timer &timer, device_timer_id i
 	case TIMER_ACK:
 		output_ack(param);
 
-		if (param == FALSE)
+		if (param == false)
 		{
 			/* data is now ready, output it */
 			m_printer->output(m_data);
 
 			/* ready to receive more data, return BUSY to low */
-			timer_set(attotime::from_usec(7), TIMER_BUSY, FALSE);
+			timer_set(attotime::from_usec(7), TIMER_BUSY, false);
 		}
 		break;
 
@@ -74,15 +74,15 @@ void centronics_printer_device::device_timer(emu_timer &timer, device_timer_id i
 		m_busy = param;
 		output_busy(m_busy);
 
-		if (param == TRUE)
+		if (param == true)
 		{
 			/* timer to turn ACK low to receive data */
-			timer_set(attotime::from_usec(10), TIMER_ACK, FALSE);
+			timer_set(attotime::from_usec(10), TIMER_ACK, false);
 		}
 		else
 		{
 			/* timer to return ACK to high state */
-			timer_set(attotime::from_usec(5), TIMER_ACK, TRUE);
+			timer_set(attotime::from_usec(5), TIMER_ACK, true);
 		}
 	}
 }
@@ -97,7 +97,7 @@ void centronics_printer_device::device_start()
 
 void centronics_printer_device::device_reset()
 {
-	m_busy = FALSE;
+	m_busy = false;
 	output_busy(m_busy);
 	output_fault(1);
 	output_ack(1);
@@ -112,10 +112,10 @@ void centronics_printer_device::device_reset()
 WRITE_LINE_MEMBER( centronics_printer_device::input_strobe )
 {
 	/* look for a high -> low transition */
-	if (m_strobe == TRUE && state == FALSE && m_busy == FALSE)
+	if (m_strobe == true && state == false && m_busy == false)
 	{
 		/* STROBE has gone low, data is ready */
-		timer_set(attotime::zero, TIMER_BUSY, TRUE);
+		timer_set(attotime::zero, TIMER_BUSY, true);
 	}
 
 	m_strobe = state;
@@ -130,6 +130,6 @@ WRITE_LINE_MEMBER( centronics_printer_device::input_strobe )
 WRITE_LINE_MEMBER(centronics_printer_device::input_init)
 {
 	/* reset printer if line is low */
-	if (state == FALSE)
+	if (state == false)
 		device_reset();
 }

src/devices/bus/gba/gba_slot.cpp

@@ -319,7 +319,7 @@ int gba_cart_slot_device::get_cart_type(uint8_t *ROM, uint32_t len)
 	if (gba_chip_has_conflict(chip))
 	{
 		char game_code[5] = { 0 };
-		bool resolved = FALSE;
+		bool resolved = false;
 
 		if (len >= 0xac + 4)
 			memcpy(game_code, ROM + 0xac, 4);
@@ -335,7 +335,7 @@ int gba_cart_slot_device::get_cart_type(uint8_t *ROM, uint32_t len)
 			if (!strcmp(game_code, item->game_code))
 			{
 				chip |= item->chip;
-				resolved = TRUE;
+				resolved = true;
 				break;
 			}
 		}

src/devices/bus/generic/slot.cpp

@@ -91,7 +91,7 @@ generic_slot_device::generic_slot_device(const machine_config &mconfig, const ch
 						m_interface(nullptr),
 						m_default_card("rom"),
 						m_extensions("bin"),
-						m_must_be_loaded(FALSE),
+						m_must_be_loaded(false),
 						m_width(GENERIC_ROM8_WIDTH),
 						m_endianness(ENDIANNESS_LITTLE), m_cart(nullptr)
 {

src/devices/bus/generic/slot.h

@@ -64,7 +64,7 @@ enum
 
 
 #define MCFG_GENERIC_MANDATORY       \
-	static_cast<generic_slot_device *>(device)->set_must_be_loaded(TRUE);
+	static_cast<generic_slot_device *>(device)->set_must_be_loaded(true);
 
 #define MCFG_GENERIC_WIDTH(_width)       \
 	static_cast<generic_slot_device *>(device)->set_width(_width);

src/devices/bus/isa/3c503.cpp

@@ -46,7 +46,7 @@ void el2_3c503_device::device_start() {
 			chan++;
 			idcfr >>= 1;
 		}
-		m_isa->set_dma_channel(chan, this, FALSE);
+		m_isa->set_dma_channel(chan, this, false);
 	}
 }
 

src/devices/bus/isa/fdc.cpp

@@ -83,7 +83,7 @@ void isa8_fdc_device::device_start()
 {
 	set_isa_device();
 	m_isa->install_device(0x03f0, 0x03f7, *fdc, &pc_fdc_interface::map);
-	m_isa->set_dma_channel(2, this, TRUE);
+	m_isa->set_dma_channel(2, this, true);
 }
 
 void isa8_fdc_device::device_reset()

src/devices/bus/isa/gus.cpp

@@ -1504,7 +1504,7 @@ WRITE_LINE_MEMBER(isa16_gus_device::sb_irq)
 
 WRITE_LINE_MEMBER(isa16_gus_device::drq1_w)
 {
-	m_isa->set_dma_channel(m_gf1->dma_channel1(), this, TRUE);
+	m_isa->set_dma_channel(m_gf1->dma_channel1(), this, true);
 	switch(m_gf1->dma_channel1())
 	{
 	case 1:
@@ -1529,7 +1529,7 @@ WRITE_LINE_MEMBER(isa16_gus_device::drq1_w)
 
 WRITE_LINE_MEMBER(isa16_gus_device::drq2_w)
 {
-	m_isa->set_dma_channel(m_gf1->dma_channel2(), this, TRUE);
+	m_isa->set_dma_channel(m_gf1->dma_channel2(), this, true);
 	switch(m_gf1->dma_channel2())
 	{
 	case 1:

src/devices/bus/isa/hdc.cpp

@@ -1000,7 +1000,7 @@ void isa8_hdc_device::device_start()
 {
 	set_isa_device();
 	m_isa->install_device(0x0320, 0x0323, read8_delegate( FUNC(isa8_hdc_device::pc_hdc_r), this ), write8_delegate( FUNC(isa8_hdc_device::pc_hdc_w), this ) );
-	m_isa->set_dma_channel(3, this, FALSE);
+	m_isa->set_dma_channel(3, this, false);
 }
 
 //-------------------------------------------------

src/devices/bus/isa/mcd.cpp

@@ -49,7 +49,7 @@ void mcd_isa_device::device_start()
 {
 	cdrom_image_device::device_start();
 	set_isa_device();
-	m_isa->set_dma_channel(5, this, FALSE);
+	m_isa->set_dma_channel(5, this, false);
 	m_isa->install_device(0x0310, 0x0311, *this, &mcd_isa_device::map, 16);
 }
 

src/devices/bus/isa/omti8621.cpp

@@ -331,7 +331,7 @@ void omti8621_device::device_reset()
 			m_isa->install_device(0x03f0, 0x03f7, *m_fdc, &pc_fdc_interface::map);
 		}
 
-		m_isa->set_dma_channel(2, this, TRUE);
+		m_isa->set_dma_channel(2, this, true);
 
 		m_installed = true;
 	}

src/devices/bus/isa/sb16.cpp

@@ -710,8 +710,8 @@ void sb16_lle_device::device_start()
 	m_isa->install_device(0x0388, 0x0389, read8_delegate(FUNC(ymf262_device::read), ymf262), write8_delegate(FUNC(ymf262_device::write), ymf262));
 	m_isa->install_device(0x0220, 0x0223, read8_delegate(FUNC(ymf262_device::read), ymf262), write8_delegate(FUNC(ymf262_device::write), ymf262));
 	m_isa->install_device(0x0228, 0x0229, read8_delegate(FUNC(ymf262_device::read), ymf262), write8_delegate(FUNC(ymf262_device::write), ymf262));
-	m_isa->set_dma_channel(1, this, FALSE);
+	m_isa->set_dma_channel(1, this, false);
-	m_isa->set_dma_channel(5, this, FALSE);
+	m_isa->set_dma_channel(5, this, false);
 	m_timer = timer_alloc();
 }
 

src/devices/bus/isa/sblaster.cpp

@@ -1311,7 +1311,7 @@ void isa8_sblaster1_0_device::device_start()
 	// 1.0 always has the SAA1099s for CMS back-compatibility
 	m_isa->install_device(0x0220, 0x0221, read8_delegate( FUNC(isa8_sblaster1_0_device::saa1099_16_r), this ), write8_delegate( FUNC(isa8_sblaster1_0_device::saa1099_1_16_w), this ) );
 	m_isa->install_device(0x0222, 0x0223, read8_delegate( FUNC(isa8_sblaster1_0_device::saa1099_16_r), this ), write8_delegate( FUNC(isa8_sblaster1_0_device::saa1099_2_16_w), this ) );
-	m_isa->set_dma_channel(1, this, FALSE);
+	m_isa->set_dma_channel(1, this, false);
 	m_dsp.version = 0x0105;
 	sb8_device::device_start();
 }
@@ -1320,7 +1320,7 @@ void isa8_sblaster1_5_device::device_start()
 {
 	set_isa_device();
 	/* 1.5 makes CM/S support optional (empty sockets, but they work if the user populates them!) */
-	m_isa->set_dma_channel(1, this, FALSE);
+	m_isa->set_dma_channel(1, this, false);
 	m_dsp.version = 0x0200;
 	sb8_device::device_start();
 }
@@ -1363,8 +1363,8 @@ void sb16_device::device_start()
 void isa16_sblaster16_device::device_start()
 {
 	set_isa_device();
-	m_isa->set_dma_channel(1, this, FALSE);
+	m_isa->set_dma_channel(1, this, false);
-	m_isa->set_dma_channel(5, this, FALSE);
+	m_isa->set_dma_channel(5, this, false);
 	m_dsp.version = 0x0405; // diagnose.exe rejects anything lower than 0x0402
 	sb16_device::device_start();
 }

src/devices/bus/isa/stereo_fx.cpp

@@ -212,7 +212,7 @@ void stereo_fx_device::device_start()
 	m_isa->install_device(0x0228, 0x0229, read8_delegate(FUNC(ym3812_device::read), ym3812), write8_delegate(FUNC(ym3812_device::write), ym3812));
 	m_timer = timer_alloc();
 	m_timer->adjust(attotime::from_hz(2000000), 0, attotime::from_hz(2000000));
-	m_isa->set_dma_channel(1, this, FALSE);
+	m_isa->set_dma_channel(1, this, false);
 }
 
 

src/devices/bus/isa/wdxt_gen.cpp

@@ -208,7 +208,7 @@ void wdxt_gen_device::device_start()
 	set_isa_device();
 	m_isa->install_rom(this, 0xc8000, 0xc9fff, "hdc", "hdc");
 	m_isa->install_device(0x0320, 0x0323, READ8_DEVICE_DELEGATE(m_host, wd11c00_17_device, io_r), WRITE8_DEVICE_DELEGATE(m_host, wd11c00_17_device, io_w));
-	m_isa->set_dma_channel(3, this, FALSE);
+	m_isa->set_dma_channel(3, this, false);
 }
 
 

src/devices/bus/megadrive/md_slot.cpp

@@ -1001,7 +1001,7 @@ void base_md_cart_slot_device::file_logging(uint8_t *ROM8, uint32_t rom_len, uin
 	char serial[14], io[16], modem[12], memo[40], country[16];
 	uint32_t rom_start, rom_end, ram_start, ram_end, sram_start = 0, sram_end = 0;
 	uint16_t checksum, csum = 0;
-	bool valid_sram = FALSE, is_pico = FALSE;
+	bool valid_sram = false, is_pico = false;
 	std::string ctrl(""), reg("");
 
 	// LOG FILE DETAILS
@@ -1024,7 +1024,7 @@ void base_md_cart_slot_device::file_logging(uint8_t *ROM8, uint32_t rom_len, uin
 	for (int i = 0; i < 16; i++)
 		console[i] = ROM8[0x100 + (i ^ 1)];
 	if (!strncmp("SEGA PICO", console, 9))
-		is_pico = TRUE;
+		is_pico = true;
 	for (int i = 0; i < 16; i++)
 		copyright[i] = ROM8[0x110 + (i ^ 1)];
 	for (int i = 0; i < 48; i++)
@@ -1051,7 +1051,7 @@ void base_md_cart_slot_device::file_logging(uint8_t *ROM8, uint32_t rom_len, uin
 	ram_end = (ROM8[0x1ad] << 24 | ROM8[0x1ac] << 16 | ROM8[0x1af] << 8 | ROM8[0x1ae]);;
 	if (ROM8[0x1b1] == 'R' && ROM8[0x1b0] == 'A')
 	{
-		valid_sram = TRUE;
+		valid_sram = true;
 		sram_start = (ROM8[0x1b5] << 24 | ROM8[0x1b4] << 16 | ROM8[0x1b7] << 8 | ROM8[0x1b6]);
 		sram_end = (ROM8[0x1b9] << 24 | ROM8[0x1b8] << 16 | ROM8[0x1bb] << 8 | ROM8[0x1ba]);
 	}

src/devices/bus/megadrive/md_slot.h

@@ -260,7 +260,7 @@ extern const device_type COPERA_CART_SLOT;
 
 
 #define MCFG_MD_CARTRIDGE_NOT_MANDATORY                                     \
-	static_cast<md_cart_slot_device *>(device)->set_must_be_loaded(FALSE);
+	static_cast<md_cart_slot_device *>(device)->set_must_be_loaded(false);
 
 
 #endif

src/devices/bus/nes/jy.cpp

@@ -163,7 +163,7 @@ READ8_MEMBER(nes_jy_typea_device::chr_r)
 
 void nes_jy_typea_device::irq_clock(int mode, int blanked)
 {
-	bool clock = FALSE, fire = FALSE;
+	bool clock = false, fire = false;
 
 	if (m_irq_mode != mode)
 		return;
@@ -177,7 +177,7 @@ void nes_jy_typea_device::irq_clock(int mode, int blanked)
 	{
 		if ((m_irq_prescale & m_irq_prescale_mask) == 0)
 		{
-			clock = TRUE;
+			clock = true;
 			m_irq_prescale = (m_irq_prescale_mask == 7) ? ((m_irq_prescale & 0xf8) | 7) : 0xff;
 		}
 		else
@@ -188,7 +188,7 @@ void nes_jy_typea_device::irq_clock(int mode, int blanked)
 	{
 		if ((m_irq_prescale & m_irq_prescale_mask) == m_irq_prescale_mask)
 		{
-			clock = TRUE;
+			clock = true;
 			m_irq_prescale = (m_irq_prescale_mask == 7) ? (m_irq_prescale & 0xf8) : 0;
 		}
 		else
@@ -202,7 +202,7 @@ void nes_jy_typea_device::irq_clock(int mode, int blanked)
 		{
 			if (m_irq_count == 0)
 			{
-				fire = TRUE;
+				fire = true;
 				m_irq_count = 0xff;
 			}
 			else
@@ -213,7 +213,7 @@ void nes_jy_typea_device::irq_clock(int mode, int blanked)
 		{
 			if (m_irq_count == 0xff)
 			{
-				fire = TRUE;
+				fire = true;
 				m_irq_count = 0;
 			}
 			else

src/devices/bus/nes/nes_ines.hxx

@@ -343,11 +343,11 @@ void nes_cart_slot_device::call_load_ines()
 	uint32_t prg_size, vrom_size;
 	uint8_t header[0x10];
 	uint8_t mapper, submapper = 0, local_options;
-	bool ines20 = FALSE, prg16k;
+	bool ines20 = false, prg16k;
 	std::string mapinfo;
 	int pcb_id = 0, mapint1 = 0, mapint2 = 0, mapint3 = 0, mapint4 = 0;
 	int crc_hack = 0;
-	bool bus_conflict = FALSE;
+	bool bus_conflict = false;
 
 	// read out the header
 	fseek(0, SEEK_SET);
@@ -371,7 +371,7 @@ void nes_cart_slot_device::call_load_ines()
 			break;
 
 		case 0x8:   // it's iNES 2.0 format
-			ines20 = TRUE;
+			ines20 = true;
 		case 0x0:
 		default:
 			mapper |= header[7] & 0xf0;
@@ -423,11 +423,11 @@ void nes_cart_slot_device::call_load_ines()
 			logerror("Unimplemented iNES2.0 submapper: SEROM/SHROM/SH1ROM.\n");
 		// 002, 003, 007: UxROM, CNROM, AxROM
 		else if (mapper == 2 && submapper == 2)
-			bus_conflict = TRUE;
+			bus_conflict = true;
 		else if (mapper == 3 && submapper == 2)
-			bus_conflict = TRUE;
+			bus_conflict = true;
 		else if (mapper == 7 && submapper == 2)
-			bus_conflict = TRUE;
+			bus_conflict = true;
 		// 021, 023, 025: VRC4 / VRC2
 		else if (mapper == 21 || mapper == 23 || mapper == 25)
 		{
@@ -464,7 +464,7 @@ void nes_cart_slot_device::call_load_ines()
 		// iNES Mapper 071
 		else if (mapper == 71 && submapper == 1)
 		{
-			m_cart->set_pcb_ctrl_mirror(TRUE);    // Mapper 71 is used for 2 diff boards
+			m_cart->set_pcb_ctrl_mirror(true);    // Mapper 71 is used for 2 diff boards
 		}
 		// iNES Mapper 078
 		else if (mapper == 78)
@@ -498,8 +498,8 @@ void nes_cart_slot_device::call_load_ines()
 	m_cart->set_mirroring(BIT(local_options, 0) ? PPU_MIRROR_VERT : PPU_MIRROR_HORZ);
 	if (BIT(local_options, 1))
 		battery_size = NES_BATTERY_SIZE; // with original iNES format we can only support 8K WRAM battery
-	m_cart->set_trainer(BIT(local_options, 2) ? TRUE : FALSE);
+	m_cart->set_trainer(BIT(local_options, 2) ? true : false);
-	m_cart->set_four_screen_vram(BIT(local_options, 3) ? TRUE : FALSE);
+	m_cart->set_four_screen_vram(BIT(local_options, 3) ? true : false);
 
 	if (ines20)
 	{
@@ -537,7 +537,7 @@ void nes_cart_slot_device::call_load_ines()
 
 		case NOCASH_NOCHR:
 			// this mapper uses mirroring flags differently
-			m_cart->set_four_screen_vram(FALSE);
+			m_cart->set_four_screen_vram(false);
 			switch (local_options & 0x09)
 			{
 				case 0x00:
@@ -607,31 +607,31 @@ void nes_cart_slot_device::call_load_ines()
 			if (crc_hack && !submapper)
 				m_cart->set_mirroring(PPU_MIRROR_HIGH); // Major League has hardwired mirroring
 			else if (!submapper)
-				m_cart->set_pcb_ctrl_mirror(TRUE);
+				m_cart->set_pcb_ctrl_mirror(true);
 			break;
 
 		case DIS_74X161X161X32:
 			if (mapper == 70)
 				m_cart->set_mirroring(PPU_MIRROR_VERT); // only hardwired mirroring makes different mappers 70 & 152
 			else
-				m_cart->set_pcb_ctrl_mirror(TRUE);
+				m_cart->set_pcb_ctrl_mirror(true);
 			break;
 
 		case SUNSOFT_2:
 			if (mapper == 93)
 				m_cart->set_mirroring(PPU_MIRROR_VERT); // only hardwired mirroring makes different mappers 89 & 93
 			else
-				m_cart->set_pcb_ctrl_mirror(TRUE);
+				m_cart->set_pcb_ctrl_mirror(true);
 			break;
 
 		case HES_BOARD:
 			if (crc_hack)
-				m_cart->set_pcb_ctrl_mirror(TRUE);    // Mapper 113 is used for 2 diff boards
+				m_cart->set_pcb_ctrl_mirror(true);    // Mapper 113 is used for 2 diff boards
 			break;
 
 		case CAMERICA_BF9093:
 			if (crc_hack && !submapper)
-				m_cart->set_pcb_ctrl_mirror(TRUE);    // Mapper 71 is used for 2 diff boards
+				m_cart->set_pcb_ctrl_mirror(true);    // Mapper 71 is used for 2 diff boards
 			break;
 
 		case STD_BXROM:
@@ -670,7 +670,7 @@ void nes_cart_slot_device::call_load_ines()
 
 		case TAITO_X1_005:
 			if (mapper == 207)
-				m_cart->set_x1_005_alt(TRUE);
+				m_cart->set_x1_005_alt(true);
 			mapper_sram_size = m_cart->get_mapper_sram_size();
 			break;
 
@@ -814,7 +814,7 @@ void nes_cart_slot_device::call_load_ines()
 const char * nes_cart_slot_device::get_default_card_ines(uint8_t *ROM, uint32_t len)
 {
 	uint8_t mapper, submapper = 0;
-	bool ines20 = FALSE;
+	bool ines20 = false;
 	std::string mapinfo;
 	int pcb_id = 0, mapint1 = 0, mapint2 = 0, mapint3 = 0, mapint4 = 0;
 	int crc_hack = 0;
@@ -829,7 +829,7 @@ const char * nes_cart_slot_device::get_default_card_ines(uint8_t *ROM, uint32_t
 			break;
 
 		case 0x8:   // it's iNES 2.0 format
-			ines20 = TRUE;
+			ines20 = true;
 		case 0x0:
 		default:
 			mapper |= ROM[7] & 0xf0;

src/devices/bus/nes/nes_pcb.hxx

@@ -477,7 +477,7 @@ void nes_cart_slot_device::call_load_pcb()
 		{
 			// A few boards uses 4-screen mirroring: Gauntlet (DDROM or TRR1ROM or Tengen 800004),
 			// Rad Racer II (TVROM), and Napoleon Senki (IREM LROG017 with 74*161/161/21/138)
-			m_cart->set_four_screen_vram(TRUE);
+			m_cart->set_four_screen_vram(true);
 			m_cart->set_mirroring(PPU_MIRROR_4SCREEN);
 		}
 		if (!strcmp(mirroring, "pcb_controlled"))
@@ -487,7 +487,7 @@ void nes_cart_slot_device::call_load_pcb()
 			// See e.g. HES 6-in-1 vs other HES games, Irem Major League vs other G-101 games,
 			// Sunsoft-2 Shanghai vs Mito Koumon, Camerica BF9093 games vs BF9097 games, etc.
 			// Boards where all games control mirroring do not make real use of this.
-			m_cart->set_pcb_ctrl_mirror(TRUE);
+			m_cart->set_pcb_ctrl_mirror(true);
 		}
 	}
 
@@ -513,7 +513,7 @@ void nes_cart_slot_device::call_load_pcb()
 	if (m_pcb_id == TAITO_X1_005 && get_feature("x1-pin17") != nullptr && get_feature("x1-pin31") != nullptr)
 	{
 		if (!strcmp(get_feature("x1-pin17"), "CIRAM A10") && !strcmp(get_feature("x1-pin31"), "NC"))
-			m_cart->set_x1_005_alt(TRUE);
+			m_cart->set_x1_005_alt(true);
 	}
 
 	if (m_pcb_id == KONAMI_VRC2)
@@ -554,7 +554,7 @@ void nes_cart_slot_device::call_load_pcb()
 	// pirate variants of boards with bus conflict are often not suffering from it
 	// and actually games glitch if bus conflict is emulated...
 	if (get_feature("bus_conflict") && !strcmp(get_feature("bus_conflict"), "no"))
-		m_cart->set_bus_conflict(FALSE);
+		m_cart->set_bus_conflict(false);
 
 
 	// SETUP step 4: logging what we have found

src/devices/bus/nes/nes_slot.cpp

@@ -119,11 +119,11 @@ device_nes_cart_interface::device_nes_cart_interface(const machine_config &mconf
 						m_vrc_ls_prg_b(0),
 						m_vrc_ls_chr(0),
 						m_mirroring(PPU_MIRROR_NONE),
-						m_pcb_ctrl_mirror(FALSE),
+						m_pcb_ctrl_mirror(false),
-						m_four_screen_vram(FALSE),
+						m_four_screen_vram(false),
-						m_has_trainer(FALSE),
+						m_has_trainer(false),
-						m_x1_005_alt_mirroring(FALSE),
+						m_x1_005_alt_mirroring(false),
-						m_bus_conflict(TRUE),
+						m_bus_conflict(true),
 						m_open_bus(0),
 						m_prg_chunks(0),
 						m_prg_mask(0xffff),
@@ -583,7 +583,7 @@ uint8_t device_nes_cart_interface::hi_access_rom(uint32_t offset)
 uint8_t device_nes_cart_interface::account_bus_conflict(uint32_t offset, uint8_t data)
 {
 	// pirate variants of boards subject to bus conflict are often not subject to it
-	// so we allow to set m_bus_conflict to FALSE at loading time when necessary
+	// so we allow to set m_bus_conflict to false at loading time when necessary
 	if (m_bus_conflict)
 		return data & hi_access_rom(offset);
 	else

src/devices/bus/nes/nes_slot.h

@@ -421,7 +421,7 @@ extern const device_type NES_CART_SLOT;
 	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false)
 
 #define MCFG_NES_CARTRIDGE_NOT_MANDATORY                                     \
-	static_cast<nes_cart_slot_device *>(device)->set_must_be_loaded(FALSE);
+	static_cast<nes_cart_slot_device *>(device)->set_must_be_loaded(false);
 
 
 // Hacky configuration to add a slot with fixed disksys interface

src/devices/bus/nes/nes_unif.hxx

@@ -210,7 +210,7 @@ void nes_cart_slot_device::call_load_unif()
 	uint8_t buffer[4], mirror = 0;
 	char magic2[4];
 	char unif_mapr[32]; // here we should store MAPR chunks
-	bool mapr_chunk_found = FALSE, small_prg = FALSE;
+	bool mapr_chunk_found = false, small_prg = false;
 
 	// allocate space to temporarily store PRG & CHR banks
 	std::vector<uint8_t> temp_prg(256 * 0x4000);
@@ -237,7 +237,7 @@ void nes_cart_slot_device::call_load_unif()
 		{
 			if ((magic2[0] == 'M') && (magic2[1] == 'A') && (magic2[2] == 'P') && (magic2[3] == 'R'))
 			{
-				mapr_chunk_found = TRUE;
+				mapr_chunk_found = true;
 				logerror("[MAPR] chunk found: ");
 				fread(&buffer, 4);
 				chunk_length = buffer[0] | (buffer[1] << 8) | (buffer[2] << 16) | (buffer[3] << 24);
@@ -384,7 +384,7 @@ void nes_cart_slot_device::call_load_unif()
 					logerror("It consists of %d 16K-blocks.\n", chunk_length / 0x4000);
 				else
 				{
-					small_prg = TRUE;
+					small_prg = true;
 					logerror("This chunk is smaller than 16K: the emulation might have issues. Please report this file to the MESS forums.\n");
 				}
 
@@ -438,7 +438,7 @@ void nes_cart_slot_device::call_load_unif()
 	prgram_size = prgram * 0x2000;
 	vram_size = vram_chunks * 0x2000;
 
-	m_cart->set_four_screen_vram(FALSE);
+	m_cart->set_four_screen_vram(false);
 	switch (mirror)
 	{
 		case 0: // Horizontal Mirroring (Hard Wired)
@@ -454,7 +454,7 @@ void nes_cart_slot_device::call_load_unif()
 			m_cart->set_mirroring(PPU_MIRROR_HIGH);
 			break;
 		case 4: // Four Screens of VRAM (Hard Wired)
-			m_cart->set_four_screen_vram(TRUE);
+			m_cart->set_four_screen_vram(true);
 			m_cart->set_mirroring(PPU_MIRROR_4SCREEN);
 			break;
 		case 5: // Mirroring Controlled By Mapper Hardware

src/devices/bus/sega8/sega8_slot.cpp

@@ -54,8 +54,8 @@ device_sega8_cart_interface::device_sega8_cart_interface(const machine_config &m
 		m_rom(nullptr),
 		m_rom_size(0),
 		m_rom_page_count(0),
-		has_battery(FALSE),
+		has_battery(false),
-		m_late_battery_enable(FALSE),
+		m_late_battery_enable(false),
 		m_lphaser_xoffs(-1),
 		m_sms_mode(0)
 {
@@ -112,7 +112,7 @@ sega8_cart_slot_device::sega8_cart_slot_device(const machine_config &mconfig, de
 						device_image_interface(mconfig, *this),
 						device_slot_interface(mconfig, *this),
 						m_type(SEGA8_BASE_ROM),
-						m_must_be_loaded(FALSE),
+						m_must_be_loaded(false),
 						m_interface("sms_cart"),
 						m_extensions("bin"), m_cart(nullptr)
 {
@@ -124,15 +124,15 @@ sega8_cart_slot_device::sega8_cart_slot_device(const machine_config &mconfig, co
 						device_image_interface(mconfig, *this),
 						device_slot_interface(mconfig, *this),
 						m_type(SEGA8_BASE_ROM),
-						m_must_be_loaded(FALSE),
+						m_must_be_loaded(false),
-						m_is_card(FALSE),
+						m_is_card(false),
 						m_interface("sms_cart"),
 						m_extensions("bin"), m_cart(nullptr)
 {
 }
 
 sega8_card_slot_device::sega8_card_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
-						sega8_cart_slot_device(mconfig, SEGA8_CARD_SLOT, "Sega Master System / Game Gear / SG1000 Card Slot", tag, owner, clock, TRUE, "sega8_card_slot", __FILE__)
+						sega8_cart_slot_device(mconfig, SEGA8_CARD_SLOT, "Sega Master System / Game Gear / SG1000 Card Slot", tag, owner, clock, true, "sega8_card_slot", __FILE__)
 {
 }
 
@@ -275,45 +275,45 @@ void sega8_cart_slot_device::setup_ram()
 		if (m_type == SEGA8_CASTLE)
 		{
 			m_cart->ram_alloc(0x2000);
-			m_cart->set_has_battery(FALSE);
+			m_cart->set_has_battery(false);
 		}
 		else if (m_type == SEGA8_OTHELLO)
 		{
 			m_cart->ram_alloc(0x800);
-			m_cart->set_has_battery(FALSE);
+			m_cart->set_has_battery(false);
 		}
 		else if (m_type == SEGA8_BASIC_L3)
 		{
 			m_cart->ram_alloc(0x8000);
-			m_cart->set_has_battery(FALSE);
+			m_cart->set_has_battery(false);
 		}
 		else if (m_type == SEGA8_MUSIC_EDITOR)
 		{
 			m_cart->ram_alloc(0x2800);
-			m_cart->set_has_battery(FALSE);
+			m_cart->set_has_battery(false);
 		}
 		else if (m_type == SEGA8_DAHJEE_TYPEA)
 		{
 			m_cart->ram_alloc(0x2400);
-			m_cart->set_has_battery(FALSE);
+			m_cart->set_has_battery(false);
 		}
 		else if (m_type == SEGA8_DAHJEE_TYPEB)
 		{
 			m_cart->ram_alloc(0x2000);
-			m_cart->set_has_battery(FALSE);
+			m_cart->set_has_battery(false);
 		}
 		else if (m_type == SEGA8_CODEMASTERS)
 		{
 			// Codemasters cart can have 64KB of RAM (Ernie Els Golf? or 8KB?) and no battery
 			m_cart->ram_alloc(0x10000);
-			m_cart->set_has_battery(FALSE);
+			m_cart->set_has_battery(false);
 		}
 		else
 		{
 			// for generic carts loaded from fullpath we have no way to know exactly if there was RAM,
 			// how much RAM was in the cart and if there was a battery so we always alloc 32KB and
 			// we save its content only if the game enable the RAM
-			m_cart->set_late_battery(TRUE);
+			m_cart->set_late_battery(true);
 			m_cart->ram_alloc(0x08000);
 		}
 	}
@@ -321,13 +321,13 @@ void sega8_cart_slot_device::setup_ram()
 	{
 		// from softlist we rely on the xml to only allocate the correct amount of RAM and to save it only if a battery was present
 		const char *battery = get_feature("battery");
-		m_cart->set_late_battery(FALSE);
+		m_cart->set_late_battery(false);
 
 		if (get_software_region_length("ram"))
 			m_cart->ram_alloc(get_software_region_length("ram"));
 
 		if (battery && !strcmp(battery, "yes"))
-			m_cart->set_has_battery(TRUE);
+			m_cart->set_has_battery(true);
 	}
 }
 
@@ -388,7 +388,7 @@ image_init_result sega8_cart_slot_device::call_load()
 				m_cart->set_sms_mode(1);
 		}
 
-		// when loading from fullpath m_late_battery_enable can be TRUE and in that case
+		// when loading from fullpath m_late_battery_enable can be true and in that case
 		// we attempt to load a battery because the game might have it!
 		if (m_cart->get_ram_size() && (m_cart->get_has_battery() || m_cart->get_late_battery()))
 			battery_load(m_cart->get_ram_base(), m_cart->get_ram_size(), 0x00);

src/devices/bus/sega8/sega8_slot.h

@@ -179,42 +179,42 @@ public:
 #define MCFG_SG1000_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
 	MCFG_DEVICE_ADD(_tag, SEGA8_CART_SLOT, 0) \
 	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
-	static_cast<sega8_cart_slot_device *>(device)->set_mandatory(TRUE); \
+	static_cast<sega8_cart_slot_device *>(device)->set_mandatory(true); \
 	static_cast<sega8_cart_slot_device *>(device)->set_intf("sg1000_cart"); \
 	static_cast<sega8_cart_slot_device *>(device)->set_ext("bin,sg");
 
 #define MCFG_OMV_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
 	MCFG_DEVICE_ADD(_tag, SEGA8_CART_SLOT, 0) \
 	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
-	static_cast<sega8_cart_slot_device *>(device)->set_mandatory(FALSE); \
+	static_cast<sega8_cart_slot_device *>(device)->set_mandatory(false); \
 	static_cast<sega8_cart_slot_device *>(device)->set_intf("sg1000_cart"); \
 	static_cast<sega8_cart_slot_device *>(device)->set_ext("bin,sg");
 
 #define MCFG_SC3000_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
 	MCFG_DEVICE_ADD(_tag, SEGA8_CART_SLOT, 0) \
 	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
-	static_cast<sega8_cart_slot_device *>(device)->set_mandatory(TRUE); \
+	static_cast<sega8_cart_slot_device *>(device)->set_mandatory(true); \
 	static_cast<sega8_cart_slot_device *>(device)->set_intf("sg1000_cart"); \
 	static_cast<sega8_cart_slot_device *>(device)->set_ext("bin,sg,sc");
 
 #define MCFG_SG1000MK3_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
 	MCFG_DEVICE_ADD(_tag, SEGA8_CART_SLOT, 0) \
 	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
-	static_cast<sega8_cart_slot_device *>(device)->set_mandatory(FALSE); \
+	static_cast<sega8_cart_slot_device *>(device)->set_mandatory(false); \
 	static_cast<sega8_cart_slot_device *>(device)->set_intf("sms_cart,sg1000_cart"); \
 	static_cast<sega8_cart_slot_device *>(device)->set_ext("bin,sms,sg");
 
 #define MCFG_SMS_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
 	MCFG_DEVICE_ADD(_tag, SEGA8_CART_SLOT, 0) \
 	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
-	static_cast<sega8_cart_slot_device *>(device)->set_mandatory(FALSE); \
+	static_cast<sega8_cart_slot_device *>(device)->set_mandatory(false); \
 	static_cast<sega8_cart_slot_device *>(device)->set_intf("sms_cart"); \
 	static_cast<sega8_cart_slot_device *>(device)->set_ext("bin,sms");
 
 #define MCFG_GG_CARTRIDGE_ADD(_tag,_slot_intf,_def_slot) \
 	MCFG_DEVICE_ADD(_tag, SEGA8_CART_SLOT, 0) \
 	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
-	static_cast<sega8_cart_slot_device *>(device)->set_mandatory(TRUE); \
+	static_cast<sega8_cart_slot_device *>(device)->set_mandatory(true); \
 	static_cast<sega8_cart_slot_device *>(device)->set_intf("gamegear_cart"); \
 	static_cast<sega8_cart_slot_device *>(device)->set_ext("bin,gg");
 
@@ -223,7 +223,7 @@ public:
 #define MCFG_SMS_CARD_ADD(_tag,_slot_intf,_def_slot) \
 	MCFG_DEVICE_ADD(_tag, SEGA8_CARD_SLOT, 0) \
 	MCFG_DEVICE_SLOT_INTERFACE(_slot_intf, _def_slot, false) \
-	static_cast<sega8_card_slot_device *>(device)->set_mandatory(FALSE); \
+	static_cast<sega8_card_slot_device *>(device)->set_mandatory(false); \
 	static_cast<sega8_card_slot_device *>(device)->set_intf("sms_card"); \
 	static_cast<sega8_card_slot_device *>(device)->set_ext("bin");
 #define MCFG_SG1000_CARD_ADD(_tag,_slot_intf,_def_slot) \

src/devices/bus/sms_ctrl/lphaser.cpp

@@ -298,6 +298,6 @@ void sms_light_phaser_device::device_timer(emu_timer &timer, device_timer_id id,
 		sensor_check();
 		break;
 	default:
-		assert_always(FALSE, "Unknown id in sms_light_phaser_device::device_timer");
+		assert_always(false, "Unknown id in sms_light_phaser_device::device_timer");
 	}
 }

src/devices/bus/sms_ctrl/sports.cpp

@@ -71,7 +71,7 @@ void sms_sports_pad_device::device_timer(emu_timer &timer, device_timer_id id, i
 
 		break;
 	default:
-		assert_always(FALSE, "Unknown id in sms_sports_pad_device::device_timer");
+		assert_always(false, "Unknown id in sms_sports_pad_device::device_timer");
 	}
 }
 

src/devices/bus/snes/spc7110.cpp

@@ -972,14 +972,14 @@ void sns_rom_spc7110_device::spc7110_update_time(uint8_t offset)
 	machine().current_datetime(curtime);
 	int64_t diff = curtime.time - m_rtc_basetime.time - offset;
 //  printf("diff %llx\n", diff);
-	bool update = TRUE;
+	bool update = true;
 
 	// TEST: can we go beyond 24hrs of rounding?!? I doubt it will ever go beyond 3600, but I could be wrong...
 	assert(diff < 86400);
 
 	/* do not update if CR0 or CR2 timer disable flags are set */
 	if ((m_rtc_ram[13] & 0x01) || (m_rtc_ram[15] & 0x03))
-		update = FALSE;
+		update = false;
 
 	if (update && diff > 0)
 	{
@@ -1021,11 +1021,11 @@ void sns_rom_spc7110_device::spc7110_update_time(uint8_t offset)
 			// check for feb 29th
 			if (days == 28)
 			{
-				bool leap = FALSE;
+				bool leap = false;
 				if ((year % 4) == 0)
 				{
 					if(year % 100 || !(year % 400))
-						leap = TRUE;
+						leap = true;
 				}
 				if (leap)
 					days++;

src/devices/bus/snes/upd.cpp

@@ -240,7 +240,7 @@ WRITE8_MEMBER( sns_rom21_necdsp_device::chip_write )
 READ8_MEMBER( sns_rom_setadsp_device::chip_read )
 {
 	if (offset >= 0x600000 && offset < 0x680000 && (offset & 0xffff) < 0x4000)
-		m_upd96050->snesdsp_read((offset & 0x01) ? FALSE : TRUE);
+		m_upd96050->snesdsp_read((offset & 0x01) ? false : true);
 
 	if (offset >= 0x680000 && offset < 0x700000 && (offset & 0xffff) < 0x8000)
 	{
@@ -260,7 +260,7 @@ WRITE8_MEMBER( sns_rom_setadsp_device::chip_write )
 {
 	if (offset >= 0x600000 && offset < 0x680000 && (offset & 0xffff) < 0x4000)
 	{
-		m_upd96050->snesdsp_write((offset & 0x01) ? FALSE : TRUE, data);
+		m_upd96050->snesdsp_write((offset & 0x01) ? false : true, data);
 		return;
 	}
 

src/devices/bus/ti99_peb/bwg.h

@@ -94,7 +94,7 @@ private:
 	// Indicates whether the clock is mapped into the address space.
 	bool m_rtc_enabled;
 
-	// Signal motor_on. When TRUE, makes all drives turning.
+	// Signal motor_on. When true, makes all drives turning.
 	int m_MOTOR_ON;
 
 	// Needed for triggering the motor monoflop

src/devices/bus/ti99_peb/hfdc.h

@@ -170,7 +170,7 @@ private:
 	// Needed for triggering the motor monoflop
 	uint8_t m_lastval;
 
-	// Signal motor_on. When TRUE, makes all drives turning.
+	// Signal motor_on. When true, makes all drives turning.
 	int m_MOTOR_ON;
 
 	// Calculates the index from the bit

src/devices/bus/ti99_peb/peribox.h

@@ -231,10 +231,10 @@ protected:
 	int m_senila;
 	int m_senilb;
 
-	// When TRUE, card is accessible. Indicated by a LED.
+	// When true, card is accessible. Indicated by a LED.
 	bool    m_selected;
 
-	// When TRUE, GenMod is selected. Modified by peribox_slot_device.
+	// When true, GenMod is selected. Modified by peribox_slot_device.
 	bool    m_genmod;
 
 	// CRU base. Used to configure the address by which a card is selected.

src/devices/bus/ti99_peb/spchsyn.cpp

@@ -104,7 +104,7 @@ SETADDRESS_DBIN_MEMBER( ti_speech_synthesizer_device::setaddress_dbin )
 
 WRITE_LINE_MEMBER( ti_speech_synthesizer_device::speech_ready )
 {
-	// The TMS5200 implementation uses TRUE/FALSE, not ASSERT/CLEAR semantics
+	// The TMS5200 implementation uses true/false, not ASSERT/CLEAR semantics
 	// and we have to adapt a /READY to a READY line.
 	// The real synthesizer board uses a transistor for that purpose.
 	m_slot->set_ready((state==0)? ASSERT_LINE : CLEAR_LINE);

src/devices/bus/ti99_peb/ti_fdc.h

@@ -68,13 +68,13 @@ private:
 	// Needed for triggering the motor monoflop
 	uint8_t   m_lastval;
 
-	// Signal DVENA. When TRUE, makes some drive turning.
+	// Signal DVENA. When true, makes some drive turning.
 	int  m_DVENA;
 
 	// Set when address is in card area
 	bool    m_inDsrArea;
 
-	// When TRUE the CPU is halted while DRQ/IRQ are true.
+	// When true the CPU is halted while DRQ/IRQ are true.
 	bool    m_WAITena;
 
 	// WD chip selected

src/devices/bus/ti99x/990_dk.cpp

@@ -100,7 +100,7 @@ void fd800_machine_init(void (*interrupt_callback)(running_machine &machine, int
     cylinder_id: cylinder ID read
     sector_id: sector ID read
 
-    Return TRUE if an ID was found
+    Return true if an ID was found
 */
 int fd800_legacy_device::read_id(int unit, int head, int *cylinder_id, int *sector_id)
 {
@@ -117,11 +117,11 @@ int fd800_legacy_device::read_id(int unit, int head, int *cylinder_id, int *sect
 	            *cylinder_id = id.C;
 	        if (sector_id)
 	            *sector_id = id.R;
-	        return TRUE;
+	        return true;
 	    }
 	}*/
 
-	return FALSE;
+	return false;
 }
 
 /*
@@ -132,7 +132,7 @@ int fd800_legacy_device::read_id(int unit, int head, int *cylinder_id, int *sect
     sector: sector ID to search
     data_id: data ID to be used when calling sector read/write functions
 
-    Return TRUE if the given sector ID was found
+    Return true if the given sector ID was found
 */
 int fd800_legacy_device::find_sector(int unit, int head, int sector, int *data_id)
 {
@@ -151,12 +151,12 @@ int fd800_legacy_device::find_sector(int unit, int head, int sector, int *data_i
                 *data_id = id.data_id;
                 // get ddam status
                 // w->ddam = id.flags & ID_FLAG_DELETED_DATA;
-                return TRUE;
+                return true;
             }
         }
     }
 */
-	return FALSE;
+	return false;
 }
 
 /*
@@ -166,7 +166,7 @@ int fd800_legacy_device::find_sector(int unit, int head, int sector, int *data_i
     cylinder: track to seek for
     head: head for which the seek is performed
 
-    Return FALSE if the seek was successful
+    Return false if the seek was successful
 */
 int fd800_legacy_device::do_seek(int unit, int cylinder, int head)
 {
@@ -175,13 +175,13 @@ int fd800_legacy_device::do_seek(int unit, int cylinder, int head)
     if (cylinder > 76)
     {
         m_stat_reg |= status_invalid_cmd;
-        return TRUE;
+        return true;
     }
 
     if (m_drv[unit].img == nullptr || !m_drv[unit].img->exists())
     {
         m_stat_reg |= status_drv_not_ready;
-        return TRUE;
+        return true;
     }
 
     if (m_drv[unit].log_cylinder[head] == -1)
@@ -189,14 +189,14 @@ int fd800_legacy_device::do_seek(int unit, int cylinder, int head)
         if (!read_id(unit, head, &m_drv[unit].log_cylinder[head], nullptr))
         {
             m_stat_reg |= status_ID_not_found;
-            return TRUE;
+            return true;
         }
     }
 
     if (m_drv[unit].log_cylinder[head] == cylinder)
     {
 
-        return FALSE;
+        return false;
     }
     for (retries=0; retries<10; retries++)
     {
@@ -209,19 +209,19 @@ int fd800_legacy_device::do_seek(int unit, int cylinder, int head)
         {
             m_drv[unit].log_cylinder[head] = -1;
             m_stat_reg |= status_ID_not_found;
-            return TRUE;
+            return true;
         }
 
         if (m_drv[unit].log_cylinder[head] == cylinder)
         {
 
-            return FALSE;
+            return false;
         }
     }
 
     m_stat_reg |= status_seek_err;
     */
-	return TRUE;
+	return true;
 }
 
 /*
@@ -229,7 +229,7 @@ int fd800_legacy_device::do_seek(int unit, int cylinder, int head)
 
     unit: floppy drive index
 
-    Return FALSE if the restore was successful
+    Return false if the restore was successful
 */
 int fd800_legacy_device::do_restore(int unit)
 {
@@ -239,7 +239,7 @@ int fd800_legacy_device::do_restore(int unit)
     if (!m_drv[unit].img->exists())
     {
         m_stat_reg |= status_drv_not_ready;
-        return TRUE;
+        return true;
     }
 
 

src/devices/bus/ti99x/990_hd.h

@@ -58,8 +58,8 @@ private:
 		device_image_interface *img;                        /* image descriptor */
 		format_t format;
 		hard_disk_file *hd_handle;      /* mame hard disk descriptor - only if format == format_mame */
-		unsigned int wp : 1;                    /* TRUE if disk is write-protected */
+		unsigned int wp : 1;                    /* true if disk is write-protected */
-		unsigned int unsafe : 1;                /* TRUE when a disk has just been connected */
+		unsigned int unsafe : 1;                /* true when a disk has just been connected */
 
 		/* disk geometry */
 		unsigned int cylinders, heads, sectors_per_track, bytes_per_sector;

src/devices/bus/ti99x/990_tap.h

@@ -10,9 +10,9 @@ extern const device_type TI990_TAPE_CTRL;
 struct tape_unit_t
 {
 	device_image_interface *img;        // image descriptor
-	bool bot;   // TRUE if we are at the beginning of tape
+	bool bot;   // true if we are at the beginning of tape
-	bool eot;   // TRUE if we are at the end of tape
+	bool eot;   // true if we are at the end of tape
-	bool wp;    // TRUE if tape is write-protected
+	bool wp;    // true if tape is write-protected
 };
 
 class tap_990_device : public device_t

src/devices/bus/ti99x/998board.cpp

@@ -197,8 +197,8 @@ SETOFFSET_MEMBER( mainboard8_device::setoffset )
 	select_groms();
 
 	// Speech select lines will always be asserted/cleared as soon as the address is available
-	m_speech->wsq_w((m_vaquerro->spwt_out() == ASSERT_LINE)? FALSE : TRUE);
+	m_speech->wsq_w((m_vaquerro->spwt_out() == ASSERT_LINE)? false : true);
-	m_speech->rsq_w((m_vaquerro->sprd_out() == ASSERT_LINE)? FALSE : TRUE);
+	m_speech->rsq_w((m_vaquerro->sprd_out() == ASSERT_LINE)? false : true);
 
 	// If it is a logical space address, tell the mapper to stay inactive
 	line_state lasreq = (line_state)m_vaquerro->lascsq_out();
@@ -746,8 +746,8 @@ WRITE_LINE_MEMBER( mainboard8_device::sound_ready )
 
 WRITE_LINE_MEMBER( mainboard8_device::speech_ready )
 {
-	// The TMS5200 implementation uses TRUE/FALSE, not ASSERT/CLEAR semantics
+	// The TMS5200 implementation uses true/false, not ASSERT/CLEAR semantics
-	m_speech_ready = (state==FALSE)? ASSERT_LINE : CLEAR_LINE;
+	m_speech_ready = (state==false)? ASSERT_LINE : CLEAR_LINE;
 }
 
 WRITE_LINE_MEMBER( mainboard8_device::pbox_ready )

src/devices/bus/ti99x/handset.cpp

@@ -148,7 +148,7 @@ void ti99_handset_device::post_message(int message)
     poll_keyboard()
     Poll the current state of one given handset keypad.
     num: number of the keypad to poll (0-3)
-    Returns TRUE if the handset state has changed and a message was posted.
+    Returns true if the handset state has changed and a message was posted.
 */
 bool ti99_handset_device::poll_keyboard(int num)
 {
@@ -219,7 +219,7 @@ bool ti99_handset_device::poll_keyboard(int num)
 
     Poll the current state of one given handset joystick.
     num: number of the joystick to poll (0-3)
-    Returns TRUE if the handset state has changed and a message was posted.
+    Returns true if the handset state has changed and a message was posted.
 */
 bool ti99_handset_device::poll_joystick(int num)
 {

src/devices/bus/vcs/vcs_slot.cpp

@@ -222,7 +222,7 @@ image_init_result vcs_cart_slot_device::call_load()
 		if (software_entry() != nullptr)
 		{
 			const char *pcb_name;
-			bool has_ram = get_software_region("ram") ? TRUE : FALSE;
+			bool has_ram = get_software_region("ram") ? true : false;
 			memcpy(ROM, get_software_region("rom"), len);
 
 			if ((pcb_name = get_feature("slot")) != nullptr)

src/devices/cpu/apexc/apexc.cpp

@@ -524,7 +524,7 @@ void apexc_cpu_device::execute()
 		case 0:
 			/* stop */
 
-			m_running = FALSE;
+			m_running = false;
 
 			/* BTW, I don't know whether stop loads y into ml or not, and whether
 			subsequent fetch is done */
@@ -835,7 +835,7 @@ void apexc_cpu_device::device_reset()
 
 	/* next two lines are just the product of my bold fantasy */
 	m_cr = 0;               /* first instruction executed will be a stop */
-	m_running = TRUE;       /* this causes the CPU to load the instruction at 0/0,
+	m_running = true;       /* this causes the CPU to load the instruction at 0/0,
 	                           which enables easy booting (just press run on the panel) */
 	m_a = 0;
 	m_r = 0;

src/devices/cpu/arm7/arm7.cpp

@@ -353,7 +353,7 @@ bool arm7_cpu_device::arm7_tlb_translate(offs_t &addr, int flags)
 			LOG( ( "ARM7: Translation fault on unmapped virtual address, PC = %08x, vaddr = %08x\n", m_r[eR15], addr ) );
 			m_pendingAbtP = true;
 		}
-		return FALSE;
+		return false;
 	}
 	else
 	{
@@ -383,7 +383,7 @@ bool arm7_cpu_device::arm7_tlb_translate(offs_t &addr, int flags)
 					LOG( ( "ARM7: Translation fault on unmapped virtual address, vaddr = %08x, PC %08X\n", addr, m_r[eR15] ) );
 					m_pendingAbtP = true;
 				}
-				return FALSE;
+				return false;
 			case COPRO_TLB_LARGE_PAGE:
 				// Large page descriptor
 				addr = ( desc_lvl2 & COPRO_TLB_LARGE_PAGE_MASK ) | ( addr & ~COPRO_TLB_LARGE_PAGE_MASK );
@@ -578,7 +578,7 @@ void arm7_cpu_device::device_reset()
 	SwitchMode(eARM7_MODE_SVC);
 	m_r[eR15] = 0;
 
-	m_impstate.cache_dirty = TRUE;
+	m_impstate.cache_dirty = true;
 }
 
 

src/devices/cpu/arm7/arm7.h

@@ -279,7 +279,7 @@ protected:
 	{
 		offs_t              start;                      /* start of the RAM block */
 		offs_t              end;                        /* end of the RAM block */
-		uint8_t               readonly;                   /* TRUE if read-only */
+		bool                readonly;                   /* true if read-only */
 		void *              base;                       /* base in memory where the RAM lives */
 	};
 
@@ -486,7 +486,7 @@ protected:
 	bool drcarm7ops_cd(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t op);
 	bool drcarm7ops_e(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t op);
 	bool drcarm7ops_f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t op);
-	int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
 
 };
 

src/devices/cpu/arm7/arm7drc.hxx

@@ -188,7 +188,7 @@ void arm7_cpu_device::arm7_drc_init()
 	}
 
 	/* mark the cache dirty so it is updated on next execute */
-	m_impstate.cache_dirty = TRUE;
+	m_impstate.cache_dirty = true;
 }
 
 
@@ -205,7 +205,7 @@ void arm7_cpu_device::execute_run_drc()
 	/* reset the cache if dirty */
 	if (m_impstate.cache_dirty)
 		code_flush_cache();
-	m_impstate.cache_dirty = FALSE;
+	m_impstate.cache_dirty = false;
 
 	/* execute */
 	do
@@ -307,12 +307,12 @@ void arm7_cpu_device::code_flush_cache()
 		//static_generate_tlb_mismatch();
 
 		/* add subroutines for memory accesses */
-		static_generate_memory_accessor(1, FALSE, FALSE, "read8",       &m_impstate.read8);
+		static_generate_memory_accessor(1, false, false, "read8",       &m_impstate.read8);
-		static_generate_memory_accessor(1, TRUE,  FALSE, "write8",      &m_impstate.write8);
+		static_generate_memory_accessor(1, true,  false, "write8",      &m_impstate.write8);
-		static_generate_memory_accessor(2, FALSE, FALSE, "read16",      &m_impstate.read16);
+		static_generate_memory_accessor(2, false, false, "read16",      &m_impstate.read16);
-		static_generate_memory_accessor(2, TRUE,  FALSE, "write16",     &m_impstate.write16);
+		static_generate_memory_accessor(2, true,  false, "write16",     &m_impstate.write16);
-		static_generate_memory_accessor(4, FALSE, FALSE, "read32",      &m_impstate.read32);
+		static_generate_memory_accessor(4, false, false, "read32",      &m_impstate.read32);
-		static_generate_memory_accessor(4, TRUE,  FALSE, "write32",     &m_impstate.write32);
+		static_generate_memory_accessor(4, true,  false, "write32",     &m_impstate.write32);
 	}
 	catch (drcuml_block::abort_compilation &)
 	{
@@ -331,7 +331,7 @@ void arm7_cpu_device::code_compile_block(uint8_t mode, offs_t pc)
 	drcuml_state *drcuml = m_impstate.drcuml;
 	compiler_state compiler = { 0 };
 	const opcode_desc *seqlast;
-	int override = FALSE;
+	bool override = false;
 
 	g_profiler.start(PROFILER_DRC_COMPILE);
 
@@ -374,7 +374,7 @@ void arm7_cpu_device::code_compile_block(uint8_t mode, offs_t pc)
 				/* are recompiling due to being out of sync and allow future overrides */
 				else if (seqhead == desclist)
 				{
-					override = TRUE;
+					override = true;
 					UML_HASH(block, mode, seqhead->pc);                                     // hash    mode,pc
 				}
 
@@ -1169,7 +1169,7 @@ void arm7_cpu_device::generate_update_cycles(drcuml_block *block, compiler_state
 	{
 		uml::code_label skip;
 
-		compiler->checkints = FALSE;
+		compiler->checkints = false;
 		UML_CALLH(block, *m_impstate.check_irq);
 	}
 
@@ -1685,7 +1685,7 @@ bool arm7_cpu_device::drcarm7ops_f(drcuml_block *block, compiler_state *compiler
     opcode
 -------------------------------------------------*/
 
-int arm7_cpu_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool arm7_cpu_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
 {
 	//int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0);
 	uint32_t op = desc->opptr.l[0];
@@ -1711,7 +1711,7 @@ int arm7_cpu_device::generate_opcode(drcuml_block *block, compiler_state *compil
 	if (T_IS_SET(GET_CPSR))
 	{
 		//UML_CALLH(block, *m_impstate.drcthumb[(op & 0xffc0) >> 6]);          // callh    drcthumb[op] // TODO FIXME
-		return TRUE;
+		return true;
 	}
 
 	switch (op >> INSN_COND_SHIFT)
@@ -1825,10 +1825,10 @@ int arm7_cpu_device::generate_opcode(drcuml_block *block, compiler_state *compil
 		/* ----- sub-groups ----- */
 
 		case 0x00:  /* SPECIAL - MIPS I */
-			return TRUE;
+			return true;
 
 		// TODO: FINISH ME
 	}
 
-	return FALSE;
+	return false;
 }

src/devices/cpu/ccpu/ccpu.cpp

@@ -83,7 +83,7 @@ READ8_MEMBER( ccpu_cpu_device::read_jmi )
 
 void ccpu_cpu_device::wdt_timer_trigger()
 {
-	m_waiting = FALSE;
+	m_waiting = false;
 	m_watchdog++;
 	if (m_watchdog >= 3)
 		m_PC = 0;
@@ -180,7 +180,7 @@ void ccpu_cpu_device::device_reset()
 	m_miflag = m_nextmiflag = m_nextnextmiflag = 0;
 	m_drflag = 0;
 
-	m_waiting = FALSE;
+	m_waiting = false;
 	m_watchdog = 0;
 }
 
@@ -568,7 +568,7 @@ void ccpu_cpu_device::execute_run()
 			/* FRM */
 			case 0xe5:
 			case 0xf5:
-				m_waiting = TRUE;
+				m_waiting = true;
 				NEXT_ACC_A;
 				m_icount = -1;
 

src/devices/cpu/drcbec.cpp

@@ -1581,19 +1581,19 @@ int drcbe_c::execute(code_handle &entry)
 				break;
 
 			case MAKE_OPCODE_SHORT(OP_MULU, 8, 0):      // DMULU   dst,edst,src1,src2[,f]
-				dmulu(*inst[0].puint64, *inst[1].puint64, DPARAM2, DPARAM3, FALSE);
+				dmulu(*inst[0].puint64, *inst[1].puint64, DPARAM2, DPARAM3, false);
 				break;
 
 			case MAKE_OPCODE_SHORT(OP_MULU, 8, 1):
-				flags = dmulu(*inst[0].puint64, *inst[1].puint64, DPARAM2, DPARAM3, TRUE);
+				flags = dmulu(*inst[0].puint64, *inst[1].puint64, DPARAM2, DPARAM3, true);
 				break;
 
 			case MAKE_OPCODE_SHORT(OP_MULS, 8, 0):      // DMULS   dst,edst,src1,src2[,f]
-				dmuls(*inst[0].puint64, *inst[1].puint64, DPARAM2, DPARAM3, FALSE);
+				dmuls(*inst[0].puint64, *inst[1].puint64, DPARAM2, DPARAM3, false);
 				break;
 
 			case MAKE_OPCODE_SHORT(OP_MULS, 8, 1):
-				flags = dmuls(*inst[0].puint64, *inst[1].puint64, DPARAM2, DPARAM3, TRUE);
+				flags = dmuls(*inst[0].puint64, *inst[1].puint64, DPARAM2, DPARAM3, true);
 				break;
 
 			case MAKE_OPCODE_SHORT(OP_DIVU, 8, 0):      // DDIVU   dst,edst,src1,src2[,f]
@@ -2220,10 +2220,10 @@ void drcbe_c::fixup_label(void *parameter, drccodeptr labelcodeptr)
 //  dmulu - perform a double-wide unsigned multiply
 //-------------------------------------------------
 
-int drcbe_c::dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2, int flags)
+int drcbe_c::dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2, bool flags)
 {
 	// shortcut if we don't care about the high bits or the flags
-	if (&dstlo == &dsthi && flags == 0)
+	if (&dstlo == &dsthi && flags == false)
 	{
 		dstlo = src1 * src2;
 		return 0;
@@ -2264,10 +2264,10 @@ int drcbe_c::dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src
 //  dmuls - perform a double-wide signed multiply
 //-------------------------------------------------
 
-int drcbe_c::dmuls(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2, int flags)
+int drcbe_c::dmuls(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2, bool flags)
 {
 	// shortcut if we don't care about the high bits or the flags
-	if (&dstlo == &dsthi && flags == 0)
+	if (&dstlo == &dsthi && flags == false)
 	{
 		dstlo = src1 * src2;
 		return 0;

src/devices/cpu/drcbec.h

@@ -42,8 +42,8 @@ private:
 	// helpers
 	void output_parameter(drcbec_instruction **dstptr, void **immedptr, int size, const uml::parameter &param);
 	void fixup_label(void *parameter, drccodeptr labelcodeptr);
-	int dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2, int flags);
+	int dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2, bool flags);
-	int dmuls(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2, int flags);
+	int dmuls(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2, bool flags);
 	uint32_t tzcount32(uint32_t value);
 	uint64_t tzcount64(uint64_t value);
 

src/devices/cpu/drcbex86.cpp

@@ -6615,10 +6615,10 @@ void drcbe_x86::op_icopyf(x86code *&dst, const instruction &inst)
 //  dmulu - perform a double-wide unsigned multiply
 //-------------------------------------------------
 
-int drcbe_x86::dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2, int flags)
+int drcbe_x86::dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2, bool flags)
 {
 	// shortcut if we don't care about the high bits or the flags
-	if (&dstlo == &dsthi && flags == 0)
+	if (&dstlo == &dsthi && flags == false)
 	{
 		dstlo = src1 * src2;
 		return 0;
@@ -6659,13 +6659,13 @@ int drcbe_x86::dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t s
 //  dmuls - perform a double-wide signed multiply
 //-------------------------------------------------
 
-int drcbe_x86::dmuls(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2, int flags)
+int drcbe_x86::dmuls(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2, bool flags)
 {
 	uint64_t lo, hi, prevlo;
 	uint64_t a, b, temp;
 
 	// shortcut if we don't care about the high bits or the flags
-	if (&dstlo == &dsthi && flags == 0)
+	if (&dstlo == &dsthi && flags == false)
 	{
 		dstlo = src1 * src2;
 		return 0;

src/devices/cpu/drcbex86.h

@@ -286,8 +286,8 @@ private:
 	void emit_fstp_p(x86code *&dst, int size, const be_parameter &param);
 
 	// callback helpers
-	static int dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2, int flags);
+	static int dmulu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2, bool flags);
-	static int dmuls(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2, int flags);
+	static int dmuls(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2, bool flags);
 	static int ddivu(uint64_t &dstlo, uint64_t &dsthi, uint64_t src1, uint64_t src2);
 	static int ddivs(uint64_t &dstlo, uint64_t &dsthi, int64_t src1, int64_t src2);
 

src/devices/cpu/drcuml.cpp

@@ -470,7 +470,7 @@ void drcuml_block::disassemble()
 			{
 				m_drcuml.log_printf("\t%-50.50s; %s\n", dasm.c_str(), get_comment_text(m_inst[firstcomment], comment));
 				firstcomment++;
-				flushcomments = TRUE;
+				flushcomments = true;
 			}
 			else
 				m_drcuml.log_printf("\t%s\n", dasm.c_str());
@@ -766,7 +766,7 @@ static void bevalidate_iterate_over_params(drcuml_state *drcuml, code_handle **h
 			// iterate over possibilities
 			for (pindex = 0; pindex < pcount; pindex++)
 			{
-				int skip = FALSE;
+				bool skip = false;
 				int pscannum;
 
 				// for param 0, print a dot
@@ -779,7 +779,7 @@ static void bevalidate_iterate_over_params(drcuml_state *drcuml, code_handle **h
 					// loop over all parameters we've done before; if the parameter is a source and matches us, skip this case
 					for (pscannum = 0; pscannum < pnum; pscannum++)
 						if ((opinfo->param[pscannum].output & PIO_IN) && ptype == paramlist[pscannum].type && pindex == paramlist[pscannum].value)
-							skip = TRUE;
+							skip = true;
 
 				// can't duplicate multiple dest parameters
 				if (opinfo->param[pnum].output & PIO_OUT)
@@ -787,7 +787,7 @@ static void bevalidate_iterate_over_params(drcuml_state *drcuml, code_handle **h
 					// loop over all parameters we've done before; if the parameter is a source and matches us, skip this case
 					for (pscannum = 0; pscannum < pnum; pscannum++)
 						if ((opinfo->param[pscannum].output & PIO_OUT) && ptype == paramlist[pscannum].type && pindex == paramlist[pscannum].value)
-							skip = TRUE;
+							skip = true;
 
 				// iterate over the next parameter in line
 				if (!skip)

src/devices/cpu/dsp56k/dsp56k.cpp

@@ -147,11 +147,11 @@ void dsp56k_device::execute_set_input(int irqline, int state)
 				logerror("DSP56k IRQA is set to fire on the \"Negative Edge\".\n");
 
 			if (state != CLEAR_LINE)
-				m_dsp56k_core.modA_state = TRUE;
+				m_dsp56k_core.modA_state = true;
 			else
-				m_dsp56k_core.modA_state = FALSE;
+				m_dsp56k_core.modA_state = false;
 
-			if (m_dsp56k_core.reset_state != TRUE)
+			if (m_dsp56k_core.reset_state != true)
 				dsp56k_add_pending_interrupt(&m_dsp56k_core, "IRQA");
 			break;
 
@@ -161,33 +161,33 @@ void dsp56k_device::execute_set_input(int irqline, int state)
 				logerror("DSP56k IRQB is set to fire on the \"Negative Edge\".\n");
 
 			if (state != CLEAR_LINE)
-				m_dsp56k_core.modB_state = TRUE;
+				m_dsp56k_core.modB_state = true;
 			else
-				m_dsp56k_core.modB_state = FALSE;
+				m_dsp56k_core.modB_state = false;
 
-			if (m_dsp56k_core.reset_state != TRUE)
+			if (m_dsp56k_core.reset_state != true)
 				dsp56k_add_pending_interrupt(&m_dsp56k_core, "IRQB");
 			break;
 
 		case DSP56K_IRQ_MODC:
 			if (state != CLEAR_LINE)
-				m_dsp56k_core.modC_state = TRUE;
+				m_dsp56k_core.modC_state = true;
 			else
-				m_dsp56k_core.modC_state = FALSE;
+				m_dsp56k_core.modC_state = false;
 
 			// TODO : Set bus mode or whatever
 			break;
 
 		case DSP56K_IRQ_RESET:
 			if (state != CLEAR_LINE)
-				m_dsp56k_core.reset_state = TRUE;
+				m_dsp56k_core.reset_state = true;
 			else
 			{
 				/* If it changes state from asserted to cleared.  Call the reset function. */
-				if (m_dsp56k_core.reset_state == TRUE)
+				if (m_dsp56k_core.reset_state == true)
 					device_reset();
 
-				m_dsp56k_core.reset_state = FALSE;
+				m_dsp56k_core.reset_state = false;
 			}
 
 			// dsp56k_add_pending_interrupt("Hardware RESET");
@@ -200,7 +200,7 @@ void dsp56k_device::execute_set_input(int irqline, int state)
 
 	/* If the reset line isn't asserted, service interrupts */
 	// TODO: Is it right to immediately service interrupts?
-	//if (cpustate->reset_state != TRUE)
+	//if (cpustate->reset_state != true)
 	//  pcu_service_interrupts();
 }
 
@@ -251,10 +251,10 @@ void dsp56k_device::device_start()
 	m_dsp56k_core.bootstrap_mode = BOOTSTRAP_OFF;
 
 	/* Clear the irq states */
-	m_dsp56k_core.modA_state = FALSE;
+	m_dsp56k_core.modA_state = false;
-	m_dsp56k_core.modB_state = FALSE;
+	m_dsp56k_core.modB_state = false;
-	m_dsp56k_core.modC_state = FALSE;
+	m_dsp56k_core.modC_state = false;
-	m_dsp56k_core.reset_state = FALSE;
+	m_dsp56k_core.reset_state = false;
 
 	/* save states - dsp56k_core members */
 	save_item(NAME(m_dsp56k_core.modA_state));

src/devices/cpu/dsp56k/dsp56k.h

@@ -170,10 +170,10 @@ struct dsp56k_core
 	dsp56k_host_interface HI;
 
 	// IRQ line states
-	uint8_t modA_state;
+	bool modA_state;
-	uint8_t modB_state;
+	bool modB_state;
-	uint8_t modC_state;
+	bool modC_state;
-	uint8_t reset_state;
+	bool reset_state;
 
 	// HACK - Bootstrap mode state variable.
 	uint8_t bootstrap_mode;

src/devices/cpu/h6280/h6280.cpp

@@ -2568,7 +2568,7 @@ bool h6280_device::memory_translate(address_spacenum spacenum, int intention, of
 	if (spacenum == AS_PROGRAM)
 		address = translated(address);
 
-	return TRUE;
+	return true;
 }
 
 uint8_t h6280_device::io_get_buffer()

src/devices/cpu/i8085/i8085.cpp

@@ -334,7 +334,7 @@ void i8085a_cpu_device::check_for_interrupts()
 		m_trap_im_copy = m_IM | 0x80;
 
 		/* reset the pending state */
-		m_trap_pending = FALSE;
+		m_trap_pending = false;
 
 		/* break out of HALT state and call the IRQ ack callback */
 		break_halt_for_interrupt();
@@ -987,8 +987,8 @@ void i8085a_cpu_device::device_reset()
 	m_HALT = 0;
 	m_IM &= ~IM_I75;
 	m_IM |= IM_M55 | IM_M65 | IM_M75;
-	m_after_ei = FALSE;
+	m_after_ei = false;
-	m_trap_pending = FALSE;
+	m_trap_pending = false;
 	m_trap_im_copy = 0;
 	set_inte(0);
 	set_sod(0);
@@ -1076,7 +1076,7 @@ void i8085a_cpu_device::execute_set_input(int irqline, int state)
 	if (irqline == INPUT_LINE_NMI)
 	{
 		if (!m_nmi_state && newstate)
-			m_trap_pending = TRUE;
+			m_trap_pending = true;
 		m_nmi_state = newstate;
 	}
 

src/devices/cpu/i86/i286.cpp

@@ -317,7 +317,7 @@ bool i80286_cpu_device::memory_translate(address_spacenum spacenum, int intentio
 	if(spacenum == AS_PROGRAM)
 		address &= m_amask;
 
-	return TRUE;
+	return true;
 }
 
 void i80286_cpu_device::execute_set_input(int inptnum, int state)

src/devices/cpu/m6800/m6800.cpp

@@ -711,7 +711,7 @@ void m6800_cpu_device::CHECK_IRQ_LINES()
 		if(m_wai_state & M6800_SLP)
 			m_wai_state &= ~M6800_SLP;
 
-		m_nmi_pending = FALSE;
+		m_nmi_pending = false;
 		enter_interrupt("M6800 '%s' take NMI\n",0xfffc);
 	}
 	else
@@ -1212,7 +1212,7 @@ void m6800_cpu_device::execute_set_input(int irqline, int state)
 	{
 	case INPUT_LINE_NMI:
 		if (!m_nmi_state && state != CLEAR_LINE)
-			m_nmi_pending = TRUE;
+			m_nmi_pending = true;
 		m_nmi_state = state;
 		break;
 

src/devices/cpu/m68000/m68kcpu.cpp

@@ -656,7 +656,7 @@ static void set_irq_line(m68000_base_device *m68k, int irqline, int state)
 	/* A transition from < 7 to 7 always interrupts (NMI) */
 	/* Note: Level 7 can also level trigger like a normal IRQ */
 	if(old_level != 0x0700 && m68k->int_level == 0x0700)
-		m68k->nmi_pending = TRUE;
+		m68k->nmi_pending = true;
 }
 
 void m68000_base_device::presave()
@@ -733,7 +733,7 @@ bool m68000_base_device::memory_translate(address_spacenum space, int intention,
 			mmu_tmp_sr = temp_mmu_tmp_sr;
 		}
 	}
-	return TRUE;
+	return true;
 }
 
 
@@ -2623,7 +2623,7 @@ bool m68020hmmu_device::memory_translate(address_spacenum space, int intention,
 			address = hmmu_translate_addr(this, address);
 		}
 	}
-	return TRUE;
+	return true;
 }
 
 

src/devices/cpu/m68000/m68kcpu.h

@@ -1682,7 +1682,7 @@ static inline void m68ki_check_interrupts(m68000_base_device *m68k)
 {
 	if(m68k->nmi_pending)
 	{
-		m68k->nmi_pending = FALSE;
+		m68k->nmi_pending = false;
 		m68k->m68ki_exception_interrupt(m68k, 7);
 	}
 	else if(m68k->int_level > m68k->int_mask)

src/devices/cpu/m6809/6309dasm.cpp

@@ -613,7 +613,8 @@ CPU_DISASSEMBLE( hd6309 )
 	unsigned int ea, flags;
 	int numoperands, offset, indirect;
 
-	int i, p = 0, page = 0, opcode_found;
+	int i, p = 0, page = 0;
+	bool opcode_found;
 
 	do
 	{
@@ -623,7 +624,7 @@ CPU_DISASSEMBLE( hd6309 )
 				break;
 
 		if (i < hd6309_numops[page])
-			opcode_found = TRUE;
+			opcode_found = true;
 		else
 		{
 			strcpy(buffer, "Illegal Opcode");
@@ -633,7 +634,7 @@ CPU_DISASSEMBLE( hd6309 )
 		if (hd6309_pgpointers[page][i].mode >= PG1)
 		{
 			page = hd6309_pgpointers[page][i].mode - PG1 + 1;
-			opcode_found = FALSE;
+			opcode_found = false;
 		}
 	} while (!opcode_found);
 
@@ -749,7 +750,7 @@ CPU_DISASSEMBLE( hd6309 )
 
 		reg = (pb >> 5) & 3;
 		pbm = pb & 0x8f;
-		indirect = ((pb & 0x90) == 0x90 )? TRUE : FALSE;
+		indirect = ((pb & 0x90) == 0x90 )? true : false;
 
 		// open brackets if indirect
 		if (indirect && pbm != 0x82)

src/devices/cpu/m6809/6809dasm.cpp

@@ -371,8 +371,10 @@ CPU_DISASSEMBLE( m6809 )
 	uint8_t opcode, mode, pb, pbm, reg;
 	const uint8_t *operandarray;
 	unsigned int ea, flags;
-	int numoperands, offset, indirect;
+	int numoperands, offset;
-	int i, p = 0, page = 0, opcode_found;
+	bool indirect;
+	int i, p = 0, page = 0;
+	bool opcode_found;
 
 	do
 	{
@@ -383,7 +385,7 @@ CPU_DISASSEMBLE( m6809 )
 				break;
 
 		if (i < m6809_numops[page])
-			opcode_found = TRUE;
+			opcode_found = true;
 		else
 		{
 			strcpy(buffer, "Illegal Opcode");
@@ -393,7 +395,7 @@ CPU_DISASSEMBLE( m6809 )
 		if (m6809_pgpointers[page][i].mode >= PG1)
 		{
 			page = m6809_pgpointers[page][i].mode - PG1 + 1;
-			opcode_found = FALSE;
+			opcode_found = false;
 		}
 	} while (!opcode_found);
 
@@ -485,7 +487,7 @@ CPU_DISASSEMBLE( m6809 )
 		pb = operandarray[0];
 		reg = (pb >> 5) & 3;
 		pbm = pb & 0x8f;
-		indirect = ((pb & 0x90) == 0x90 )? TRUE : FALSE;
+		indirect = ((pb & 0x90) == 0x90 )? true : false;
 
 		// open brackets if indirect
 		if (indirect && pbm != 0x80 && pbm != 0x82)

src/devices/cpu/m6809/knmidasm.cpp

@@ -4,11 +4,6 @@
 #include "debugger.h"
 #include "konami.h"
 
-#ifndef TRUE
-#define TRUE    -1
-#define FALSE   0
-#endif
-
 /*
 
 0x08 leax indexed

src/devices/cpu/mcs48/mcs48.cpp

@@ -640,8 +640,8 @@ OPHANDLER( dec_r5 )         { R5--; return 1; }
 OPHANDLER( dec_r6 )         { R6--; return 1; }
 OPHANDLER( dec_r7 )         { R7--; return 1; }
 
-OPHANDLER( dis_i )          { m_xirq_enabled = FALSE; return 1; }
+OPHANDLER( dis_i )          { m_xirq_enabled = false; return 1; }
-OPHANDLER( dis_tcnti )      { m_tirq_enabled = FALSE; m_timer_overflow = FALSE; return 1; }
+OPHANDLER( dis_tcnti )      { m_tirq_enabled = false; m_timer_overflow = false; return 1; }
 
 OPHANDLER( djnz_r0 )        { execute_jcc(--R0 != 0); return 2; }
 OPHANDLER( djnz_r1 )        { execute_jcc(--R1 != 0); return 2; }
@@ -652,10 +652,10 @@ OPHANDLER( djnz_r5 )        { execute_jcc(--R5 != 0); return 2; }
 OPHANDLER( djnz_r6 )        { execute_jcc(--R6 != 0); return 2; }
 OPHANDLER( djnz_r7 )        { execute_jcc(--R7 != 0); return 2; }
 
-OPHANDLER( en_i )           { m_xirq_enabled = TRUE; return 1 + check_irqs(); }
+OPHANDLER( en_i )           { m_xirq_enabled = true; return 1 + check_irqs(); }
-OPHANDLER( en_tcnti )       { m_tirq_enabled = TRUE; return 1 + check_irqs(); }
+OPHANDLER( en_tcnti )       { m_tirq_enabled = true; return 1 + check_irqs(); }
-OPHANDLER( en_dma )         { m_dma_enabled = TRUE; port_w(2, m_p2); return 1; }
+OPHANDLER( en_dma )         { m_dma_enabled = true; port_w(2, m_p2); return 1; }
-OPHANDLER( en_flags )       { m_flags_enabled = TRUE; port_w(2, m_p2); return 1; }
+OPHANDLER( en_flags )       { m_flags_enabled = true; port_w(2, m_p2); return 1; }
 OPHANDLER( ent0_clk )
 {
 	logerror("MCS-48 PC:%04X - Unimplemented opcode = %02x\n", m_pc - 1, program_r(m_pc - 1));
@@ -709,7 +709,7 @@ OPHANDLER( jnt_0 )          { execute_jcc(test_r(0) == 0); return 2; }
 OPHANDLER( jnt_1 )          { execute_jcc(test_r(1) == 0); return 2; }
 OPHANDLER( jnz )            { execute_jcc(m_a != 0); return 2; }
 OPHANDLER( jobf )           { execute_jcc((m_sts & STS_OBF) != 0); return 2; }
-OPHANDLER( jtf )            { execute_jcc(m_timer_flag); m_timer_flag = FALSE; return 2; }
+OPHANDLER( jtf )            { execute_jcc(m_timer_flag); m_timer_flag = false; return 2; }
 OPHANDLER( jt_0 )           { execute_jcc(test_r(0) != 0); return 2; }
 OPHANDLER( jt_1 )           { execute_jcc(test_r(1) != 0); return 2; }
 OPHANDLER( jz )             { execute_jcc(m_a == 0); return 2; }
@@ -823,7 +823,7 @@ OPHANDLER( retr )
 	pull_pc_psw();
 
 	/* implicitly clear the IRQ in progress flip flop and re-check interrupts */
-	m_irq_in_progress = FALSE;
+	m_irq_in_progress = false;
 	return 2 + check_irqs();
 }
 
@@ -1036,17 +1036,17 @@ void mcs48_cpu_device::device_reset()
 	m_p2 = 0xff;
 	port_w(1, m_p1);
 	port_w(2, m_p2);
-	m_tirq_enabled = FALSE;
+	m_tirq_enabled = false;
-	m_xirq_enabled = FALSE;
+	m_xirq_enabled = false;
 	m_timecount_enabled = 0;
-	m_timer_flag = FALSE;
+	m_timer_flag = false;
 	m_sts = 0;
-	m_flags_enabled = FALSE;
+	m_flags_enabled = false;
-	m_dma_enabled = FALSE;
+	m_dma_enabled = false;
 
 	/* confirmed from interrupt logic description */
-	m_irq_in_progress = FALSE;
+	m_irq_in_progress = false;
-	m_timer_overflow = FALSE;
+	m_timer_overflow = false;
 }
 
 
@@ -1068,7 +1068,7 @@ int mcs48_cpu_device::check_irqs()
 	/* external interrupts take priority */
 	if ((m_irq_state || (m_sts & STS_IBF) != 0) && m_xirq_enabled)
 	{
-		m_irq_in_progress = TRUE;
+		m_irq_in_progress = true;
 
 		/* transfer to location 0x03 */
 		push_pc_psw();
@@ -1082,14 +1082,14 @@ int mcs48_cpu_device::check_irqs()
 	/* timer overflow interrupts follow */
 	if (m_timer_overflow && m_tirq_enabled)
 	{
-		m_irq_in_progress = TRUE;
+		m_irq_in_progress = true;
 
 		/* transfer to location 0x07 */
 		push_pc_psw();
 		m_pc = 0x07;
 
 		/* timer overflow flip-flop is reset once taken */
-		m_timer_overflow = FALSE;
+		m_timer_overflow = false;
 		return 2;
 	}
 	return 0;
@@ -1103,7 +1103,7 @@ int mcs48_cpu_device::check_irqs()
 
 void mcs48_cpu_device::burn_cycles(int count)
 {
-	int timerover = FALSE;
+	int timerover = false;
 
 	/* if the timer is enabled, accumulate prescaler cycles */
 	if (m_timecount_enabled & TIMER_ENABLED)
@@ -1127,12 +1127,12 @@ void mcs48_cpu_device::burn_cycles(int count)
 	/* if either source caused a timer overflow, set the flags and check IRQs */
 	if (timerover)
 	{
-		m_timer_flag = TRUE;
+		m_timer_flag = true;
 
 		/* according to the docs, if an overflow occurs with interrupts disabled, the overflow is not stored */
 		if (m_tirq_enabled)
 		{
-			m_timer_overflow = TRUE;
+			m_timer_overflow = true;
 			check_irqs();
 		}
 	}

src/devices/cpu/mcs48/mcs48.h

@@ -175,15 +175,15 @@ protected:
 	uint8_t       m_dbbi;               /* 8-bit input data buffer (UPI-41 only) */
 	uint8_t       m_dbbo;               /* 8-bit output data buffer (UPI-41 only) */
 
-	uint8_t       m_irq_state;          /* TRUE if an IRQ is pending */
+	bool          m_irq_state;          /* true if an IRQ is pending */
-	uint8_t       m_irq_in_progress;    /* TRUE if an IRQ is in progress */
+	bool          m_irq_in_progress;    /* true if an IRQ is in progress */
-	uint8_t       m_timer_overflow;     /* TRUE on a timer overflow; cleared by taking interrupt */
+	bool          m_timer_overflow;     /* true on a timer overflow; cleared by taking interrupt */
-	uint8_t       m_timer_flag;         /* TRUE on a timer overflow; cleared on JTF */
+	bool          m_timer_flag;         /* true on a timer overflow; cleared on JTF */
-	uint8_t       m_tirq_enabled;       /* TRUE if the timer IRQ is enabled */
+	bool          m_tirq_enabled;       /* true if the timer IRQ is enabled */
-	uint8_t       m_xirq_enabled;       /* TRUE if the external IRQ is enabled */
+	bool          m_xirq_enabled;       /* true if the external IRQ is enabled */
 	uint8_t       m_timecount_enabled;  /* bitmask of timer/counter enabled */
-	uint8_t       m_flags_enabled;      /* TRUE if I/O flags have been enabled (UPI-41 only) */
+	bool          m_flags_enabled;      /* true if I/O flags have been enabled (UPI-41 only) */
-	uint8_t       m_dma_enabled;        /* TRUE if DMA has been enabled (UPI-41 only) */
+	bool          m_dma_enabled;        /* true if DMA has been enabled (UPI-41 only) */
 
 	uint16_t      m_a11;                /* A11 value, either 0x000 or 0x800 */
 

src/devices/cpu/mcs48/mcs48dsm.cpp

@@ -12,7 +12,7 @@
 #include "emu.h"
 
 
-static uint32_t common_dasm(device_t *device, char *buffer, offs_t pc, const uint8_t *oprom, const uint8_t *opram, int upi41)
+static uint32_t common_dasm(device_t *device, char *buffer, offs_t pc, const uint8_t *oprom, const uint8_t *opram, bool upi41)
 {
 	const uint8_t *startram = opram;
 	uint32_t flags = 0;
@@ -317,11 +317,11 @@ static uint32_t common_dasm(device_t *device, char *buffer, offs_t pc, const uin
 
 CPU_DISASSEMBLE( mcs48 )
 {
-	return common_dasm(device, buffer, pc, oprom, opram, FALSE);
+	return common_dasm(device, buffer, pc, oprom, opram, false);
 }
 
 
 CPU_DISASSEMBLE( upi41 )
 {
-	return common_dasm(device, buffer, pc, oprom, opram, TRUE);
+	return common_dasm(device, buffer, pc, oprom, opram, true);
 }

src/devices/cpu/mips/mips3.cpp

@@ -421,7 +421,7 @@ void mips3_device::device_start()
 	}
 
 	/* mark the cache dirty so it is updated on next execute */
-	m_cache_dirty = TRUE;
+	m_cache_dirty = true;
 
 
 	/* register for save states */
@@ -943,7 +943,7 @@ void mips3_device::device_reset()
 	vtlb_load(2 * m_tlbentries + 1, (0xc0000000 - 0xa0000000) >> MIPS3_MIN_PAGE_SHIFT, 0xa0000000, 0x00000000 | VTLB_READ_ALLOWED | VTLB_WRITE_ALLOWED | VTLB_FETCH_ALLOWED | VTLB_FLAG_VALID);
 
 	m_core->mode = (MODE_KERNEL << 1) | 0;
-	m_cache_dirty = TRUE;
+	m_cache_dirty = true;
 	m_interrupt_cycles = 0;
 }
 
@@ -1156,7 +1156,7 @@ inline void mips3_device::WBYTE(offs_t address, uint8_t data)
 		const uint32_t tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
 		for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
 		{
-			if (m_fastram[ramnum].readonly == TRUE || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
+			if (m_fastram[ramnum].readonly == true || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
 			{
 				continue;
 			}
@@ -1190,7 +1190,7 @@ inline void mips3_device::WHALF(offs_t address, uint16_t data)
 		const uint32_t tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
 		for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
 		{
-			if (m_fastram[ramnum].readonly == TRUE || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
+			if (m_fastram[ramnum].readonly == true || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
 			{
 				continue;
 			}
@@ -1224,7 +1224,7 @@ inline void mips3_device::WWORD(offs_t address, uint32_t data)
 		const uint32_t tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
 		for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
 		{
-			if (m_fastram[ramnum].readonly == TRUE || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
+			if (m_fastram[ramnum].readonly == true || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
 			{
 				continue;
 			}
@@ -2718,7 +2718,7 @@ void mips3_device::execute_run()
 		/* reset the cache if dirty */
 		if (m_cache_dirty)
 			code_flush_cache();
-		m_cache_dirty = FALSE;
+		m_cache_dirty = false;
 
 		/* execute */
 		do

src/devices/cpu/mips/mips3.h

@@ -396,7 +396,7 @@ private:
 	{
 		offs_t              start;                      /* start of the RAM block */
 		offs_t              end;                        /* end of the RAM block */
-		uint8_t               readonly;                   /* TRUE if read-only */
+		bool                readonly;                   /* true if read-only */
 		void *              base;                       /* base in memory where the RAM lives */
 		uint8_t *             offset_base8;               /* base in memory where the RAM lives, 8-bit pointer, with the start offset pre-applied */
 		uint16_t *            offset_base16;              /* base in memory where the RAM lives, 16-bit pointer, with the start offset pre-applied  */
@@ -544,27 +544,27 @@ private:
 	void static_generate_memory_accessor(int mode, int size, int iswrite, int ismasked, const char *name, uml::code_handle **handleptr);
 
 	void generate_update_mode(drcuml_block *block);
-	void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
+	void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception);
 	void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
 	void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
 	void generate_delay_slot_and_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint8_t linkreg);
 
-	int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
-	int generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
-	int generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
-	int generate_idt(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_idt(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
 
-	int generate_set_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint8_t reg);
+	bool generate_set_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint8_t reg);
-	int generate_get_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint8_t reg);
+	bool generate_get_cop0_reg(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint8_t reg);
-	int generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
-	int generate_cop1_fr0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_cop1_fr0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
-	int generate_cop1_fr1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_cop1_fr1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
 	void generate_get_cop1_reg64(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, const uint32_t reg, const uml::parameter& param);
 	void generate_get_cop1_reg64_d2i(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, const uint32_t reg, const uml::parameter& param);
 	void generate_set_cop1_reg64(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, const uint32_t reg, const uml::parameter& param);
 	void generate_set_cop1_reg64_i2d(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, const uint32_t reg, const uml::parameter& param);
-	int generate_cop1x_fr0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_cop1x_fr0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
-	int generate_cop1x_fr1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_cop1x_fr1(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
 
 	void check_cop0_access(drcuml_block *block);
 	void check_cop1_access(drcuml_block *block);

src/devices/cpu/mips/mips3com.cpp

@@ -25,22 +25,22 @@ static void tlb_entry_log_half(mips3_tlb_entry *entry, int tlbindex, int which);
 ***************************************************************************/
 
 /*-------------------------------------------------
-    tlb_entry_matches_asid - TRUE if the given
+    tlb_entry_matches_asid - true if the given
     TLB entry matches the provided ASID
 -------------------------------------------------*/
 
-static inline int tlb_entry_matches_asid(const mips3_tlb_entry *entry, uint8_t asid)
+static inline bool tlb_entry_matches_asid(const mips3_tlb_entry *entry, uint8_t asid)
 {
 	return (entry->entry_hi & 0xff) == asid;
 }
 
 
 /*-------------------------------------------------
-    tlb_entry_is_global - TRUE if the given
+    tlb_entry_is_global - true if the given
     TLB entry is global
 -------------------------------------------------*/
 
-static inline int tlb_entry_is_global(const mips3_tlb_entry *entry)
+static inline bool tlb_entry_is_global(const mips3_tlb_entry *entry)
 {
 	return (entry->entry_lo[0] & entry->entry_lo[1] & TLB_GLOBAL);
 }

src/devices/cpu/powerpc/ppc.h

@@ -588,7 +588,7 @@ protected:
 	{
 		offs_t              start;                      /* start of the RAM block */
 		offs_t              end;                        /* end of the RAM block */
-		uint8_t               readonly;                   /* TRUE if read-only */
+		bool                readonly;                   /* true if read-only */
 		void *              base;                       /* base in memory where the RAM lives */
 	};
 
@@ -629,9 +629,9 @@ protected:
 	void ppc4xx_set_irq_line(uint32_t bitmask, int state);
 	int ppc4xx_get_irq_line(uint32_t bitmask);
 	void ppc4xx_dma_update_irq_states();
-	int ppc4xx_dma_decrement_count(int dmachan);
+	bool ppc4xx_dma_decrement_count(int dmachan);
-	int ppc4xx_dma_fetch_transmit_byte(int dmachan, uint8_t *byte);
+	bool ppc4xx_dma_fetch_transmit_byte(int dmachan, uint8_t *byte);
-	int ppc4xx_dma_handle_receive_byte(int dmachan, uint8_t byte);
+	bool ppc4xx_dma_handle_receive_byte(int dmachan, uint8_t byte);
 	void ppc4xx_dma_exec(int dmachan);
 	void ppc4xx_spu_update_irq_states();
 	void ppc4xx_spu_rx_data(uint8_t data);
@@ -656,7 +656,7 @@ protected:
 	void static_generate_lsw_entries(int mode);
 	void static_generate_stsw_entries(int mode);
 	void generate_update_mode(drcuml_block *block);
-	void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
+	void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception);
 	void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
 	void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
 	void generate_compute_flags(drcuml_block *block, const opcode_desc *desc, int updatecr, uint32_t xermask, int invertcarry);
@@ -664,11 +664,11 @@ protected:
 	void generate_fp_flags(drcuml_block *block, const opcode_desc *desc, int updatefprf);
 	void generate_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, int source, uint8_t link);
 	void generate_branch_bo(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t bo, uint32_t bi, int source, int link);
-	int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
-	int generate_instruction_13(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_instruction_13(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
-	int generate_instruction_1f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_instruction_1f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
-	int generate_instruction_3b(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_instruction_3b(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
-	int generate_instruction_3f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_instruction_3f(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
 	void log_add_disasm_comment(drcuml_block *block, uint32_t pc, uint32_t op);
 	const char *log_desc_flags_to_string(uint32_t flags);
 	void log_register_list(drcuml_state *drcuml, const char *string, const uint32_t *reglist, const uint32_t *regnostarlist);

src/devices/cpu/powerpc/ppccom.cpp

@@ -311,10 +311,10 @@ ppc405gp_device::ppc405gp_device(const machine_config &mconfig, const char *tag,
     of access and the protection bits
 -------------------------------------------------*/
 
-static inline int page_access_allowed(int transtype, uint8_t key, uint8_t protbits)
+static inline bool page_access_allowed(int transtype, uint8_t key, uint8_t protbits)
 {
 	if (key == 0)
-		return (transtype == TRANSLATE_WRITE) ? (protbits != 3) : TRUE;
+		return (transtype == TRANSLATE_WRITE) ? (protbits != 3) : true;
 	else
 		return (transtype == TRANSLATE_WRITE) ? (protbits == 2) : (protbits != 0);
 }
@@ -968,7 +968,7 @@ void ppc_device::device_start()
 	}
 
 	/* mark the cache dirty so it is updated on next execute */
-	m_cache_dirty = TRUE;
+	m_cache_dirty = true;
 }
 
 void ppc_device::state_export(const device_state_entry &entry)
@@ -1223,7 +1223,7 @@ void ppc_device::device_reset()
 
 	/* Mark the cache dirty */
 	m_core->mode = 0;
-	m_cache_dirty = TRUE;
+	m_cache_dirty = true;
 }
 
 
@@ -1465,7 +1465,7 @@ bool ppc_device::memory_translate(address_spacenum spacenum, int intention, offs
 {
 	/* only applies to the program address space */
 	if (spacenum != AS_PROGRAM)
-		return TRUE;
+		return true;
 
 	/* translation is successful if the internal routine returns 0 or 1 */
 	return (ppccom_translate_address_internal(intention, address) <= 1);
@@ -1803,9 +1803,9 @@ void ppc_device::ppccom_execute_mtspr()
 			case SPR4XX_TCR:
 				m_core->spr[SPR4XX_TCR] = m_core->param1 | (oldval & PPC4XX_TCR_WRC_MASK);
 				if ((oldval ^ m_core->spr[SPR4XX_TCR]) & PPC4XX_TCR_FIE)
-					ppc4xx_fit_callback(nullptr, FALSE);
+					ppc4xx_fit_callback(nullptr, false);
 				if ((oldval ^ m_core->spr[SPR4XX_TCR]) & PPC4XX_TCR_PIE)
-					ppc4xx_pit_callback(nullptr, FALSE);
+					ppc4xx_pit_callback(nullptr, false);
 				return;
 
 			/* timer status register */
@@ -1818,7 +1818,7 @@ void ppc_device::ppccom_execute_mtspr()
 			case SPR4XX_PIT:
 				m_core->spr[SPR4XX_PIT] = m_core->param1;
 				m_pit_reload = m_core->param1;
-				ppc4xx_pit_callback(nullptr, FALSE);
+				ppc4xx_pit_callback(nullptr, false);
 				return;
 
 			/* timebase */
@@ -2150,9 +2150,9 @@ void ppc_device::ppc4xx_set_irq_line(uint32_t bitmask, int state)
 	/* update the IRQ status */
 	m_core->irq_pending = ((m_dcr[DCR4XX_EXISR] & m_dcr[DCR4XX_EXIER]) != 0);
 	if ((m_core->spr[SPR4XX_TCR] & PPC4XX_TCR_FIE) && (m_core->spr[SPR4XX_TSR] & PPC4XX_TSR_FIS))
-		m_core->irq_pending = TRUE;
+		m_core->irq_pending = true;
 	if ((m_core->spr[SPR4XX_TCR] & PPC4XX_TCR_PIE) && (m_core->spr[SPR4XX_TSR] & PPC4XX_TSR_PIS))
-		m_core->irq_pending = TRUE;
+		m_core->irq_pending = true;
 }
 
 
@@ -2213,7 +2213,7 @@ void ppc_device::ppc4xx_dma_update_irq_states()
     to do so
 -------------------------------------------------*/
 
-int ppc_device::ppc4xx_dma_decrement_count(int dmachan)
+bool ppc_device::ppc4xx_dma_decrement_count(int dmachan)
 {
 	uint32_t *dmaregs = &m_dcr[8 * dmachan];
 
@@ -2222,7 +2222,7 @@ int ppc_device::ppc4xx_dma_decrement_count(int dmachan)
 
 	/* if non-zero, we keep going */
 	if ((dmaregs[DCR4XX_DMACT0] & 0xffff) != 0)
-		return FALSE;
+		return false;
 
 	// if chained mode
 	if (dmaregs[DCR4XX_DMACR0] & PPC4XX_DMACR_CH)
@@ -2261,9 +2261,9 @@ int ppc_device::ppc4xx_dma_decrement_count(int dmachan)
 	//  m_dcr[DCR4XX_DMASR] |= 1 << (27 - dmachan);
 		ppc4xx_dma_update_irq_states();
 
-		m_buffered_dma_timer[dmachan]->adjust(attotime::never, FALSE);
+		m_buffered_dma_timer[dmachan]->adjust(attotime::never, false);
 	}
-	return TRUE;
+	return true;
 }
 
 
@@ -2376,22 +2376,22 @@ TIMER_CALLBACK_MEMBER( ppc_device::ppc4xx_buffered_dma_callback )
     to send to a peripheral
 -------------------------------------------------*/
 
-int ppc_device::ppc4xx_dma_fetch_transmit_byte(int dmachan, uint8_t *byte)
+bool ppc_device::ppc4xx_dma_fetch_transmit_byte(int dmachan, uint8_t *byte)
 {
 	uint32_t *dmaregs = &m_dcr[8 * dmachan];
 
 	/* if the channel is not enabled, fail */
 	if (!(dmaregs[DCR4XX_DMACR0] & PPC4XX_DMACR_CE))
-		return FALSE;
+		return false;
 
 	/* if no transfers remaining, fail */
 	if ((dmaregs[DCR4XX_DMACT0] & 0xffff) == 0)
-		return FALSE;
+		return false;
 
 	/* fetch the data */
 	*byte = m_program->read_byte(dmaregs[DCR4XX_DMADA0]++);
 	ppc4xx_dma_decrement_count(dmachan);
-	return TRUE;
+	return true;
 }
 
 
@@ -2400,22 +2400,22 @@ int ppc_device::ppc4xx_dma_fetch_transmit_byte(int dmachan, uint8_t *byte)
     transmitted by a peripheral
 -------------------------------------------------*/
 
-int ppc_device::ppc4xx_dma_handle_receive_byte(int dmachan, uint8_t byte)
+bool ppc_device::ppc4xx_dma_handle_receive_byte(int dmachan, uint8_t byte)
 {
 	uint32_t *dmaregs = &m_dcr[8 * dmachan];
 
 	/* if the channel is not enabled, fail */
 	if (!(dmaregs[DCR4XX_DMACR0] & PPC4XX_DMACR_CE))
-		return FALSE;
+		return false;
 
 	/* if no transfers remaining, fail */
 	if ((dmaregs[DCR4XX_DMACT0] & 0xffff) == 0)
-		return FALSE;
+		return false;
 
 	/* store the data */
 	m_program->write_byte(dmaregs[DCR4XX_DMADA0]++, byte);
 	ppc4xx_dma_decrement_count(dmachan);
-	return TRUE;
+	return true;
 }
 
 
@@ -2551,12 +2551,12 @@ TIMER_CALLBACK_MEMBER( ppc_device::ppc4xx_fit_callback )
 		uint32_t timebase = get_timebase();
 		uint32_t interval = 0x200 << (4 * ((m_core->spr[SPR4XX_TCR] & PPC4XX_TCR_FP_MASK) >> 24));
 		uint32_t target = (timebase + interval) & ~(interval - 1);
-		m_fit_timer->adjust(cycles_to_attotime((target + 1 - timebase) / m_tb_divisor), TRUE);
+		m_fit_timer->adjust(cycles_to_attotime((target + 1 - timebase) / m_tb_divisor), true);
 	}
 
 	/* otherwise, turn ourself off */
 	else
-		m_fit_timer->adjust(attotime::never, FALSE);
+		m_fit_timer->adjust(attotime::never, false);
 }
 
 
@@ -2580,12 +2580,12 @@ TIMER_CALLBACK_MEMBER( ppc_device::ppc4xx_pit_callback )
 		uint32_t timebase = get_timebase();
 		uint32_t interval = m_pit_reload;
 		uint32_t target = timebase + interval;
-		m_pit_timer->adjust(cycles_to_attotime((target + 1 - timebase) / m_tb_divisor), TRUE);
+		m_pit_timer->adjust(cycles_to_attotime((target + 1 - timebase) / m_tb_divisor), true);
 	}
 
 	/* otherwise, turn ourself off */
 	else
-		m_pit_timer->adjust(attotime::never, FALSE);
+		m_pit_timer->adjust(attotime::never, false);
 }
 
 

src/devices/cpu/rsp/rsp.cpp

@@ -106,7 +106,7 @@ rsp_device::rsp_device(const machine_config &mconfig, const char *tag, device_t
 //  , m_drcuml(*this, m_cache, 0, 8, 32, 2)
 	, m_drcfe(nullptr)
 	, m_drcoptions(0)
-	, m_cache_dirty(TRUE)
+	, m_cache_dirty(true)
 	, m_numcycles(0)
 	, m_format(nullptr)
 	, m_arg2(0)
@@ -420,7 +420,7 @@ void rsp_device::device_start()
 	}
 
 	/* mark the cache dirty so it is updated on next execute */
-	m_cache_dirty = TRUE;
+	m_cache_dirty = true;
 
 	state_add( RSP_PC,      "PC", m_debugger_temp).callimport().callexport().formatstr("%08X");
 	state_add( RSP_R0,      "R0", m_rsp_state->r[0]).formatstr("%08X");

src/devices/cpu/rsp/rsp.h

@@ -210,7 +210,7 @@ private:
 	{
 		offs_t              start;                      /* start of the RAM block */
 		offs_t              end;                        /* end of the RAM block */
-		uint8_t               readonly;                   /* TRUE if read-only */
+		bool                readonly;                   /* true if read-only */
 		void *              base;                       /* base in memory where the RAM lives */
 	};
 
@@ -311,15 +311,15 @@ private:
 	void static_generate_nocode_handler();
 	void static_generate_out_of_cycles();
 	void static_generate_memory_accessor(int size, int iswrite, const char *name, uml::code_handle *&handleptr);
-	void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
+	void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception);
 	void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
 	void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
 	void generate_delay_slot_and_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint8_t linkreg);
 	void generate_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
-	int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
-	int generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
-	int generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
-	int generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
 	void log_add_disasm_comment(drcuml_block *block, uint32_t pc, uint32_t op);
 };
 

src/devices/cpu/rsp/rspcp2.h

@@ -85,9 +85,9 @@ protected:
 	virtual void init();
 	virtual void start();
 
-	virtual int generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return TRUE; }
+	virtual bool generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return true; }
-	virtual int generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return TRUE; }
+	virtual bool generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return true; }
-	virtual int generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return TRUE; }
+	virtual bool generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return true; }
 
 	virtual void state_string_export(const int index, std::string &str) const;
 
@@ -172,7 +172,7 @@ public:
 	void            dump_dmem();
 
 protected:
-	virtual int     generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return TRUE; }
+	virtual bool     generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) { return true; }
 
 	uint16_t          SATURATE_ACCUM(int accum, int slice, uint16_t negative, uint16_t positive);
 

src/devices/cpu/rsp/rspcp2d.cpp

@@ -707,7 +707,7 @@ static void cfunc_ltv(void *param)
 }
 
 
-int rsp_cop2_drc::generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
+bool rsp_cop2_drc::generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
 {
 	uint32_t op = desc->opptr.l[0];
 	int offset = (op & 0x7f);
@@ -721,65 +721,65 @@ int rsp_cop2_drc::generate_lwc2(drcuml_block *block, rsp_device::compiler_state
 		case 0x00:      /* LBV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [m_rspcop2_state->op],desc->opptr.l
 			UML_CALLC(block, cfunc_lbv, this);
-			return TRUE;
+			return true;
 
 		case 0x01:      /* LSV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [m_rspcop2_state->op],desc->opptr.l
 			UML_CALLC(block, cfunc_lsv, this);
-			return TRUE;
+			return true;
 
 		case 0x02:      /* LLV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [m_rspcop2_state->op],desc->opptr.l
 			UML_CALLC(block, cfunc_llv, this);
-			return TRUE;
+			return true;
 
 		case 0x03:      /* LDV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [m_rspcop2_state->op],desc->opptr.l
 			UML_CALLC(block, cfunc_ldv, this);
-			return TRUE;
+			return true;
 
 		case 0x04:      /* LQV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [m_rspcop2_state->op],desc->opptr.l
 			UML_CALLC(block, cfunc_lqv, this);
-			return TRUE;
+			return true;
 
 		case 0x05:      /* LRV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [m_rspcop2_state->op],desc->opptr.l
 			UML_CALLC(block, cfunc_lrv, this);
-			return TRUE;
+			return true;
 
 		case 0x06:      /* LPV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [m_rspcop2_state->op],desc->opptr.l
 			UML_CALLC(block, cfunc_lpv, this);
-			return TRUE;
+			return true;
 
 		case 0x07:      /* LUV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [m_rspcop2_state->op],desc->opptr.l
 			UML_CALLC(block, cfunc_luv, this);
-			return TRUE;
+			return true;
 
 		case 0x08:      /* LHV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [m_rspcop2_state->op],desc->opptr.l
 			UML_CALLC(block, cfunc_lhv, this);
-			return TRUE;
+			return true;
 
 		case 0x09:      /* LFV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [m_rspcop2_state->op],desc->opptr.l
 			UML_CALLC(block, cfunc_lfv, this);
-			return TRUE;
+			return true;
 
 		case 0x0a:      /* LWV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [m_rspcop2_state->op],desc->opptr.l
 			UML_CALLC(block, cfunc_lwv, this);
-			return TRUE;
+			return true;
 
 		case 0x0b:      /* LTV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [m_rspcop2_state->op],desc->opptr.l
 			UML_CALLC(block, cfunc_ltv, this);
-			return TRUE;
+			return true;
 
 		default:
-			return FALSE;
+			return false;
 	}
 }
 
@@ -1257,7 +1257,7 @@ static void cfunc_stv(void *param)
 	((rsp_cop2 *)param)->stv();
 }
 
-int rsp_cop2_drc::generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
+bool rsp_cop2_drc::generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
 {
 	uint32_t op = desc->opptr.l[0];
 	int offset = (op & 0x7f);
@@ -1271,69 +1271,69 @@ int rsp_cop2_drc::generate_swc2(drcuml_block *block, rsp_device::compiler_state
 		case 0x00:      /* SBV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_sbv, this);
-			return TRUE;
+			return true;
 
 		case 0x01:      /* SSV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_ssv, this);
-			return TRUE;
+			return true;
 
 		case 0x02:      /* SLV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_slv, this);
-			return TRUE;
+			return true;
 
 		case 0x03:      /* SDV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_sdv, this);
-			return TRUE;
+			return true;
 
 		case 0x04:      /* SQV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_sqv, this);
-			return TRUE;
+			return true;
 
 		case 0x05:      /* SRV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_srv, this);
-			return TRUE;
+			return true;
 
 		case 0x06:      /* SPV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_spv, this);
-			return TRUE;
+			return true;
 
 		case 0x07:      /* SUV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_suv, this);
-			return TRUE;
+			return true;
 
 		case 0x08:      /* SHV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_shv, this);
-			return TRUE;
+			return true;
 
 		case 0x09:      /* SFV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_sfv, this);
-			return TRUE;
+			return true;
 
 		case 0x0a:      /* SWV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_swv, this);
-			return TRUE;
+			return true;
 
 		case 0x0b:      /* STV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_stv, this);
-			return TRUE;
+			return true;
 
 		default:
 			m_rsp.unimplemented_opcode(op);
-			return FALSE;
+			return false;
 	}
 
-	return TRUE;
+	return true;
 }
 
 
@@ -3251,7 +3251,7 @@ static void cfunc_vrsqh(void *param)
     vector opcode
 -------------------------------------------------*/
 
-int rsp_cop2_drc::generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
+bool rsp_cop2_drc::generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
 {
 	uint32_t op = desc->opptr.l[0];
 	// Opcode legend:
@@ -3265,226 +3265,226 @@ int rsp_cop2_drc::generate_vector_opcode(drcuml_block *block, rsp_device::compil
 		case 0x00:      /* VMULF */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vmulf, this);
-			return TRUE;
+			return true;
 
 		case 0x01:      /* VMULU */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vmulu, this);
-			return TRUE;
+			return true;
 
 		case 0x04:      /* VMUDL */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vmudl, this);
-			return TRUE;
+			return true;
 
 		case 0x05:      /* VMUDM */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vmudm, this);
-			return TRUE;
+			return true;
 
 		case 0x06:      /* VMUDN */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vmudn, this);
-			return TRUE;
+			return true;
 
 		case 0x07:      /* VMUDH */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vmudh, this);
-			return TRUE;
+			return true;
 
 		case 0x08:      /* VMACF */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vmacf, this);
-			return TRUE;
+			return true;
 
 		case 0x09:      /* VMACU */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vmacu, this);
-			return TRUE;
+			return true;
 
 		case 0x0c:      /* VMADL */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vmadl, this);
-			return TRUE;
+			return true;
 
 		case 0x0d:      /* VMADM */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vmadm, this);
-			return TRUE;
+			return true;
 
 		case 0x0e:      /* VMADN */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vmadn, this);
-			return TRUE;
+			return true;
 
 		case 0x0f:      /* VMADH */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vmadh, this);
-			return TRUE;
+			return true;
 
 		case 0x10:      /* VADD */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vadd, this);
-			return TRUE;
+			return true;
 
 		case 0x11:      /* VSUB */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vsub, this);
-			return TRUE;
+			return true;
 
 		case 0x13:      /* VABS */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vabs, this);
-			return TRUE;
+			return true;
 
 		case 0x14:      /* VADDC */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vaddc, this);
-			return TRUE;
+			return true;
 
 		case 0x15:      /* VSUBC */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vsubc, this);
-			return TRUE;
+			return true;
 
 		case 0x16:      /* VADDB */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vaddb, this);
-			return TRUE;
+			return true;
 
 		case 0x17:      /* VSUBB (reserved, functionally identical to VADDB) */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vaddb, this);
-			return TRUE;
+			return true;
 
 		case 0x18:      /* VACCB (reserved, functionally identical to VADDB) */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vaddb, this);
-			return TRUE;
+			return true;
 
 		case 0x19:      /* VSUCB (reserved, functionally identical to VADDB) */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vaddb, this);
-			return TRUE;
+			return true;
 
 		case 0x1d:      /* VSAW */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vsaw, this);
-			return TRUE;
+			return true;
 
 		case 0x20:      /* VLT */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vlt, this);
-			return TRUE;
+			return true;
 
 		case 0x21:      /* VEQ */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_veq, this);
-			return TRUE;
+			return true;
 
 		case 0x22:      /* VNE */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vne, this);
-			return TRUE;
+			return true;
 
 		case 0x23:      /* VGE */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vge, this);
-			return TRUE;
+			return true;
 
 		case 0x24:      /* VCL */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vcl, this);
-			return TRUE;
+			return true;
 
 		case 0x25:      /* VCH */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vch, this);
-			return TRUE;
+			return true;
 
 		case 0x26:      /* VCR */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vcr, this);
-			return TRUE;
+			return true;
 
 		case 0x27:      /* VMRG */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vmrg, this);
-			return TRUE;
+			return true;
 
 		case 0x28:      /* VAND */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vand, this);
-			return TRUE;
+			return true;
 
 		case 0x29:      /* VNAND */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vnand, this);
-			return TRUE;
+			return true;
 
 		case 0x2a:      /* VOR */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vor, this);
-			return TRUE;
+			return true;
 
 		case 0x2b:      /* VNOR */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vnor, this);
-			return TRUE;
+			return true;
 
 		case 0x2c:      /* VXOR */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vxor, this);
-			return TRUE;
+			return true;
 
 		case 0x2d:      /* VNXOR */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vnxor, this);
-			return TRUE;
+			return true;
 
 		case 0x30:      /* VRCP */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vrcp, this);
-			return TRUE;
+			return true;
 
 		case 0x31:      /* VRCPL */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vrcpl, this);
-			return TRUE;
+			return true;
 
 		case 0x32:      /* VRCPH */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vrcph, this);
-			return TRUE;
+			return true;
 
 		case 0x33:      /* VMOV */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vmov, this);
-			return TRUE;
+			return true;
 
 		case 0x34:      /* VRSQ */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);         // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vrsq, this);
-			return TRUE;
+			return true;
 
 		case 0x35:      /* VRSQL */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vrsql, this);
-			return TRUE;
+			return true;
 
 		case 0x36:      /* VRSQH */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_vrsqh, this);
-			return TRUE;
+			return true;
 
 		case 0x37:      /* VNOP */
 		case 0x3F:      /* VNULL */
-			return TRUE;
+			return true;
 
 		default:
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);        // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, unimplemented_opcode, &m_rsp);
-			return FALSE;
+			return false;
 	}
 }
 
@@ -3695,7 +3695,7 @@ static void cfunc_ctc2(void *param)
     COP2 Opcode Compilation
 ***************************************************************************/
 
-int rsp_cop2_drc::generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
+bool rsp_cop2_drc::generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc)
 {
 	uint32_t op = desc->opptr.l[0];
 	uint8_t opswitch = RSREG;
@@ -3708,7 +3708,7 @@ int rsp_cop2_drc::generate_cop2(drcuml_block *block, rsp_device::compiler_state
 				UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);   // mov     [arg0],desc->opptr.l
 				UML_CALLC(block, cfunc_mfc2, this);             // callc   mfc2
 			}
-			return TRUE;
+			return true;
 
 		case 0x02:  /* CFCz */
 			if (RTREG != 0)
@@ -3716,21 +3716,21 @@ int rsp_cop2_drc::generate_cop2(drcuml_block *block, rsp_device::compiler_state
 				UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);   // mov     [arg0],desc->opptr.l
 				UML_CALLC(block, cfunc_cfc2, this);             // callc   cfc2
 			}
-			return TRUE;
+			return true;
 
 		case 0x04:  /* MTCz */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);   // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_mtc2, this);             // callc   mtc2
-			return TRUE;
+			return true;
 
 		case 0x06:  /* CTCz */
 			UML_MOV(block, mem(&m_rspcop2_state->op), desc->opptr.l[0]);   // mov     [arg0],desc->opptr.l
 			UML_CALLC(block, cfunc_ctc2, this);             // callc   ctc2
-			return TRUE;
+			return true;
 
 		case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
 		case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
 			return generate_vector_opcode(block, compiler, desc);
 	}
-	return FALSE;
+	return false;
 }

src/devices/cpu/rsp/rspcp2d.h

@@ -24,9 +24,9 @@ class rsp_cop2_drc : public rsp_cop2
 public:
 	rsp_cop2_drc(rsp_device &rsp, running_machine &machine) : rsp_cop2(rsp, machine) { }
 private:
-	virtual int generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
+	virtual bool generate_cop2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
-	virtual int generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
+	virtual bool generate_lwc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
-	virtual int generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
+	virtual bool generate_swc2(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
 
 	virtual void state_string_export(const int index, std::string &str) const override;
 
@@ -103,7 +103,7 @@ public:
 	virtual void ctc2() override;
 
 private:
-	virtual int     generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
+	virtual bool generate_vector_opcode(drcuml_block *block, rsp_device::compiler_state *compiler, const opcode_desc *desc) override;
 };
 
 #endif /* __RSPCP2D_H__ */

src/devices/cpu/rsp/rspdrc.cpp

@@ -266,7 +266,7 @@ void rsp_device::execute_run_drc()
 	/* reset the cache if dirty */
 	if (m_cache_dirty)
 		code_flush_cache();
-	m_cache_dirty = FALSE;
+	m_cache_dirty = false;
 
 	/* execute */
 	do
@@ -308,7 +308,7 @@ void rsp_device::execute_run_drc()
 void rsp_device::rspdrc_flush_drc_cache()
 {
 	if (!allow_drc()) return;
-	m_cache_dirty = TRUE;
+	m_cache_dirty = true;
 }
 
 /*-------------------------------------------------
@@ -329,12 +329,12 @@ void rsp_device::code_flush_cache()
 		static_generate_out_of_cycles();
 
 		/* add subroutines for memory accesses */
-		static_generate_memory_accessor(1, FALSE, "read8",       m_read8);
+		static_generate_memory_accessor(1, false, "read8",       m_read8);
-		static_generate_memory_accessor(1, TRUE,  "write8",      m_write8);
+		static_generate_memory_accessor(1, true,  "write8",      m_write8);
-		static_generate_memory_accessor(2, FALSE, "read16",      m_read16);
+		static_generate_memory_accessor(2, false, "read16",      m_read16);
-		static_generate_memory_accessor(2, TRUE,  "write16",     m_write16);
+		static_generate_memory_accessor(2, true,  "write16",     m_write16);
-		static_generate_memory_accessor(4, FALSE, "read32",      m_read32);
+		static_generate_memory_accessor(4, false, "read32",      m_read32);
-		static_generate_memory_accessor(4, TRUE,  "write32",     m_write32);
+		static_generate_memory_accessor(4, true,  "write32",     m_write32);
 	}
 	catch (drcuml_block::abort_compilation &)
 	{
@@ -354,7 +354,7 @@ void rsp_device::code_compile_block(offs_t pc)
 	compiler_state compiler = { 0 };
 	const opcode_desc *seqhead, *seqlast;
 	const opcode_desc *desclist;
-	int override = FALSE;
+	int override = false;
 	drcuml_block *block;
 
 	g_profiler.start(PROFILER_DRC_COMPILE);
@@ -394,7 +394,7 @@ void rsp_device::code_compile_block(offs_t pc)
 				/* are recompiling due to being out of sync and allow future overrides */
 				else if (seqhead == desclist)
 				{
-					override = TRUE;
+					override = true;
 					UML_HASH(block, 0, seqhead->pc);                                        // hash    mode,pc
 				}
 
@@ -428,7 +428,7 @@ void rsp_device::code_compile_block(offs_t pc)
 					nextpc = seqlast->pc + (seqlast->skipslots + 1) * 4;
 
 				/* count off cycles and go there */
-				generate_update_cycles(block, &compiler, nextpc, TRUE);            // <subtract cycles>
+				generate_update_cycles(block, &compiler, nextpc, true);            // <subtract cycles>
 
 				/* if the last instruction can change modes, use a variable mode; otherwise, assume the same mode */
 				if (seqlast->next() == nullptr || seqlast->next()->pc != nextpc)
@@ -638,7 +638,7 @@ void rsp_device::static_generate_memory_accessor(int size, int iswrite, const ch
     subtract cycles from the icount and generate
     an exception if out
 -------------------------------------------------*/
-void rsp_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception)
+void rsp_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception)
 {
 	/* account for cycles */
 	if (compiler->cycles > 0)
@@ -783,7 +783,7 @@ void rsp_device::generate_branch(drcuml_block *block, compiler_state *compiler,
 	/* update the cycles and jump through the hash table to the target */
 	if (desc->targetpc != BRANCH_TARGET_DYNAMIC)
 	{
-		generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE);    // <subtract cycles>
+		generate_update_cycles(block, &compiler_temp, desc->targetpc, true);    // <subtract cycles>
 		if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
 			UML_JMP(block, desc->targetpc | 0x80000000);                        // jmp     desc->targetpc
 		else
@@ -791,7 +791,7 @@ void rsp_device::generate_branch(drcuml_block *block, compiler_state *compiler,
 	}
 	else
 	{
-		generate_update_cycles(block, &compiler_temp, mem(&m_rsp_state->jmpdest), TRUE);    // <subtract cycles>
+		generate_update_cycles(block, &compiler_temp, mem(&m_rsp_state->jmpdest), true);    // <subtract cycles>
 		UML_HASHJMP(block, 0, mem(&m_rsp_state->jmpdest), *m_nocode);                       // hashjmp <mode>,<rsreg>,nocode
 	}
 }
@@ -832,7 +832,7 @@ void rsp_device::generate_delay_slot_and_branch(drcuml_block *block, compiler_st
 	UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles);                             // mapvar  CYCLES,compiler->cycles
 }
 
-int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
 {
 	int in_delay_slot = ((desc->flags & OPFLAG_IN_DELAY_SLOT) != 0);
 	uint32_t op = desc->opptr.l[0];
@@ -853,25 +853,25 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
 
 		case 0x02:  /* J - MIPS I */
 			generate_delay_slot_and_branch(block, compiler, desc, 0);      // <next instruction + hashjmp>
-			return TRUE;
+			return true;
 
 		case 0x03:  /* JAL - MIPS I */
 			generate_delay_slot_and_branch(block, compiler, desc, 31);     // <next instruction + hashjmp>
-			return TRUE;
+			return true;
 
 		case 0x04:  /* BEQ - MIPS I */
 			UML_CMP(block, R32(RSREG), R32(RTREG));                             // cmp    <rsreg>,<rtreg>
 			UML_JMPc(block, COND_NE, skip = compiler->labelnum++);              // jmp    skip,NE
 			generate_delay_slot_and_branch(block, compiler, desc, 0);      // <next instruction + hashjmp>
 			UML_LABEL(block, skip);                                             // skip:
-			return TRUE;
+			return true;
 
 		case 0x05:  /* BNE - MIPS I */
 			UML_CMP(block, R32(RSREG), R32(RTREG));                             // dcmp    <rsreg>,<rtreg>
 			UML_JMPc(block, COND_E, skip = compiler->labelnum++);                       // jmp     skip,E
 			generate_delay_slot_and_branch(block, compiler, desc, 0);      // <next instruction + hashjmp>
 			UML_LABEL(block, skip);                                             // skip:
-			return TRUE;
+			return true;
 
 		case 0x06:  /* BLEZ - MIPS I */
 			if (RSREG != 0)
@@ -883,14 +883,14 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
 			}
 			else
 				generate_delay_slot_and_branch(block, compiler, desc, 0);  // <next instruction + hashjmp>
-			return TRUE;
+			return true;
 
 		case 0x07:  /* BGTZ - MIPS I */
 			UML_CMP(block, R32(RSREG), 0);                                  // dcmp    <rsreg>,0
 			UML_JMPc(block, COND_LE, skip = compiler->labelnum++);                  // jmp     skip,LE
 			generate_delay_slot_and_branch(block, compiler, desc, 0);      // <next instruction + hashjmp>
 			UML_LABEL(block, skip);                                             // skip:
-			return TRUE;
+			return true;
 
 
 		/* ----- immediate arithmetic ----- */
@@ -898,7 +898,7 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
 		case 0x0f:  /* LUI - MIPS I */
 			if (RTREG != 0)
 				UML_MOV(block, R32(RTREG), SIMMVAL << 16);                  // dmov    <rtreg>,SIMMVAL << 16
-			return TRUE;
+			return true;
 
 		case 0x08:  /* ADDI - MIPS I */
 		case 0x09:  /* ADDIU - MIPS I */
@@ -906,7 +906,7 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
 			{
 				UML_ADD(block, R32(RTREG), R32(RSREG), SIMMVAL);                // add     i0,<rsreg>,SIMMVAL,V
 			}
-			return TRUE;
+			return true;
 
 		case 0x0a:  /* SLTI - MIPS I */
 			if (RTREG != 0)
@@ -914,7 +914,7 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
 				UML_CMP(block, R32(RSREG), SIMMVAL);                            // dcmp    <rsreg>,SIMMVAL
 				UML_SETc(block, COND_L, R32(RTREG));                                    // dset    <rtreg>,l
 			}
-			return TRUE;
+			return true;
 
 		case 0x0b:  /* SLTIU - MIPS I */
 			if (RTREG != 0)
@@ -922,23 +922,23 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
 				UML_CMP(block, R32(RSREG), SIMMVAL);                            // dcmp    <rsreg>,SIMMVAL
 				UML_SETc(block, COND_B, R32(RTREG));                                    // dset    <rtreg>,b
 			}
-			return TRUE;
+			return true;
 
 
 		case 0x0c:  /* ANDI - MIPS I */
 			if (RTREG != 0)
 				UML_AND(block, R32(RTREG), R32(RSREG), UIMMVAL);                // dand    <rtreg>,<rsreg>,UIMMVAL
-			return TRUE;
+			return true;
 
 		case 0x0d:  /* ORI - MIPS I */
 			if (RTREG != 0)
 				UML_OR(block, R32(RTREG), R32(RSREG), UIMMVAL);             // dor     <rtreg>,<rsreg>,UIMMVAL
-			return TRUE;
+			return true;
 
 		case 0x0e:  /* XORI - MIPS I */
 			if (RTREG != 0)
 				UML_XOR(block, R32(RTREG), R32(RSREG), UIMMVAL);                // dxor    <rtreg>,<rsreg>,UIMMVAL
-			return TRUE;
+			return true;
 
 		/* ----- memory load operations ----- */
 
@@ -948,8 +948,8 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
 			if (RTREG != 0)
 				UML_SEXT(block, R32(RTREG), I0, SIZE_BYTE);                     // dsext   <rtreg>,i0,byte
 			if (!in_delay_slot)
-				generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
+				generate_update_cycles(block, compiler, desc->pc + 4, true);
-			return TRUE;
+			return true;
 
 		case 0x21:  /* LH - MIPS I */
 			UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
@@ -957,8 +957,8 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
 			if (RTREG != 0)
 				UML_SEXT(block, R32(RTREG), I0, SIZE_WORD);                     // dsext   <rtreg>,i0,word
 			if (!in_delay_slot)
-				generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
+				generate_update_cycles(block, compiler, desc->pc + 4, true);
-			return TRUE;
+			return true;
 
 		case 0x23:  /* LW - MIPS I */
 			UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
@@ -966,8 +966,8 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
 			if (RTREG != 0)
 				UML_MOV(block, R32(RTREG), I0);
 			if (!in_delay_slot)
-				generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
+				generate_update_cycles(block, compiler, desc->pc + 4, true);
-			return TRUE;
+			return true;
 
 		case 0x24:  /* LBU - MIPS I */
 			UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
@@ -975,8 +975,8 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
 			if (RTREG != 0)
 				UML_AND(block, R32(RTREG), I0, 0xff);                   // dand    <rtreg>,i0,0xff
 			if (!in_delay_slot)
-				generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
+				generate_update_cycles(block, compiler, desc->pc + 4, true);
-			return TRUE;
+			return true;
 
 		case 0x25:  /* LHU - MIPS I */
 			UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
@@ -984,8 +984,8 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
 			if (RTREG != 0)
 				UML_AND(block, R32(RTREG), I0, 0xffff);                 // dand    <rtreg>,i0,0xffff
 			if (!in_delay_slot)
-				generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
+				generate_update_cycles(block, compiler, desc->pc + 4, true);
-			return TRUE;
+			return true;
 
 		case 0x32:  /* LWC2 - MIPS I */
 			return m_cop2->generate_lwc2(block, compiler, desc);
@@ -998,24 +998,24 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
 			UML_MOV(block, I1, R32(RTREG));                                 // mov     i1,<rtreg>
 			UML_CALLH(block, *m_write8);                               // callh   write8
 			if (!in_delay_slot)
-				generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
+				generate_update_cycles(block, compiler, desc->pc + 4, true);
-			return TRUE;
+			return true;
 
 		case 0x29:  /* SH - MIPS I */
 			UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
 			UML_MOV(block, I1, R32(RTREG));                                 // mov     i1,<rtreg>
 			UML_CALLH(block, *m_write16);                              // callh   write16
 			if (!in_delay_slot)
-				generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
+				generate_update_cycles(block, compiler, desc->pc + 4, true);
-			return TRUE;
+			return true;
 
 		case 0x2b:  /* SW - MIPS I */
 			UML_ADD(block, I0, R32(RSREG), SIMMVAL);                        // add     i0,<rsreg>,SIMMVAL
 			UML_MOV(block, I1, R32(RTREG));                                 // mov     i1,<rtreg>
 			UML_CALLH(block, *m_write32);                              // callh   write32
 			if (!in_delay_slot)
-				generate_update_cycles(block, compiler, desc->pc + 4, TRUE);
+				generate_update_cycles(block, compiler, desc->pc + 4, true);
-			return TRUE;
+			return true;
 
 		case 0x3a:  /* SWC2 - MIPS I */
 			return m_cop2->generate_swc2(block, compiler, desc);
@@ -1034,7 +1034,7 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
 		//default:    /* ??? */       invalid_instruction(op);                                                break;
 	}
 
-	return FALSE;
+	return false;
 }
 
 
@@ -1043,7 +1043,7 @@ int rsp_device::generate_opcode(drcuml_block *block, compiler_state *compiler, c
     'SPECIAL' group
 -------------------------------------------------*/
 
-int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool rsp_device::generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
 {
 	uint32_t op = desc->opptr.l[0];
 	uint8_t opswitch = op & 63;
@@ -1058,42 +1058,42 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
 			{
 				UML_SHL(block, R32(RDREG), R32(RTREG), SHIFT);
 			}
-			return TRUE;
+			return true;
 
 		case 0x02:  /* SRL - MIPS I */
 			if (RDREG != 0)
 			{
 				UML_SHR(block, R32(RDREG), R32(RTREG), SHIFT);
 			}
-			return TRUE;
+			return true;
 
 		case 0x03:  /* SRA - MIPS I */
 			if (RDREG != 0)
 			{
 				UML_SAR(block, R32(RDREG), R32(RTREG), SHIFT);
 			}
-			return TRUE;
+			return true;
 
 		case 0x04:  /* SLLV - MIPS I */
 			if (RDREG != 0)
 			{
 				UML_SHL(block, R32(RDREG), R32(RTREG), R32(RSREG));
 			}
-			return TRUE;
+			return true;
 
 		case 0x06:  /* SRLV - MIPS I */
 			if (RDREG != 0)
 			{
 				UML_SHR(block, R32(RDREG), R32(RTREG), R32(RSREG));
 			}
-			return TRUE;
+			return true;
 
 		case 0x07:  /* SRAV - MIPS I */
 			if (RDREG != 0)
 			{
 				UML_SAR(block, R32(RDREG), R32(RTREG), R32(RSREG));
 			}
-			return TRUE;
+			return true;
 
 		/* ----- basic arithmetic ----- */
 
@@ -1103,7 +1103,7 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
 			{
 				UML_ADD(block, R32(RDREG), R32(RSREG), R32(RTREG));
 			}
-			return TRUE;
+			return true;
 
 		case 0x22:  /* SUB - MIPS I */
 		case 0x23:  /* SUBU - MIPS I */
@@ -1111,7 +1111,7 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
 			{
 				UML_SUB(block, R32(RDREG), R32(RSREG), R32(RTREG));
 			}
-			return TRUE;
+			return true;
 
 		/* ----- basic logical ops ----- */
 
@@ -1120,21 +1120,21 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
 			{
 				UML_AND(block, R32(RDREG), R32(RSREG), R32(RTREG));             // dand     <rdreg>,<rsreg>,<rtreg>
 			}
-			return TRUE;
+			return true;
 
 		case 0x25:  /* OR - MIPS I */
 			if (RDREG != 0)
 			{
 				UML_OR(block, R32(RDREG), R32(RSREG), R32(RTREG));                  // dor      <rdreg>,<rsreg>,<rtreg>
 			}
-			return TRUE;
+			return true;
 
 		case 0x26:  /* XOR - MIPS I */
 			if (RDREG != 0)
 			{
 				UML_XOR(block, R32(RDREG), R32(RSREG), R32(RTREG));             // dxor     <rdreg>,<rsreg>,<rtreg>
 			}
-			return TRUE;
+			return true;
 
 		case 0x27:  /* NOR - MIPS I */
 			if (RDREG != 0)
@@ -1142,7 +1142,7 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
 				UML_OR(block, I0, R32(RSREG), R32(RTREG));                  // dor      i0,<rsreg>,<rtreg>
 				UML_XOR(block, R32(RDREG), I0, (uint64_t)~0);             // dxor     <rdreg>,i0,~0
 			}
-			return TRUE;
+			return true;
 
 
 		/* ----- basic comparisons ----- */
@@ -1153,7 +1153,7 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
 				UML_CMP(block, R32(RSREG), R32(RTREG));                         // dcmp    <rsreg>,<rtreg>
 				UML_SETc(block, COND_L, R32(RDREG));                                    // dset    <rdreg>,l
 			}
-			return TRUE;
+			return true;
 
 		case 0x2b:  /* SLTU - MIPS I */
 			if (RDREG != 0)
@@ -1161,18 +1161,18 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
 				UML_CMP(block, R32(RSREG), R32(RTREG));                         // dcmp    <rsreg>,<rtreg>
 				UML_SETc(block, COND_B, R32(RDREG));                                    // dset    <rdreg>,b
 			}
-			return TRUE;
+			return true;
 
 
 		/* ----- jumps and branches ----- */
 
 		case 0x08:  /* JR - MIPS I */
 			generate_delay_slot_and_branch(block, compiler, desc, 0);      // <next instruction + hashjmp>
-			return TRUE;
+			return true;
 
 		case 0x09:  /* JALR - MIPS I */
 			generate_delay_slot_and_branch(block, compiler, desc, RDREG);  // <next instruction + hashjmp>
-			return TRUE;
+			return true;
 
 
 		/* ----- system calls ----- */
@@ -1186,9 +1186,9 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
 			generate_branch(block, compiler, desc);
 
 			UML_EXIT(block, EXECUTE_OUT_OF_CYCLES);
-			return TRUE;
+			return true;
 	}
-	return FALSE;
+	return false;
 }
 
 
@@ -1198,7 +1198,7 @@ int rsp_device::generate_special(drcuml_block *block, compiler_state *compiler,
     'REGIMM' group
 -------------------------------------------------*/
 
-int rsp_device::generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool rsp_device::generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
 {
 	uint32_t op = desc->opptr.l[0];
 	uint8_t opswitch = RTREG;
@@ -1216,7 +1216,7 @@ int rsp_device::generate_regimm(drcuml_block *block, compiler_state *compiler, c
 																					// <next instruction + hashjmp>
 				UML_LABEL(block, skip);                                         // skip:
 			}
-			return TRUE;
+			return true;
 
 		case 0x01:  /* BGEZ */
 		case 0x11:  /* BGEZAL */
@@ -1231,9 +1231,9 @@ int rsp_device::generate_regimm(drcuml_block *block, compiler_state *compiler, c
 			else
 				generate_delay_slot_and_branch(block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
 																					// <next instruction + hashjmp>
-			return TRUE;
+			return true;
 	}
-	return FALSE;
+	return false;
 }
 
 
@@ -1241,7 +1241,7 @@ int rsp_device::generate_regimm(drcuml_block *block, compiler_state *compiler, c
     generate_cop0 - compile COP0 opcodes
 -------------------------------------------------*/
 
-int rsp_device::generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool rsp_device::generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
 {
 	uint32_t op = desc->opptr.l[0];
 	uint8_t opswitch = RSREG;
@@ -1256,20 +1256,20 @@ int rsp_device::generate_cop0(drcuml_block *block, compiler_state *compiler, con
 				UML_CALLC(block, cfunc_get_cop0_reg, this);                          // callc   cfunc_get_cop0_reg
 				if(RDREG == 2)
 				{
-					generate_update_cycles(block, compiler, mem(&m_rsp_state->pc), TRUE);
+					generate_update_cycles(block, compiler, mem(&m_rsp_state->pc), true);
 					UML_HASHJMP(block, 0, mem(&m_rsp_state->pc), *m_nocode);
 				}
 			}
-			return TRUE;
+			return true;
 
 		case 0x04:  /* MTCz */
 			UML_MOV(block, mem(&m_rsp_state->arg0), RDREG);                   // mov     [arg0],<rdreg>
 			UML_MOV(block, mem(&m_rsp_state->arg1), R32(RTREG));                  // mov     [arg1],rtreg
 			UML_CALLC(block, cfunc_set_cop0_reg, this);                              // callc   cfunc_set_cop0_reg
-			return TRUE;
+			return true;
 	}
 
-	return FALSE;
+	return false;
 }
 
 /***************************************************************************

src/devices/cpu/sc61860/sctable.hxx

@@ -50,8 +50,8 @@ void sc61860_device::sc61860_instruction()
 		case 41: sc61860_jump_rel_minus(!m_zero);m_icount-=4;break;
 		case 42: sc61860_jump_rel_plus(!m_carry);m_icount-=4;break;
 		case 43: sc61860_jump_rel_minus(!m_carry);m_icount-=4;break;
-		case 44: sc61860_jump_rel_plus(TRUE);m_icount-=4;break;
+		case 44: sc61860_jump_rel_plus(true);m_icount-=4;break;
-		case 45: sc61860_jump_rel_minus(TRUE);m_icount-=4;break;
+		case 45: sc61860_jump_rel_minus(true);m_icount-=4;break;
 		case 47: sc61860_loop();m_icount-=7;break;
 		case 48: sc61860_load_imm_p(READ_RAM(A));m_icount-=2;break;
 		case 49: sc61860_load_imm_q(READ_RAM(A));m_icount-=2;break;
@@ -78,7 +78,7 @@ void sc61860_device::sc61860_instruction()
 		case 76: sc61860_in_a();m_icount-=2;break;
 		case 77: /*nopw*/;m_icount-=2;break;
 		case 78: sc61860_wait();m_icount-=6;break;
-		case 79: sc61860_wait_x(FALSE);m_icount-=1;break;
+		case 79: sc61860_wait_x(false);m_icount-=1;break;
 		case 80: sc61860_inc_p();m_icount-=2;break;
 		case 81: sc61860_dec_p();m_icount-=2;break;
 		case 82: sc61860_store_ext(A);m_icount-=2;break;
@@ -103,7 +103,7 @@ void sc61860_device::sc61860_instruction()
 		case 103: sc61860_cmp(A, READ_OP());m_icount-=4;break;
 		case 105: sc61860_execute_table_call();m_icount-=3;break;
 		case 107: sc61860_test_special();m_icount-=4;break;
-		case 111: sc61860_wait_x(TRUE);m_icount-=1;break;
+		case 111: sc61860_wait_x(true);m_icount-=1;break;
 		case 112: sc61860_add(m_p, READ_OP());m_icount-=4;break;
 		case 113: sc61860_sub(m_p, READ_OP());m_icount-=4;break;
 		case 116: sc61860_add(A, READ_OP());m_icount-=4;break;

src/devices/cpu/sh2/sh2.cpp

@@ -2274,7 +2274,7 @@ void sh2_device::device_reset()
 
 	m_sh2_state->internal_irq_level = -1;
 
-	m_cache_dirty = TRUE;
+	m_cache_dirty = true;
 }
 
 
@@ -2565,7 +2565,7 @@ void sh2_device::device_start()
 	}
 
 	/* mark the cache dirty so it is updated on next execute */
-	m_cache_dirty = TRUE;
+	m_cache_dirty = true;
 }
 
 

src/devices/cpu/sh2/sh2.h

@@ -252,7 +252,7 @@ private:
 	{
 		offs_t              start;                      /* start of the RAM block */
 		offs_t              end;                        /* end of the RAM block */
-		uint8_t               readonly;                   /* TRUE if read-only */
+		bool                readonly;                   /* true if read-only */
 		void *              base;                       /* base in memory where the RAM lives */
 	} m_fastram[SH2_MAX_FASTRAM];
 
@@ -456,18 +456,18 @@ private:
 	void log_register_list(drcuml_state *drcuml, const char *string, const uint32_t *reglist, const uint32_t *regnostarlist);
 	void log_opcode_desc(drcuml_state *drcuml, const opcode_desc *desclist, int indent);
 	void log_add_disasm_comment(drcuml_block *block, uint32_t pc, uint32_t op);
-	void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
+	void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception);
 	void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
 	void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t ovrpc);
 	void generate_delay_slot(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t ovrpc);
-	int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t ovrpc);
+	bool generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint32_t ovrpc);
-	int generate_group_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
+	bool generate_group_0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
-	int generate_group_2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
+	bool generate_group_2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
-	int generate_group_3(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, uint32_t ovrpc);
+	bool generate_group_3(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, uint32_t ovrpc);
-	int generate_group_4(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
+	bool generate_group_4(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
-	int generate_group_6(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
+	bool generate_group_6(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
-	int generate_group_8(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
+	bool generate_group_8(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
-	int generate_group_12(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
+	bool generate_group_12(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc);
 
 public:
 	void func_printf_probe();

src/devices/cpu/sh4/sh4.cpp

@@ -338,7 +338,7 @@ inline void sh34_base_device::WB(offs_t A, uint8_t V)
 	const offs_t _A = A & AM;
 	for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
 	{
-		if (m_fastram[ramnum].readonly == TRUE || _A < m_fastram[ramnum].start || _A > m_fastram[ramnum].end)
+		if (m_fastram[ramnum].readonly == true || _A < m_fastram[ramnum].start || _A > m_fastram[ramnum].end)
 		{
 			continue;
 		}
@@ -364,7 +364,7 @@ inline void sh34_base_device::WW(offs_t A, uint16_t V)
 	const offs_t _A = A & AM;
 	for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
 	{
-		if (m_fastram[ramnum].readonly == TRUE || _A < m_fastram[ramnum].start || _A > m_fastram[ramnum].end)
+		if (m_fastram[ramnum].readonly == true || _A < m_fastram[ramnum].start || _A > m_fastram[ramnum].end)
 		{
 			continue;
 		}
@@ -390,7 +390,7 @@ inline void sh34_base_device::WL(offs_t A, uint32_t V)
 	const offs_t _A = A & AM;
 	for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
 	{
-		if (m_fastram[ramnum].readonly == TRUE || _A < m_fastram[ramnum].start || _A > m_fastram[ramnum].end)
+		if (m_fastram[ramnum].readonly == true || _A < m_fastram[ramnum].start || _A > m_fastram[ramnum].end)
 		{
 			continue;
 		}

src/devices/cpu/sh4/sh4.h

@@ -703,7 +703,7 @@ protected:
 	{
 		offs_t              start;                      /* start of the RAM block */
 		offs_t              end;                        /* end of the RAM block */
-		uint8_t               readonly;                   /* TRUE if read-only */
+		bool                readonly;                   /* true if read-only */
 		void *              base;                       /* base in memory where the RAM lives */
 	}       m_fastram[SH4_MAX_FASTRAM];
 #endif

src/devices/cpu/sharc/sharc.h

@@ -623,8 +623,8 @@ private:
 	void load_fast_iregs(drcuml_block *block);
 	void save_fast_iregs(drcuml_block *block);
 	void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, bool last_delayslot);
-	void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
+	void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception);
-	int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
+	bool generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
 	void generate_unimplemented_compute(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
 	void generate_compute(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
 	void generate_if_condition(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, int condition, int skip_label);

src/devices/cpu/sharc/sharcdrc.cpp

@@ -1202,7 +1202,7 @@ void adsp21062_device::compile_block(offs_t pc)
 
 
 				/* count off cycles and go there */
-				generate_update_cycles(block, &compiler, nextpc, TRUE);                     // <subtract cycles>
+				generate_update_cycles(block, &compiler, nextpc, true);                     // <subtract cycles>
 
 				if (seqlast->next() == nullptr || seqlast->next()->pc != nextpc)
 					UML_HASHJMP(block, 0, nextpc, *m_nocode);                               // hashjmp <mode>,nextpc,nocode
@@ -1536,13 +1536,13 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil
 	}
 }
 
-void adsp21062_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception)
+void adsp21062_device::generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, bool allow_exception)
 {
 	/* check full interrupts if pending */
 	if (compiler->checkints)
 	{
 		code_label skip = compiler->labelnum++;
-		compiler->checkints = FALSE;
+		compiler->checkints = false;
 
 		UML_CMP(block, mem(&m_core->irq_pending), 0);                                       // cmp     [irq_pending],0
 		UML_JMPc(block, COND_E, skip);                                                      // je      skip
@@ -1854,7 +1854,7 @@ void adsp21062_device::generate_call(drcuml_block *block, compiler_state *compil
 	// update cycles and hash jump
 	if (desc->targetpc != BRANCH_TARGET_DYNAMIC)
 	{
-		generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE);
+		generate_update_cycles(block, &compiler_temp, desc->targetpc, true);
 		if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
 			UML_JMP(block, desc->targetpc | 0x80000000);                                // jmp      targetpc | 0x80000000
 		else
@@ -1862,7 +1862,7 @@ void adsp21062_device::generate_call(drcuml_block *block, compiler_state *compil
 	}
 	else
 	{
-		generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), TRUE);
+		generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), true);
 		UML_HASHJMP(block, 0, mem(&m_core->jmpdest), *m_nocode);                        // hashjmp  0,jmpdest,nocode
 	}
 
@@ -1917,7 +1917,7 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil
 	// update cycles and hash jump
 	if (desc->targetpc != BRANCH_TARGET_DYNAMIC)
 	{
-		generate_update_cycles(block, &compiler_temp, desc->targetpc, TRUE);
+		generate_update_cycles(block, &compiler_temp, desc->targetpc, true);
 		if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
 			UML_JMP(block, desc->targetpc | 0x80000000);                                // jmp      targetpc | 0x80000000
 		else
@@ -1925,7 +1925,7 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil
 	}
 	else
 	{
-		generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), TRUE);
+		generate_update_cycles(block, &compiler_temp, mem(&m_core->jmpdest), true);
 		UML_HASHJMP(block, 0, mem(&m_core->jmpdest), *m_nocode);                        // hashjmp  0,jmpdest,nocode
 	}
 
@@ -1940,7 +1940,7 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil
 void adsp21062_device::generate_loop_jump(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
 {
 	// update cycles and hash jump
-	generate_update_cycles(block, compiler, desc->userdata0, TRUE);
+	generate_update_cycles(block, compiler, desc->userdata0, true);
 	/*
 	if (desc->flags & OPFLAG_INTRABLOCK_BRANCH)
 	    UML_JMP(block, desc->targetpc | 0x80000000);                                // jmp      targetpc | 0x80000000
@@ -2280,7 +2280,7 @@ void adsp21062_device::generate_write_ureg(drcuml_block *block, compiler_state *
 	}
 }
 
-int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
+bool adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
 {
 	uint64_t opcode = desc->opptr.q[0];
 
@@ -2297,12 +2297,12 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 						// IDLE
 						UML_MOV(block, mem(&m_core->idle), 1);
 						UML_MOV(block, mem(&m_core->icount), 0);
-						return TRUE;
+						return true;
 					}
 					else
 					{
 						// NOP
-						return TRUE;
+						return true;
 					}
 					break;
 
@@ -2323,7 +2323,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 
 					if (has_condition)
 						UML_LABEL(block, skip_label);
-					return TRUE;
+					return true;
 				}
 
 				case 0x02:          // immediate shift                      |000|00010|
@@ -2347,7 +2347,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 
 					if (has_condition)
 						UML_LABEL(block, skip_label);
-					return TRUE;
+					return true;
 				}
 
 				case 0x04:          // compute / modify                     |000|00100|
@@ -2384,7 +2384,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 					if (has_condition)
 						UML_LABEL(block, skip_label);
 
-					return TRUE;
+					return true;
 				}
 
 				case 0x06:          // direct jump|call                     |000|00110|
@@ -2413,7 +2413,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 					}
 					if (has_condition)
 						UML_LABEL(block, skip_label);
-					return TRUE;
+					return true;
 				}
 
 				case 0x07:          // direct jump|call                     |000|00111|
@@ -2442,7 +2442,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 					}
 					if (has_condition)
 						UML_LABEL(block, skip_label);
-					return TRUE;
+					return true;
 				}
 
 				case 0x08:          // indirect jump|call / compute         |000|01000|
@@ -2505,7 +2505,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 							UML_LABEL(block, skip_label);
 					}
 
-					return TRUE;
+					return true;
 				}
 
 				case 0x09:          // indirect jump|call / compute         |000|01001|
@@ -2562,7 +2562,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 							UML_LABEL(block, skip_label);
 					}
 
-					return TRUE;
+					return true;
 				}
 
 				case 0x0a:          // return from subroutine / compute     |000|01010|
@@ -2607,7 +2607,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 							UML_LABEL(block, skip_label);
 					}
 
-					return TRUE;
+					return true;
 				}
 
 				case 0x0b:          // return from interrupt / compute      |000|01011|
@@ -2664,7 +2664,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 							UML_LABEL(block, skip_label);
 					}
 
-					return TRUE;
+					return true;
 				}
 
 				case 0x0c:          // do until counter expired             |000|01100|
@@ -2685,7 +2685,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 						UML_MOV(block, I1, address);
 						UML_CALLH(block, *m_push_loop);
 					}
-					return TRUE;
+					return true;
 				}
 
 				case 0x0d:          // do until counter expired             |000|01101|
@@ -2707,7 +2707,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 					UML_MOV(block, I0, I3);
 					UML_MOV(block, I1, address);
 					UML_CALLH(block, *m_push_loop);
-					return TRUE;
+					return true;
 				}
 
 				case 0x0e:          // do until                             |000|01110|
@@ -2723,7 +2723,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 					UML_MOV(block, I0, 0);
 					UML_MOV(block, I1, address);
 					UML_CALLH(block, *m_push_loop);
-					return TRUE;
+					return true;
 				}
 
 				case 0x0f:          // immediate data -> ureg               |000|01111|
@@ -2732,7 +2732,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 					uint32_t data = (uint32_t)opcode;
 
 					generate_write_ureg(block, compiler, desc, ureg, true, data);
-					return TRUE;
+					return true;
 				}
 
 				case 0x10:          // ureg <-> DM|PM (direct)              |000|100|G|D|
@@ -2784,7 +2784,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 
 						generate_write_ureg(block, compiler, desc, ureg, false, 0);
 					}
-					return TRUE;
+					return true;
 				}
 
 				case 0x14:          // system register bit manipulation     |000|10100|
@@ -2872,9 +2872,9 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 									break;
 
 								default:
-									return FALSE;
+									return false;
 							}
-							return TRUE;
+							return true;
 						}
 						case 1:     // CLEAR
 						{
@@ -2953,9 +2953,9 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 									break;
 
 								default:
-									return FALSE;
+									return false;
 							}
-							return TRUE;
+							return true;
 						}
 						case 2:     // TOGGLE
 						{
@@ -2979,7 +2979,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 									compiler->mode1_delay.mode = MODE1_TOGGLE;
 									break;
 								case 0xc: // ASTAT
-									return FALSE;
+									return false;
 								case 0xd: // IMASK
 									UML_XOR(block, IMASK, IMASK, data);
 									break;
@@ -2991,9 +2991,9 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 									break;
 
 								default:
-									return FALSE;
+									return false;
 							}
-							return TRUE;
+							return true;
 						}
 						case 4:     // TEST
 						{
@@ -3025,7 +3025,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 									UML_SETc(block, COND_E, ASTAT_BTF);
 									break;
 								case 0xc: // ASTAT
-									return FALSE;
+									return false;
 								case 0xd: // IMASK
 									UML_AND(block, I0, IMASK, data);
 									UML_CMP(block, I0, data);
@@ -3043,26 +3043,26 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 									break;
 
 								default:
-									return FALSE;
+									return false;
 							}
-							return TRUE;
+							return true;
 						}
 						case 5:     // XOR
 						{
-							return FALSE;
+							return false;
 						}
 
 						default:
-							return FALSE;
+							return false;
 					}
-					return TRUE;
+					return true;
 				}
 
 				case 0x16:          // I register modify / bit-reverse      |000|10110|
 				{
 					if (opcode & U64(0x008000000000))   // bit reverse
 					{
-						return FALSE;
+						return false;
 					}
 					else            // modify
 					{
@@ -3081,7 +3081,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 							UML_ADD(block, DM_I(i), DM_I(i), data);
 						}
 						generate_update_circular_buffer(block, compiler, desc, g, i);
-						return TRUE;
+						return true;
 					}
 				}
 
@@ -3112,17 +3112,17 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 					{
 						UML_CALLH(block, *m_pop_pc);
 					}
-					return TRUE;
+					return true;
 				}
 
 				case 0x18:          // cjump                                |000|11000|
-					return FALSE;
+					return false;
 
 				case 0x19:          // rframe                               |000|11001|
-					return FALSE;
+					return false;
 
 				default:
-					return FALSE;
+					return false;
 			}
 			break;
 		}
@@ -3199,7 +3199,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 				UML_ADD(block, DM_I(dmi), DM_I(dmi), DM_M(dmm));
 				generate_update_circular_buffer(block, compiler, desc, 0, dmi);
 			}
-			return TRUE;
+			return true;
 		}
 
 		case 2:             // compute / ureg <-> DM|PM, register modify                            |010|
@@ -3290,7 +3290,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 			if (has_condition)
 				UML_LABEL(block, skip_label);
 
-			return TRUE;
+			return true;
 		}
 
 		case 3:
@@ -3341,7 +3341,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 				if (has_condition)
 					UML_LABEL(block, skip_label);
 
-				return TRUE;
+				return true;
 			}
 			else                                // compute / dreg <-> DM|PM, immediate modify       |011|0|
 			{
@@ -3413,7 +3413,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 				if (has_condition)
 					UML_LABEL(block, skip_label);
 
-				return TRUE;
+				return true;
 			}
 			break;
 		}
@@ -3446,7 +3446,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 
 				generate_update_circular_buffer(block, compiler, desc, g, i);
 
-				return TRUE;
+				return true;
 			}
 			else                                // immediate shift / dreg <-> DM|PM                 |100|0|
 			{
@@ -3515,7 +3515,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 				if (has_condition)
 					UML_LABEL(block, skip_label);
 
-				return TRUE;
+				return true;
 			}
 			break;
 		}
@@ -3552,7 +3552,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 
 				generate_write_ureg(block, compiler, desc, ureg, false, 0);
 			}
-			return TRUE;
+			return true;
 		}
 
 		case 6:                             // indirect jump / compute / dreg <-> DM                |110|
@@ -3613,7 +3613,7 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 
 			generate_update_circular_buffer(block, compiler, desc, 0, dmi);
 
-			return TRUE;
+			return true;
 		}
 
 		case 7:                             // indirect jump / compute / dreg <-> DM                |111|
@@ -3671,11 +3671,11 @@ int adsp21062_device::generate_opcode(drcuml_block *block, compiler_state *compi
 
 			generate_update_circular_buffer(block, compiler, desc, 0, dmi);
 
-			return TRUE;
+			return true;
 		}
 	}
 
-	return FALSE;
+	return false;
 }
 
 void adsp21062_device::generate_unimplemented_compute(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
@@ -5303,7 +5303,7 @@ void adsp21062_device::generate_if_condition(drcuml_block *block, compiler_state
 		case 0x1e:                                    /* NOT BM */
 			fatalerror("generate_if_condition 0x1e"); // should not happen
 			break;
-		case 0x1f:                                    /* TRUE */
+		case 0x1f:                                    /* true */
 			fatalerror("generate_if_condition 0x1f"); // should not happen
 			break;
 	}
@@ -5452,7 +5452,7 @@ void adsp21062_device::generate_do_condition(drcuml_block *block, compiler_state
 			// always true
 			UML_JMP(block, skip_label);
 			break;
-		case 0x1f:                                    /* FALSE (FOREVER) */
+		case 0x1f:                                    /* false (FOREVER) */
 			// infinite loop
 			break;
 	}

src/devices/cpu/tms34010/tms34010.cpp

@@ -37,7 +37,7 @@ tms340x0_device::tms340x0_device(const machine_config &mconfig, device_type type
 	: cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__)
 	, device_video_interface(mconfig, *this)
 	, m_program_config("program", ENDIANNESS_LITTLE, 16, 32, 3), m_pc(0), m_ppc(0), m_st(0), m_pixel_write(nullptr), m_pixel_read(nullptr), m_raster_op(nullptr), m_pixel_op(nullptr), m_pixel_op_timing(0), m_convsp(0), m_convdp(0), m_convmp(0), m_gfxcycles(0), m_pixelshift(0), m_is_34020(0), m_reset_deferred(false)
-		, m_halt_on_reset(FALSE), m_hblank_stable(0), m_external_host_access(0), m_executing(0), m_program(nullptr), m_direct(nullptr)
+		, m_halt_on_reset(false), m_hblank_stable(0), m_external_host_access(0), m_executing(0), m_program(nullptr), m_direct(nullptr)
 		, m_pixclock(0)
 	, m_pixperclock(0), m_scantimer(nullptr), m_icount(0)
 		, m_output_int_cb(*this)
@@ -577,7 +577,7 @@ void tms340x0_device::device_start()
 	m_to_shiftreg_cb.bind_relative_to(*owner());
 	m_from_shiftreg_cb.bind_relative_to(*owner());
 
-	m_external_host_access = FALSE;
+	m_external_host_access = false;
 
 	m_program = &space(AS_PROGRAM);
 	m_direct = &m_program->direct();
@@ -720,12 +720,12 @@ void tms340x0_device::execute_run()
 	/* if the CPU's reset was deferred, do it now */
 	if (m_reset_deferred)
 	{
-		m_reset_deferred = FALSE;
+		m_reset_deferred = false;
 		m_pc = RLONG(0xffffffe0);
 	}
 
 	/* check interrupts first */
-	m_executing = TRUE;
+	m_executing = true;
 	check_interrupt();
 	if ((machine().debug_flags & DEBUG_FLAG_ENABLED) == 0)
 	{
@@ -748,7 +748,7 @@ void tms340x0_device::execute_run()
 			(this->*s_opcode_table[op >> 4])(op);
 		} while (m_icount > 0);
 	}
-	m_executing = FALSE;
+	m_executing = false;
 }
 
 
@@ -1526,10 +1526,10 @@ WRITE16_MEMBER( tms340x0_device::host_w )
 		/* control register */
 		case TMS34010_HOST_CONTROL:
 		{
-			m_external_host_access = TRUE;
+			m_external_host_access = true;
 			if (mem_mask&0xff00) io_register_w(*m_program, REG_HSTCTLH, data & 0xff00, 0xff00);
 			if (mem_mask&0x00ff) io_register_w(*m_program, REG_HSTCTLL, data & 0x00ff, 0x00ff);
-			m_external_host_access = FALSE;
+			m_external_host_access = false;
 			break;
 		}
 

src/devices/cpu/z80/z80.cpp

@@ -665,7 +665,7 @@ inline void z80_device::ld_a_r()
 {
 	A = (m_r & 0x7f) | m_r2;
 	F = (F & CF) | SZ[A] | (m_iff2 << 2);
-	m_after_ldair = TRUE;
+	m_after_ldair = true;
 }
 
 /***************************************************************
@@ -683,7 +683,7 @@ inline void z80_device::ld_a_i()
 {
 	A = m_i;
 	F = (F & CF) | SZ[A] | (m_iff2 << 2);
-	m_after_ldair = TRUE;
+	m_after_ldair = true;
 }
 
 /***************************************************************
@@ -1359,7 +1359,7 @@ inline void z80_device::otdr()
 inline void z80_device::ei()
 {
 	m_iff1 = m_iff2 = 1;
-	m_after_ei = TRUE;
+	m_after_ei = true;
 }
 
 /**********************************************************
@@ -3139,7 +3139,7 @@ void z80_device::take_nmi()
 	PCD = 0x0066;
 	WZ=PCD;
 	m_icount -= 11;
-	m_nmi_pending = FALSE;
+	m_nmi_pending = false;
 }
 
 void z80_device::take_interrupt()
@@ -3475,9 +3475,9 @@ void z80_device::device_reset()
 	m_i = 0;
 	m_r = 0;
 	m_r2 = 0;
-	m_nmi_pending = FALSE;
+	m_nmi_pending = false;
-	m_after_ei = FALSE;
+	m_after_ei = false;
-	m_after_ldair = FALSE;
+	m_after_ldair = false;
 	m_iff1 = 0;
 	m_iff2 = 0;
 
@@ -3510,8 +3510,8 @@ void z80_device::execute_run()
 		else if (m_irq_state != CLEAR_LINE && m_iff1 && !m_after_ei)
 			take_interrupt();
 
-		m_after_ei = FALSE;
+		m_after_ei = false;
-		m_after_ldair = FALSE;
+		m_after_ldair = false;
 
 		PRVPC = PCD;
 		debugger_instruction_hook(this, PCD);
@@ -3539,8 +3539,8 @@ void nsc800_device::execute_run()
 		else if (m_irq_state != CLEAR_LINE && m_iff1 && !m_after_ei)
 			take_interrupt();
 
-		m_after_ei = FALSE;
+		m_after_ei = false;
-		m_after_ldair = FALSE;
+		m_after_ldair = false;
 
 		PRVPC = PCD;
 		debugger_instruction_hook(this, PCD);
@@ -3560,7 +3560,7 @@ void z80_device::execute_set_input(int inputnum, int state)
 	case INPUT_LINE_NMI:
 		/* mark an NMI pending on the rising edge */
 		if (m_nmi_state == CLEAR_LINE && state != CLEAR_LINE)
-			m_nmi_pending = TRUE;
+			m_nmi_pending = true;
 		m_nmi_state = state;
 		break;
 

src/devices/imagedev/flopdrv.cpp

@@ -781,7 +781,7 @@ void legacy_floppy_image_device::device_start()
 	floppy_drive_init();
 
 	m_drive_id = floppy_get_drive(this);
-	m_active = FALSE;
+	m_active = false;
 
 	/* resolve callbacks */
 	m_out_idx_func.resolve_safe();

src/devices/imagedev/printer.cpp

@@ -92,7 +92,7 @@ image_init_result printer_image_device::call_load()
 {
 	/* send notify that the printer is now online */
 	if (!m_online_cb.isnull())
-		m_online_cb(TRUE);
+		m_online_cb(true);
 
 	/* we don't need to do anything special */
 	return image_init_result::PASS;
@@ -106,5 +106,5 @@ void printer_image_device::call_unload()
 {
 	/* send notify that the printer is now offline */
 	if (!m_online_cb.isnull())
-		m_online_cb(FALSE);
+		m_online_cb(false);
 }

src/devices/machine/53c810.cpp

@@ -718,7 +718,7 @@ unsigned lsi53c810_device::lsi53c810_dasm(char *buf, uint32_t pc)
 		}
 
 		buf += sprintf(buf, "%s ", op_mnemonic);
-		need_cojunction = FALSE;
+		need_cojunction = false;
 
 		for (i = 0; i < ARRAY_LENGTH(flags); i++)
 		{
@@ -727,7 +727,7 @@ unsigned lsi53c810_device::lsi53c810_dasm(char *buf, uint32_t pc)
 				if (need_cojunction)
 					buf += sprintf(buf, " AND ");
 				else
-					need_cojunction = TRUE;
+					need_cojunction = true;
 				buf += sprintf(buf, "%s", flags[i].text);
 			}
 		}

src/devices/machine/6532riot.cpp

@@ -483,6 +483,6 @@ void riot6532_device::device_timer(emu_timer &timer, device_timer_id id, int par
 			timer_end();
 			break;
 		default:
-			assert_always(FALSE, "Unknown id in riot6532_device::device_timer");
+			assert_always(false, "Unknown id in riot6532_device::device_timer");
 	}
 }

src/devices/machine/6821pia.cpp

@@ -143,8 +143,8 @@ void pia6821_device::device_reset()
 	// ports B,CB1,CB2 are three-state and undefined (set to 0)
 	//
 	m_in_a = 0xff;
-	m_in_ca1 = TRUE;
+	m_in_ca1 = true;
-	m_in_ca2 = TRUE;
+	m_in_ca2 = true;
 	m_out_a = 0;
 	m_out_ca2 = 0;
 	m_port_a_z_mask = 0;
@@ -183,8 +183,8 @@ void pia6821_device::device_reset()
 
 
 	// clear the IRQs
-	m_irqa_handler(FALSE);
+	m_irqa_handler(false);
-	m_irqb_handler(FALSE);
+	m_irqb_handler(false);
 }
 
 
@@ -409,20 +409,20 @@ uint8_t pia6821_device::port_a_r()
 	uint8_t ret = get_in_a_value();
 
 	// IRQ flags implicitly cleared by a read
-	m_irq_a1 = FALSE;
+	m_irq_a1 = false;
-	m_irq_a2 = FALSE;
+	m_irq_a2 = false;
 	update_interrupts();
 
 	// CA2 is configured as output and in read strobe mode
 	if(C2_OUTPUT(m_ctl_a) && C2_STROBE_MODE(m_ctl_a))
 	{
 		// this will cause a transition low
-		set_out_ca2(FALSE);
+		set_out_ca2(false);
 
 		// if the CA2 strobe is cleared by the E, reset it right away
 		if(STROBE_E_RESET(m_ctl_a))
 		{
-			set_out_ca2(TRUE);
+			set_out_ca2(true);
 		}
 	}
 
@@ -460,12 +460,12 @@ uint8_t pia6821_device::port_b_r()
 	// from what happens with port A.
 	if(m_irq_b1 && C2_STROBE_MODE(m_ctl_b) && STROBE_C1_RESET(m_ctl_b))
 	{
-		set_out_cb2(TRUE);
+		set_out_cb2(true);
 	}
 
 	// IRQ flags implicitly cleared by a read
-	m_irq_b1 = FALSE;
+	m_irq_b1 = false;
-	m_irq_b2 = FALSE;
+	m_irq_b2 = false;
 	update_interrupts();
 
 	LOG(("PIA #%s: port B read = %02X\n", tag(), ret));
@@ -740,12 +740,12 @@ void pia6821_device::port_b_w(uint8_t data)
 	if(C2_STROBE_MODE(m_ctl_b))
 	{
 		// this will cause a transition low
-		set_out_cb2(FALSE);
+		set_out_cb2(false);
 
 		// if the CB2 strobe is cleared by the E, reset it right away
 		if(STROBE_E_RESET(m_ctl_b))
 		{
-			set_out_cb2(TRUE);
+			set_out_cb2(true);
 		}
 	}
 }
@@ -807,7 +807,7 @@ void pia6821_device::control_a_w(uint8_t data)
 		else
 		{
 			// strobe mode - output is always high unless strobed
-			temp = TRUE;
+			temp = true;
 		}
 
 		set_out_ca2(temp);
@@ -842,7 +842,7 @@ void pia6821_device::control_b_w(uint8_t data)
 	else
 	{
 		// strobe mode - output is always high unless strobed
-		temp = TRUE;
+		temp = true;
 	}
 
 	set_out_cb2(temp);
@@ -946,7 +946,7 @@ WRITE_LINE_MEMBER( pia6821_device::ca1_w )
 		LOG(("PIA #%s: CA1 triggering\n", tag()));
 
 		// mark the IRQ
-		m_irq_a1 = TRUE;
+		m_irq_a1 = true;
 
 		// update externals
 		update_interrupts();
@@ -954,7 +954,7 @@ WRITE_LINE_MEMBER( pia6821_device::ca1_w )
 		// CA2 is configured as output and in read strobe mode and cleared by a CA1 transition
 		if(C2_OUTPUT(m_ctl_a) && C2_STROBE_MODE(m_ctl_a) && STROBE_C1_RESET(m_ctl_a))
 		{
-			set_out_ca2(TRUE);
+			set_out_ca2(true);
 		}
 	}
 
@@ -978,7 +978,7 @@ WRITE_LINE_MEMBER( pia6821_device::ca2_w )
 		LOG(("PIA #%s: CA2 triggering\n", tag()));
 
 		// mark the IRQ
-		m_irq_a2 = TRUE;
+		m_irq_a2 = true;
 
 		// update externals
 		update_interrupts();

src/devices/machine/6850acia.cpp

@@ -362,7 +362,7 @@ WRITE_LINE_MEMBER( acia6850_device::write_rxc )
 					{
 						if (m_rx_counter != 1)
 						{
-							if (LOG) logerror("MC6850 '%s': RX FALSE START BIT\n", tag());
+							if (LOG) logerror("MC6850 '%s': RX false START BIT\n", tag());
 						}
 
 						m_rx_counter = 0;

src/devices/machine/appldriv.cpp

@@ -101,7 +101,7 @@ static void apple525_seek_disk(apple525_floppy_image_device *img, signed int ste
 
 	disk = get_device(img);
 
-	apple525_save_current_track(img, FALSE);
+	apple525_save_current_track(img, false);
 
 	track = img->floppy_drive_get_current_track();
 	pseudo_track = (track * 2) + disk->tween_tracks;
@@ -237,7 +237,7 @@ static uint8_t apple525_process_byte(device_t *img, int write_value)
 
 	/* when writing; save the current track after every full sector write */
 	if ((write_value >= 0) && ((disk->position % APPLE2_NIBBLE_SIZE) == 0))
-		apple525_save_current_track(img, FALSE);
+		apple525_save_current_track(img, false);
 
 	return read_value;
 }
@@ -330,7 +330,7 @@ image_init_result apple525_floppy_image_device::call_load()
 
 void apple525_floppy_image_device::call_unload()
 {
-	apple525_save_current_track(this, TRUE);
+	apple525_save_current_track(this, true);
 
 	legacy_floppy_image_device::call_unload();
 }

src/devices/machine/bcreader.h

@@ -33,7 +33,7 @@ public:
 	int read_pixel();
 
 	// TODO: add checksum validation!
-	bool is_valid(int len) { return (len != 12 && len != 13 && len != 8) ? FALSE : TRUE; }
+	bool is_valid(int len) { return (len != 12 && len != 13 && len != 8) ? false : true; }
 	void decode(int len);
 
 protected:

src/devices/machine/ds2404.cpp

@@ -366,7 +366,7 @@ void ds2404_device::device_timer(emu_timer &timer, device_timer_id id, int param
 		}
 
 		default:
-			assert_always(FALSE, "Unknown id in ds2404_device::device_timer");
+			assert_always(false, "Unknown id in ds2404_device::device_timer");
 			break;
 	}
 }

src/devices/machine/e05a30.cpp

@@ -73,13 +73,13 @@ void e05a30_device::device_reset()
 	m_cr_stepper = 0x00;
 
 	/* centronics init */
-	m_centronics_nack = FALSE;
+	m_centronics_nack = false;
-	m_centronics_busy = FALSE;
+	m_centronics_busy = false;
 	m_write_centronics_ack   (!m_centronics_nack);
 	m_write_centronics_busy  ( m_centronics_busy);
-	m_write_centronics_perror(FALSE);
+	m_write_centronics_perror(false);
-	m_write_centronics_fault (TRUE);
+	m_write_centronics_fault (true);
-	m_write_centronics_select(TRUE);
+	m_write_centronics_select(true);
 
 	m_write_ready(1);
 }
@@ -150,11 +150,11 @@ void e05a30_device::update_cr_stepper(uint8_t data)
 
 WRITE_LINE_MEMBER( e05a30_device::centronics_input_strobe )
 {
-	if (m_centronics_strobe == TRUE && state == FALSE && !m_centronics_busy) {
+	if (m_centronics_strobe == true && state == false && !m_centronics_busy) {
 		m_centronics_data_latch   = m_centronics_data;
 
-		m_centronics_data_latched = TRUE;
+		m_centronics_data_latched = true;
-		m_centronics_busy         = TRUE;
+		m_centronics_busy         = true;
 		m_write_centronics_busy(m_centronics_busy);
 	}
 
@@ -180,7 +180,7 @@ WRITE8_MEMBER( e05a30_device::write )
 		 * assume the busy signal cannot be reset while the data hasn't been
 		 * read. */
 		if (m_centronics_data_latched)
-			m_centronics_busy = TRUE;
+			m_centronics_busy = true;
 		m_write_centronics_ack (!m_centronics_nack);
 		m_write_centronics_busy( m_centronics_busy);
 		break;
@@ -206,7 +206,7 @@ READ8_MEMBER( e05a30_device::read )
 		break;
 	case 0x03:
 		result = m_centronics_data_latch;
-		m_centronics_data_latched = FALSE;
+		m_centronics_data_latched = false;
 		break;
 	case 0x04:
 		result |= m_centronics_busy << 0;

src/devices/machine/f3853.cpp

@@ -63,10 +63,10 @@ void f3853_device::device_start()
 	uint8_t reg = 0xfe;
 	for(int32_t i=254 /* Known to get 0xfe after 255 cycles */; i >= 0; i--)
 	{
-		int32_t o7 = (reg & 0x80) ? TRUE : FALSE;
+		int32_t o7 = (reg & 0x80) ? true : false;
-		int32_t o5 = (reg & 0x20) ? TRUE : FALSE;
+		int32_t o5 = (reg & 0x20) ? true : false;
-		int32_t o4 = (reg & 0x10) ? TRUE : FALSE;
+		int32_t o4 = (reg & 0x10) ? true : false;
-		int32_t o3 = (reg & 0x08) ? TRUE : FALSE;
+		int32_t o3 = (reg & 0x08) ? true : false;
 		m_value_to_cycle[reg] = i;
 		reg <<= 1;
 		if (!((o7 != o5) != (o4 != o3)))
@@ -100,8 +100,8 @@ void f3853_device::device_reset()
 	m_external_enable = 0;
 	m_timer_enable = 0;
 	m_request_flipflop = 0;
-	m_priority_line = FALSE;
+	m_priority_line = false;
-	m_external_interrupt_line = TRUE;
+	m_external_interrupt_line = true;
 
 	m_timer->enable(false);
 }
@@ -113,11 +113,11 @@ void f3853_device::set_interrupt_request_line()
 		return;
 
 	if (m_external_enable && !m_priority_line)
-		m_interrupt_req_cb(INTERRUPT_VECTOR(TRUE), TRUE);
+		m_interrupt_req_cb(INTERRUPT_VECTOR(true), true);
 	else if (m_timer_enable && !m_priority_line && m_request_flipflop)
-		m_interrupt_req_cb(INTERRUPT_VECTOR(FALSE), TRUE);
+		m_interrupt_req_cb(INTERRUPT_VECTOR(false), true);
 	else
-		m_interrupt_req_cb(0, FALSE);
+		m_interrupt_req_cb(0, false);
 }
 
 
@@ -132,7 +132,7 @@ TIMER_CALLBACK_MEMBER(f3853_device::timer_callback)
 {
 	if(m_timer_enable)
 	{
-		m_request_flipflop = TRUE;
+		m_request_flipflop = true;
 		set_interrupt_request_line();
 	}
 	timer_start(0xfe);
@@ -142,7 +142,7 @@ void f3853_device::set_external_interrupt_in_line(int level)
 {
 	if(m_external_interrupt_line && !level && m_external_enable)
 	{
-		m_request_flipflop = TRUE;
+		m_request_flipflop = true;
 	}
 	m_external_interrupt_line = level;
 	set_interrupt_request_line();
@@ -197,7 +197,7 @@ WRITE8_MEMBER(f3853_device::write)
 		break;
 
 	case 3: //timer
-		m_request_flipflop = FALSE;
+		m_request_flipflop = false;
 		set_interrupt_request_line();
 		timer_start(data);
 		break;

src/devices/machine/gt64xxx.cpp

@@ -71,7 +71,7 @@ void gt64xxx_device::device_start()
 	uint32_t romSize = m_romRegion->bytes();
 	m_cpu_space->install_rom   (0x1fc00000, 0x1fc00000 + romSize - 1, m_romRegion->base());
 	// ROM MIPS DRC
-	m_cpu->add_fastram(0x1fc00000, 0x1fc00000 + romSize - 1, TRUE, m_romRegion->base());
+	m_cpu->add_fastram(0x1fc00000, 0x1fc00000 + romSize - 1, true, m_romRegion->base());
 	if (LOG_GALILEO)
 		logerror("%s: gt64xxx_device::device_start ROM Mapped size: 0x%08X start: 0x1fc00000 end: %08X\n", tag(), romSize, 0x1fc00000 + romSize - 1);
 
@@ -175,8 +175,8 @@ void gt64xxx_device::map_cpu_space()
 		winEnd = (m_reg[GREG_RAS_1_0_LO + 0x10 / 4 * (ramIndex / 2)] << 21) | (m_reg[GREG_RAS0_HI + 0x8 / 4 * ramIndex] << 20) | 0xfffff;
 		m_ram[ramIndex].resize((winEnd + 1 - winStart) / 4);
 		m_cpu_space->install_ram(winStart, winEnd, m_ram[ramIndex].data());
-		//m_cpu->add_fastram(winStart, m_ram[ramIndex].size() * sizeof(m_ram[ramIndex][0]), FALSE, &m_ram[ramIndex][0]);
+		//m_cpu->add_fastram(winStart, m_ram[ramIndex].size() * sizeof(m_ram[ramIndex][0]), false, &m_ram[ramIndex][0]);
-		//m_cpu->add_fastram(winStart, m_ram[ramIndex].size() * sizeof(uint32_t), FALSE, m_ram[ramIndex].data());
+		//m_cpu->add_fastram(winStart, m_ram[ramIndex].size() * sizeof(uint32_t), false, m_ram[ramIndex].data());
 		if (LOG_GALILEO)
 			logerror("%s: map_cpu_space ras[%i] start: %08X end: %08X\n", tag(), ramIndex, winStart, winEnd);
 	}

src/devices/machine/ldpr8210.cpp

@@ -328,7 +328,7 @@ void pioneer_pr8210_device::device_timer(emu_timer &timer, device_timer_id id, i
 			// logging
 			if (LOG_VBLANK_VBI)
 			{
-				uint32_t line1718 = get_field_code(LASERDISC_CODE_LINE1718, FALSE);
+				uint32_t line1718 = get_field_code(LASERDISC_CODE_LINE1718, false);
 				if ((line1718 & VBI_MASK_CAV_PICTURE) == VBI_CODE_CAV_PICTURE)
 					printf("%3d:VBI(%05d)\n", screen().vpos(), VBI_CAV_PICTURE(line1718));
 				else
@@ -340,8 +340,8 @@ void pioneer_pr8210_device::device_timer(emu_timer &timer, device_timer_id id, i
 			m_pia.vbi2 = 0xff;
 			if (focus_on() && laser_on())
 			{
-				uint32_t line16 = get_field_code(LASERDISC_CODE_LINE16, FALSE);
+				uint32_t line16 = get_field_code(LASERDISC_CODE_LINE16, false);
-				uint32_t line1718 = get_field_code(LASERDISC_CODE_LINE1718, FALSE);
+				uint32_t line1718 = get_field_code(LASERDISC_CODE_LINE1718, false);
 				if (line1718 == VBI_CODE_LEADIN)
 					m_pia.vbi1 &= ~0x01;
 				if (line1718 == VBI_CODE_LEADOUT)