mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
drivers starting with j, k, l and part of m: read* and write* macro removal (nw)
This commit is contained in:
parent
8b69ca54e2
commit
148c8649c7
@ -1461,7 +1461,7 @@ void dcs_audio_device::set_io_callbacks(write_line_delegate output_full_cb, writ
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}
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void dcs_audio_device::set_fifo_callbacks(read16smo_delegate fifo_data_r, read16_delegate fifo_status_r, write_line_delegate fifo_reset_w)
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void dcs_audio_device::set_fifo_callbacks(read16smo_delegate fifo_data_r, read16mo_delegate fifo_status_r, write_line_delegate fifo_reset_w)
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{
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m_fifo_data_r = fifo_data_r;
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m_fifo_status_r = fifo_status_r;
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@ -1506,7 +1506,7 @@ uint16_t dcs_audio_device::latch_status_r(address_space &space)
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if (IS_OUTPUT_EMPTY())
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result |= 0x40;
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if (!m_fifo_status_r.isnull() && (!m_transfer.hle_enabled || m_transfer.state == 0))
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result |= m_fifo_status_r(space, 0, 0xffff) & 0x38;
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result |= m_fifo_status_r(space) & 0x38;
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if (m_transfer.hle_enabled && m_transfer.state != 0)
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result |= 0x08;
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return result;
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@ -26,7 +26,7 @@ public:
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void set_auto_ack(int state);
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void set_fifo_callbacks(read16smo_delegate fifo_data_r, read16_delegate fifo_status_r, write_line_delegate fifo_reset_w);
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void set_fifo_callbacks(read16smo_delegate fifo_data_r, read16mo_delegate fifo_status_r, write_line_delegate fifo_reset_w);
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void set_io_callbacks(write_line_delegate output_full_cb, write_line_delegate input_empty_cb);
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uint16_t data_r();
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@ -218,7 +218,7 @@ protected:
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write_line_delegate m_input_empty_cb;
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read16smo_delegate m_fifo_data_r;
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read16_delegate m_fifo_status_r;
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read16mo_delegate m_fifo_status_r;
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write_line_delegate m_fifo_reset_w;
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/* timers */
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@ -215,7 +215,7 @@ void jaguar_state::sound_start()
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*
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*************************************/
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READ16_MEMBER( jaguar_state::jerry_regs_r )
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uint16_t jaguar_state::jerry_regs_r(offs_t offset)
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{
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if (offset != JINTCTRL && offset != JINTCTRL+2)
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logerror("%s:jerry read register @ F10%03X\n", machine().describe_context(), offset * 2);
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@ -232,7 +232,7 @@ READ16_MEMBER( jaguar_state::jerry_regs_r )
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}
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WRITE16_MEMBER( jaguar_state::jerry_regs_w )
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void jaguar_state::jerry_regs_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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{
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COMBINE_DATA(&m_dsp_regs[offset]);
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@ -258,7 +258,7 @@ WRITE16_MEMBER( jaguar_state::jerry_regs_w )
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#if ENABLE_SPEEDUP_HACKS
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WRITE32_MEMBER( jaguar_state::dsp_flags_w )
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void jaguar_state::dsp_flags_w(address_space &space, offs_t offset, uint32_t data, uint32_t mem_mask)
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{
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/* write the data through */
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m_dsp->iobus_w(offset, data, mem_mask);
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@ -321,14 +321,14 @@ void jaguar_state::serial_update()
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*
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*************************************/
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READ32_MEMBER( jaguar_state::serial_r )
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uint32_t jaguar_state::serial_r(offs_t offset)
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{
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logerror("%s:jaguar_serial_r(%X)\n", machine().describe_context(), offset);
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return 0;
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}
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WRITE32_MEMBER( jaguar_state::serial_w )
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void jaguar_state::serial_w(offs_t offset, uint32_t data)
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{
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switch (offset)
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{
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@ -11,22 +11,22 @@
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#include "includes/laserbat.h"
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READ8_MEMBER(laserbat_state_base::rhsc_r)
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uint8_t laserbat_state_base::rhsc_r()
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{
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return m_rhsc;
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}
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WRITE8_MEMBER(laserbat_state_base::whsc_w)
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void laserbat_state_base::whsc_w(uint8_t data)
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{
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m_whsc = data;
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}
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WRITE8_MEMBER(laserbat_state_base::csound1_w)
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void laserbat_state_base::csound1_w(uint8_t data)
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{
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m_csound1 = data;
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}
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WRITE8_MEMBER(laserbat_state_base::csound2_w)
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void laserbat_state_base::csound2_w(uint8_t data)
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{
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m_csound2 = data;
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}
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@ -127,7 +127,7 @@ WRITE8_MEMBER(laserbat_state_base::csound2_w)
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*/
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WRITE8_MEMBER(laserbat_state::csound2_w)
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void laserbat_state::csound2_w(uint8_t data)
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{
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// there are a bunch of edge-triggered things, so grab changes
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unsigned const diff = data ^ m_csound2;
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@ -307,14 +307,14 @@ WRITE8_MEMBER(laserbat_state::csound2_w)
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it isn't routed anywhere.
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*/
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WRITE8_MEMBER(catnmous_state::csound1_w)
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void catnmous_state::csound1_w(uint8_t data)
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{
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m_audiopcb->sound_w(data);
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m_csound1 = data;
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}
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WRITE8_MEMBER(catnmous_state::csound2_w)
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void catnmous_state::csound2_w(uint8_t data)
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{
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// the bottom bit is used for sprite banking, of all things
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m_gfx2 = memregion("gfx2")->base() + ((data & 0x01) ? 0x0800 : 0x0000);
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@ -110,7 +110,7 @@ public:
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private:
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virtual void machine_reset() override;
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virtual void machine_start() override;
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u8 applix_inputs_r();
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u16 applix_inputs_r();
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void palette_w(offs_t offset, u16 data, u16 mem_mask = ~0);
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void analog_latch_w(u16 data);
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void dac_latch_w(u16 data);
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@ -272,7 +272,7 @@ d1 = cassette in
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d2,3 = joystick in
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d4-7 = SW2 dipswitch block
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*/
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u8 applix_state::applix_inputs_r()
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u16 applix_state::applix_inputs_r()
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{
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return m_io_dsw->read() | m_cass_data[2];
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}
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@ -112,7 +112,7 @@ IRQ_CALLBACK_MEMBER(jack_state::jack_sh_irq_ack)
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/***************************************************************/
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READ8_MEMBER(jack_state::striv_question_r)
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uint8_t jack_state::striv_question_r(offs_t offset)
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{
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// Set-up the remap table for every 16 bytes
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if ((offset & 0xc00) == 0x800)
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@ -86,36 +86,36 @@ Address Dir Data Description
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*
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*************************************/
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READ8_MEMBER(jackal_state::jackalr_rotary_r)
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uint8_t jackal_state::jackalr_rotary_r(offs_t offset)
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{
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return (1 << m_dials[offset].read_safe(0x00)) ^ 0xff;
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}
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WRITE8_MEMBER(jackal_state::jackal_flipscreen_w)
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void jackal_state::jackal_flipscreen_w(uint8_t data)
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{
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m_irq_enable = data & 0x02;
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flip_screen_set(data & 0x08);
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}
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READ8_MEMBER(jackal_state::jackal_zram_r)
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uint8_t jackal_state::jackal_zram_r(offs_t offset)
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{
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return m_rambank[0x0020 + offset];
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}
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READ8_MEMBER(jackal_state::jackal_voram_r)
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uint8_t jackal_state::jackal_voram_r(offs_t offset)
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{
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return m_rambank[0x2000 + offset];
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}
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READ8_MEMBER(jackal_state::jackal_spriteram_r)
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uint8_t jackal_state::jackal_spriteram_r(offs_t offset)
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{
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return m_spritebank[0x3000 + offset];
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}
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WRITE8_MEMBER(jackal_state::jackal_rambank_w)
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void jackal_state::jackal_rambank_w(uint8_t data)
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{
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uint8_t *rgn = memregion("master")->base();
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@ -136,13 +136,13 @@ WRITE8_MEMBER(jackal_state::jackal_rambank_w)
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}
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WRITE8_MEMBER(jackal_state::jackal_zram_w)
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void jackal_state::jackal_zram_w(offs_t offset, uint8_t data)
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{
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m_rambank[0x0020 + offset] = data;
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}
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WRITE8_MEMBER(jackal_state::jackal_voram_w)
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void jackal_state::jackal_voram_w(offs_t offset, uint8_t data)
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{
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if ((offset & 0xf800) == 0)
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jackal_mark_tile_dirty(offset & 0x3ff);
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@ -151,7 +151,7 @@ WRITE8_MEMBER(jackal_state::jackal_voram_w)
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}
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WRITE8_MEMBER(jackal_state::jackal_spriteram_w)
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void jackal_state::jackal_spriteram_w(offs_t offset, uint8_t data)
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{
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m_spritebank[0x3000 + offset] = data;
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}
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@ -565,7 +565,7 @@ static NVRAM_HANDLER( jaguar )
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}
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}
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*/
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WRITE32_MEMBER(jaguar_state::eeprom_w)
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void jaguar_state::eeprom_w(uint32_t data)
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{
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m_eeprom_bit_count++;
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if (m_eeprom_bit_count != 9) /* kill extra bit at end of address */
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@ -576,7 +576,7 @@ WRITE32_MEMBER(jaguar_state::eeprom_w)
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}
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}
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READ32_MEMBER(jaguar_state::eeprom_clk)
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uint32_t jaguar_state::eeprom_clk()
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{
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if (!machine().side_effects_disabled())
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{
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@ -586,7 +586,7 @@ READ32_MEMBER(jaguar_state::eeprom_clk)
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return 0;
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}
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READ32_MEMBER(jaguar_state::eeprom_cs)
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uint32_t jaguar_state::eeprom_cs()
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{
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if (!machine().side_effects_disabled())
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{
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@ -608,7 +608,7 @@ READ32_MEMBER(jaguar_state::eeprom_cs)
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*
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*************************************/
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READ32_MEMBER(jaguar_state::misc_control_r)
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uint32_t jaguar_state::misc_control_r()
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{
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/* D7 = board reset (low)
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D6 = audio must & reset (high)
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@ -621,7 +621,7 @@ READ32_MEMBER(jaguar_state::misc_control_r)
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}
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WRITE32_MEMBER(jaguar_state::misc_control_w)
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void jaguar_state::misc_control_w(offs_t offset, uint32_t data, uint32_t mem_mask)
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{
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logerror("%s:misc_control_w(%02X)\n", machine().describe_context(), data);
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@ -661,12 +661,12 @@ WRITE32_MEMBER(jaguar_state::misc_control_w)
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*
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*************************************/
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READ32_MEMBER(jaguar_state::gpuctrl_r)
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uint32_t jaguar_state::gpuctrl_r(offs_t offset, uint32_t mem_mask)
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{
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return m_gpu->iobus_r(offset, mem_mask);
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}
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WRITE32_MEMBER(jaguar_state::gpuctrl_w)
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void jaguar_state::gpuctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
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{
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m_gpu->iobus_w(offset, data, mem_mask);
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}
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@ -677,12 +677,12 @@ WRITE32_MEMBER(jaguar_state::gpuctrl_w)
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*
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*************************************/
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READ32_MEMBER(jaguar_state::dspctrl_r)
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uint32_t jaguar_state::dspctrl_r(offs_t offset, uint32_t mem_mask)
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{
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return m_dsp->iobus_r(offset, mem_mask);
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}
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WRITE32_MEMBER(jaguar_state::dspctrl_w)
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void jaguar_state::dspctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
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{
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m_dsp->iobus_w(offset, data, mem_mask);
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}
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@ -696,7 +696,7 @@ WRITE32_MEMBER(jaguar_state::dspctrl_w)
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*
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*************************************/
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READ32_MEMBER(jaguar_state::joystick_r)
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uint32_t jaguar_state::joystick_r()
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{
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uint16_t joystick_result = 0xfffe;
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uint16_t joybuts_result = 0xffef;
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@ -730,7 +730,7 @@ READ32_MEMBER(jaguar_state::joystick_r)
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return (joystick_result << 16) | joybuts_result;
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}
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WRITE32_MEMBER(jaguar_state::joystick_w)
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void jaguar_state::joystick_w(offs_t offset, uint32_t data, uint32_t mem_mask)
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{
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/*
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* 16 12 8 4 0
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@ -788,7 +788,7 @@ WRITE32_MEMBER(jaguar_state::joystick_w)
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*
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*************************************/
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WRITE32_MEMBER(jaguar_state::latch_w)
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void jaguar_state::latch_w(uint32_t data)
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{
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logerror("%08X:latch_w(%X)\n", m_maincpu->pcbase(), data);
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@ -811,7 +811,7 @@ WRITE32_MEMBER(jaguar_state::latch_w)
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*
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*************************************/
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READ32_MEMBER(jaguar_state::eeprom_data_r)
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uint32_t jaguar_state::eeprom_data_r(offs_t offset)
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{
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if (m_is_r3000)
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return m_nvram[offset] | 0xffffff00;
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@ -820,13 +820,13 @@ READ32_MEMBER(jaguar_state::eeprom_data_r)
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}
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WRITE32_MEMBER(jaguar_state::eeprom_enable_w)
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void jaguar_state::eeprom_enable_w(uint32_t data)
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{
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m_eeprom_enable = true;
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}
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WRITE32_MEMBER(jaguar_state::eeprom_data_w)
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void jaguar_state::eeprom_data_w(offs_t offset, uint32_t data)
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{
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// if (m_eeprom_enable)
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{
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@ -870,7 +870,7 @@ WRITE32_MEMBER(jaguar_state::eeprom_data_w)
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*/
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WRITE32_MEMBER(jaguar_state::gpu_jump_w)
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void jaguar_state::gpu_jump_w(offs_t offset, uint32_t data, uint32_t mem_mask)
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{
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/* update the data in memory */
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COMBINE_DATA(m_gpu_jump_address);
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@ -885,7 +885,7 @@ WRITE32_MEMBER(jaguar_state::gpu_jump_w)
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}
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READ32_MEMBER(jaguar_state::gpu_jump_r)
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uint32_t jaguar_state::gpu_jump_r()
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{
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/* if the current GPU command is just pointing back to the spin loop, and */
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/* we're reading it from the spin loop, we can optimize */
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@ -926,7 +926,7 @@ READ32_MEMBER(jaguar_state::gpu_jump_r)
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#if ENABLE_SPEEDUP_HACKS
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READ32_MEMBER(jaguar_state::cojagr3k_main_speedup_r)
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uint32_t jaguar_state::cojagr3k_main_speedup_r()
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{
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uint64_t curcycles = m_maincpu->total_cycles();
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@ -974,7 +974,7 @@ READ32_MEMBER(jaguar_state::cojagr3k_main_speedup_r)
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#if ENABLE_SPEEDUP_HACKS
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READ32_MEMBER(jaguar_state::main_gpu_wait_r)
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uint32_t jaguar_state::main_gpu_wait_r()
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{
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if (m_gpu_command_pending)
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m_maincpu->spin_until_interrupt();
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@ -1000,7 +1000,7 @@ READ32_MEMBER(jaguar_state::main_gpu_wait_r)
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#if ENABLE_SPEEDUP_HACKS
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WRITE32_MEMBER(jaguar_state::area51_main_speedup_w)
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void jaguar_state::area51_main_speedup_w(offs_t offset, uint32_t data, uint32_t mem_mask)
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{
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uint64_t curcycles = m_maincpu->total_cycles();
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@ -1034,7 +1034,7 @@ WRITE32_MEMBER(jaguar_state::area51_main_speedup_w)
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against 0 must handle that explicitly.
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*/
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WRITE32_MEMBER(jaguar_state::area51mx_main_speedup_w)
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void jaguar_state::area51mx_main_speedup_w(offs_t offset, uint32_t data, uint32_t mem_mask)
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{
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uint64_t curcycles = m_maincpu->total_cycles();
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@ -1072,41 +1072,41 @@ WRITE32_MEMBER(jaguar_state::area51mx_main_speedup_w)
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// surely these should be 16-bit natively if the standard Jaguar is driven by a plain 68k?
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// all these trampolines are not good for performance ;-)
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|
||||
READ16_MEMBER(jaguar_state::gpuctrl_r16){ if (!(offset&1)) { return gpuctrl_r(space, offset>>1, mem_mask<<16) >> 16; } else { return gpuctrl_r(space, offset>>1, mem_mask); } }
|
||||
WRITE16_MEMBER(jaguar_state::gpuctrl_w16){ if (!(offset&1)) { gpuctrl_w(space, offset>>1, data << 16, mem_mask << 16); } else { gpuctrl_w(space, offset>>1, data, mem_mask); } }
|
||||
READ16_MEMBER(jaguar_state::blitter_r16){ if (!(offset&1)) { return blitter_r(space, offset>>1, mem_mask<<16) >> 16; } else { return blitter_r(space, offset>>1, mem_mask); } }
|
||||
WRITE16_MEMBER(jaguar_state::blitter_w16){ if (!(offset&1)) { blitter_w(space, offset>>1, data << 16, mem_mask << 16); } else { blitter_w(space, offset>>1, data, mem_mask); } }
|
||||
READ16_MEMBER(jaguar_state::serial_r16){ if (!(offset&1)) { return serial_r(space, offset>>1, mem_mask<<16) >> 16; } else { return serial_r(space, offset>>1, mem_mask); } }
|
||||
WRITE16_MEMBER(jaguar_state::serial_w16){ if (!(offset&1)) { serial_w(space, offset>>1, data << 16, mem_mask << 16); } else { serial_w(space, offset>>1, data, mem_mask); } }
|
||||
READ16_MEMBER(jaguar_state::dspctrl_r16){ if (!(offset&1)) { return dspctrl_r(space, offset>>1, mem_mask<<16) >> 16; } else { return dspctrl_r(space, offset>>1, mem_mask); } }
|
||||
WRITE16_MEMBER(jaguar_state::dspctrl_w16){ if (!(offset&1)) { dspctrl_w(space, offset>>1, data << 16, mem_mask << 16); } else { dspctrl_w(space, offset>>1, data, mem_mask); } }
|
||||
READ16_MEMBER(jaguar_state::eeprom_cs16){ if (!(offset&1)) { return eeprom_cs(space, offset>>1, mem_mask<<16) >> 16; } else { return eeprom_cs(space, offset>>1, mem_mask); } }
|
||||
READ16_MEMBER(jaguar_state::eeprom_clk16){ if (!(offset&1)) { return eeprom_clk(space, offset>>1, mem_mask<<16) >> 16; } else { return eeprom_clk(space, offset>>1, mem_mask); } }
|
||||
WRITE16_MEMBER(jaguar_state::eeprom_w16){ if (!(offset&1)) { eeprom_w(space, offset>>1, data << 16, mem_mask << 16); } else { eeprom_w(space, offset>>1, data, mem_mask); } }
|
||||
READ16_MEMBER(jaguar_state::joystick_r16){ if (!(offset&1)) { return joystick_r(space, offset>>1, mem_mask<<16) >> 16; } else { return joystick_r(space, offset>>1, mem_mask); } }
|
||||
WRITE16_MEMBER(jaguar_state::joystick_w16){ if (!(offset&1)) { joystick_w(space, offset>>1, data << 16, mem_mask << 16); } else { joystick_w(space, offset>>1, data, mem_mask); } }
|
||||
uint16_t jaguar_state::gpuctrl_r16(offs_t offset, uint16_t mem_mask){ if (!(offset&1)) { return gpuctrl_r(offset>>1, mem_mask<<16) >> 16; } else { return gpuctrl_r(offset>>1, mem_mask); } }
|
||||
void jaguar_state::gpuctrl_w16(offs_t offset, uint16_t data, uint16_t mem_mask){ if (!(offset&1)) { gpuctrl_w(offset>>1, data << 16, mem_mask << 16); } else { gpuctrl_w(offset>>1, data, mem_mask); } }
|
||||
uint16_t jaguar_state::blitter_r16(offs_t offset, uint16_t mem_mask){ if (!(offset&1)) { return blitter_r(offset>>1, mem_mask<<16) >> 16; } else { return blitter_r(offset>>1, mem_mask); } }
|
||||
void jaguar_state::blitter_w16(offs_t offset, uint16_t data, uint16_t mem_mask){ if (!(offset&1)) { blitter_w(offset>>1, data << 16, mem_mask << 16); } else { blitter_w(offset>>1, data, mem_mask); } }
|
||||
uint16_t jaguar_state::serial_r16(offs_t offset){ if (!(offset&1)) { return serial_r(offset>>1) >> 16; } else { return serial_r(offset>>1); } }
|
||||
void jaguar_state::serial_w16(offs_t offset, uint16_t data){ if (!(offset&1)) { serial_w(offset>>1, data << 16); } else { serial_w(offset>>1, data); } }
|
||||
uint16_t jaguar_state::dspctrl_r16(offs_t offset, uint16_t mem_mask){ if (!(offset&1)) { return dspctrl_r(offset>>1, mem_mask<<16) >> 16; } else { return dspctrl_r(offset>>1, mem_mask); } }
|
||||
void jaguar_state::dspctrl_w16(offs_t offset, uint16_t data, uint16_t mem_mask){ if (!(offset&1)) { dspctrl_w(offset>>1, data << 16, mem_mask << 16); } else { dspctrl_w(offset>>1, data, mem_mask); } }
|
||||
uint16_t jaguar_state::eeprom_cs16(offs_t offset){ if (!(offset&1)) { return eeprom_cs() >> 16; } else { return eeprom_cs(); } }
|
||||
uint16_t jaguar_state::eeprom_clk16(offs_t offset){ if (!(offset&1)) { return eeprom_clk() >> 16; } else { return eeprom_clk(); } }
|
||||
void jaguar_state::eeprom_w16(offs_t offset, uint16_t data){ if (!(offset&1)) { eeprom_w(data << 16); } else { eeprom_w(data); } }
|
||||
uint16_t jaguar_state::joystick_r16(offs_t offset){ if (!(offset&1)) { return joystick_r() >> 16; } else { return joystick_r(); } }
|
||||
void jaguar_state::joystick_w16(offs_t offset, uint16_t data, uint16_t mem_mask){ if (!(offset&1)) { joystick_w(offset>>1, data << 16, mem_mask << 16); } else { joystick_w(offset>>1, data, mem_mask); } }
|
||||
|
||||
READ32_MEMBER(jaguar_state::shared_ram_r){ return m_shared_ram[offset]; }
|
||||
WRITE32_MEMBER(jaguar_state::shared_ram_w){ COMBINE_DATA(&m_shared_ram[offset]); }
|
||||
READ32_MEMBER(jaguar_state::rom_base_r){ return m_rom_base[offset*2+1] << 16 | m_rom_base[offset*2]; }
|
||||
READ32_MEMBER(jaguar_state::wave_rom_r){ return m_wave_rom[offset*2+1] << 16 | m_wave_rom[offset*2]; }
|
||||
READ32_MEMBER(jaguarcd_state::cd_bios_r){ return m_cd_bios[offset*2+1] << 16 | m_cd_bios[offset*2]; }
|
||||
READ32_MEMBER(jaguar_state::dsp_ram_r){ return m_dsp_ram[offset]; }
|
||||
WRITE32_MEMBER(jaguar_state::dsp_ram_w){ COMBINE_DATA(&m_dsp_ram[offset]); }
|
||||
READ32_MEMBER(jaguar_state::gpu_clut_r){ return m_gpu_clut[offset]; }
|
||||
WRITE32_MEMBER(jaguar_state::gpu_clut_w){ COMBINE_DATA(&m_gpu_clut[offset]); }
|
||||
READ32_MEMBER(jaguar_state::gpu_ram_r){ return m_gpu_ram[offset]; }
|
||||
WRITE32_MEMBER(jaguar_state::gpu_ram_w){ COMBINE_DATA(&m_gpu_ram[offset]); }
|
||||
uint32_t jaguar_state::shared_ram_r(offs_t offset){ return m_shared_ram[offset]; }
|
||||
void jaguar_state::shared_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask){ COMBINE_DATA(&m_shared_ram[offset]); }
|
||||
uint32_t jaguar_state::rom_base_r(offs_t offset){ return m_rom_base[offset*2+1] << 16 | m_rom_base[offset*2]; }
|
||||
uint32_t jaguar_state::wave_rom_r(offs_t offset){ return m_wave_rom[offset*2+1] << 16 | m_wave_rom[offset*2]; }
|
||||
uint32_t jaguarcd_state::cd_bios_r(offs_t offset){ return m_cd_bios[offset*2+1] << 16 | m_cd_bios[offset*2]; }
|
||||
uint32_t jaguar_state::dsp_ram_r(offs_t offset){ return m_dsp_ram[offset]; }
|
||||
void jaguar_state::dsp_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask){ COMBINE_DATA(&m_dsp_ram[offset]); }
|
||||
uint32_t jaguar_state::gpu_clut_r(offs_t offset){ return m_gpu_clut[offset]; }
|
||||
void jaguar_state::gpu_clut_w(offs_t offset, uint32_t data, uint32_t mem_mask){ COMBINE_DATA(&m_gpu_clut[offset]); }
|
||||
uint32_t jaguar_state::gpu_ram_r(offs_t offset){ return m_gpu_ram[offset]; }
|
||||
void jaguar_state::gpu_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask){ COMBINE_DATA(&m_gpu_ram[offset]); }
|
||||
|
||||
READ16_MEMBER(jaguar_state::shared_ram_r16){ if (!(offset&1)) { return shared_ram_r(space, offset>>1, mem_mask<<16) >> 16; } else { return shared_ram_r(space, offset>>1, mem_mask); } }
|
||||
WRITE16_MEMBER(jaguar_state::shared_ram_w16){ if (!(offset&1)) { shared_ram_w(space, offset>>1, data << 16, mem_mask << 16); } else { shared_ram_w(space, offset>>1, data, mem_mask); } }
|
||||
READ16_MEMBER(jaguar_state::cart_base_r16){ if (!(offset&1)) { return m_cart_base[offset>>1] >> 16; } else { return m_cart_base[offset>>1] & 0xffff; } }
|
||||
READ16_MEMBER(jaguar_state::dsp_ram_r16){ if (!(offset&1)) { return dsp_ram_r(space, offset>>1, mem_mask<<16) >> 16; } else { return dsp_ram_r(space, offset>>1, mem_mask); } }
|
||||
WRITE16_MEMBER(jaguar_state::dsp_ram_w16){ if (!(offset&1)) { dsp_ram_w(space, offset>>1, data << 16, mem_mask << 16); } else { dsp_ram_w(space, offset>>1, data, mem_mask); } }
|
||||
READ16_MEMBER(jaguar_state::gpu_clut_r16){ if (!(offset&1)) { return gpu_clut_r(space, offset>>1, mem_mask<<16) >> 16; } else { return gpu_clut_r(space, offset>>1, mem_mask); } }
|
||||
WRITE16_MEMBER(jaguar_state::gpu_clut_w16){ if (!(offset&1)) { gpu_clut_w(space, offset>>1, data << 16, mem_mask << 16); } else { gpu_clut_w(space, offset>>1, data, mem_mask); } }
|
||||
READ16_MEMBER(jaguar_state::gpu_ram_r16){ if (!(offset&1)) { return gpu_ram_r(space, offset>>1, mem_mask<<16) >> 16; } else { return gpu_ram_r(space, offset>>1, mem_mask); } }
|
||||
WRITE16_MEMBER(jaguar_state::gpu_ram_w16){ if (!(offset&1)) { gpu_ram_w(space, offset>>1, data << 16, mem_mask << 16); } else { gpu_ram_w(space, offset>>1, data, mem_mask); } }
|
||||
uint16_t jaguar_state::shared_ram_r16(offs_t offset){ if (!(offset&1)) { return shared_ram_r(offset>>1) >> 16; } else { return shared_ram_r(offset>>1); } }
|
||||
void jaguar_state::shared_ram_w16(offs_t offset, uint16_t data, uint16_t mem_mask){ if (!(offset&1)) { shared_ram_w(offset>>1, data << 16, mem_mask << 16); } else { shared_ram_w(offset>>1, data, mem_mask); } }
|
||||
uint16_t jaguar_state::cart_base_r16(offs_t offset){ if (!(offset&1)) { return m_cart_base[offset>>1] >> 16; } else { return m_cart_base[offset>>1] & 0xffff; } }
|
||||
uint16_t jaguar_state::dsp_ram_r16(offs_t offset){ if (!(offset&1)) { return dsp_ram_r(offset>>1) >> 16; } else { return dsp_ram_r(offset>>1); } }
|
||||
void jaguar_state::dsp_ram_w16(offs_t offset, uint16_t data, uint16_t mem_mask){ if (!(offset&1)) { dsp_ram_w(offset>>1, data << 16, mem_mask << 16); } else { dsp_ram_w(offset>>1, data, mem_mask); } }
|
||||
uint16_t jaguar_state::gpu_clut_r16(offs_t offset){ if (!(offset&1)) { return gpu_clut_r(offset>>1) >> 16; } else { return gpu_clut_r(offset>>1); } }
|
||||
void jaguar_state::gpu_clut_w16(offs_t offset, uint16_t data, uint16_t mem_mask){ if (!(offset&1)) { gpu_clut_w(offset>>1, data << 16, mem_mask << 16); } else { gpu_clut_w(offset>>1, data, mem_mask); } }
|
||||
uint16_t jaguar_state::gpu_ram_r16(offs_t offset){ if (!(offset&1)) { return gpu_ram_r(offset>>1) >> 16; } else { return gpu_ram_r(offset>>1); } }
|
||||
void jaguar_state::gpu_ram_w16(offs_t offset, uint16_t data, uint16_t mem_mask){ if (!(offset&1)) { gpu_ram_w(offset>>1, data << 16, mem_mask << 16); } else { gpu_ram_w(offset>>1, data, mem_mask); } }
|
||||
|
||||
void jaguar_state::console_base_map(address_map &map)
|
||||
{
|
||||
@ -1207,10 +1207,10 @@ TODO: this needs to be device-ized, of course ...
|
||||
|
||||
*/
|
||||
|
||||
READ16_MEMBER(jaguarcd_state::butch_regs_r16){ if (!(offset&1)) { return butch_regs_r(space, offset>>1, mem_mask<<16) >> 16; } else { return butch_regs_r(space, offset>>1, mem_mask); } }
|
||||
WRITE16_MEMBER(jaguarcd_state::butch_regs_w16){ if (!(offset&1)) { butch_regs_w(space, offset>>1, data << 16, mem_mask << 16); } else { butch_regs_w(space, offset>>1, data, mem_mask); } }
|
||||
uint16_t jaguarcd_state::butch_regs_r16(offs_t offset){ if (!(offset&1)) { return butch_regs_r(offset>>1) >> 16; } else { return butch_regs_r(offset>>1); } }
|
||||
void jaguarcd_state::butch_regs_w16(offs_t offset, uint16_t data, uint16_t mem_mask){ if (!(offset&1)) { butch_regs_w(offset>>1, data << 16, mem_mask << 16); } else { butch_regs_w(offset>>1, data, mem_mask); } }
|
||||
|
||||
READ32_MEMBER(jaguarcd_state::butch_regs_r)
|
||||
uint32_t jaguarcd_state::butch_regs_r(offs_t offset)
|
||||
{
|
||||
switch(offset*4)
|
||||
{
|
||||
@ -1222,7 +1222,7 @@ READ32_MEMBER(jaguarcd_state::butch_regs_r)
|
||||
return m_butch_regs[offset];
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(jaguarcd_state::butch_regs_w)
|
||||
void jaguarcd_state::butch_regs_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_butch_regs[offset]);
|
||||
|
||||
@ -2491,10 +2491,10 @@ void jaguar_state::cojag_common_init(uint16_t gpu_jump_offs, uint16_t spin_pc)
|
||||
|
||||
/* install synchronization hooks for GPU */
|
||||
if (m_is_r3000)
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x04f0b000 + gpu_jump_offs, 0x04f0b003 + gpu_jump_offs, write32_delegate(*this, FUNC(jaguar_state::gpu_jump_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x04f0b000 + gpu_jump_offs, 0x04f0b003 + gpu_jump_offs, write32s_delegate(*this, FUNC(jaguar_state::gpu_jump_w)));
|
||||
else
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xf0b000 + gpu_jump_offs, 0xf0b003 + gpu_jump_offs, write32_delegate(*this, FUNC(jaguar_state::gpu_jump_w)));
|
||||
m_gpu->space(AS_PROGRAM).install_read_handler(0xf03000 + gpu_jump_offs, 0xf03003 + gpu_jump_offs, read32_delegate(*this, FUNC(jaguar_state::gpu_jump_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xf0b000 + gpu_jump_offs, 0xf0b003 + gpu_jump_offs, write32s_delegate(*this, FUNC(jaguar_state::gpu_jump_w)));
|
||||
m_gpu->space(AS_PROGRAM).install_read_handler(0xf03000 + gpu_jump_offs, 0xf03003 + gpu_jump_offs, read32smo_delegate(*this, FUNC(jaguar_state::gpu_jump_r)));
|
||||
m_gpu_jump_address = &m_gpu_ram[gpu_jump_offs/4];
|
||||
m_gpu_spin_pc = 0xf03000 + spin_pc;
|
||||
}
|
||||
@ -2507,7 +2507,7 @@ void jaguar_state::init_area51a()
|
||||
|
||||
#if ENABLE_SPEEDUP_HACKS
|
||||
/* install speedup for main CPU */
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xa02030, 0xa02033, write32_delegate(*this, FUNC(jaguar_state::area51_main_speedup_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xa02030, 0xa02033, write32s_delegate(*this, FUNC(jaguar_state::area51_main_speedup_w)));
|
||||
m_main_speedup = m_mainram + 0x2030/4;
|
||||
#endif
|
||||
}
|
||||
@ -2520,7 +2520,7 @@ void jaguar_state::init_area51()
|
||||
#if ENABLE_SPEEDUP_HACKS
|
||||
/* install speedup for main CPU */
|
||||
m_main_speedup_max_cycles = 120;
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x100062e8, 0x100062eb, read32_delegate(*this, FUNC(jaguar_state::cojagr3k_main_speedup_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x100062e8, 0x100062eb, read32smo_delegate(*this, FUNC(jaguar_state::cojagr3k_main_speedup_r)));
|
||||
m_main_speedup = m_mainram + 0x62e8/4;
|
||||
#endif
|
||||
}
|
||||
@ -2536,7 +2536,7 @@ void jaguar_state::init_maxforce()
|
||||
#if ENABLE_SPEEDUP_HACKS
|
||||
/* install speedup for main CPU */
|
||||
m_main_speedup_max_cycles = 120;
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x1000865c, 0x1000865f, read32_delegate(*this, FUNC(jaguar_state::cojagr3k_main_speedup_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x1000865c, 0x1000865f, read32smo_delegate(*this, FUNC(jaguar_state::cojagr3k_main_speedup_r)));
|
||||
m_main_speedup = m_mainram + 0x865c/4;
|
||||
#endif
|
||||
}
|
||||
@ -2552,7 +2552,7 @@ void jaguar_state::init_area51mx()
|
||||
|
||||
#if ENABLE_SPEEDUP_HACKS
|
||||
/* install speedup for main CPU */
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xa19550, 0xa19557, write32_delegate(*this, FUNC(jaguar_state::area51mx_main_speedup_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xa19550, 0xa19557, write32s_delegate(*this, FUNC(jaguar_state::area51mx_main_speedup_w)));
|
||||
m_main_speedup = m_mainram + 0x19550/4;
|
||||
#endif
|
||||
}
|
||||
@ -2569,7 +2569,7 @@ void jaguar_state::init_a51mxr3k()
|
||||
#if ENABLE_SPEEDUP_HACKS
|
||||
/* install speedup for main CPU */
|
||||
m_main_speedup_max_cycles = 120;
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x10006f0c, 0x10006f0f, read32_delegate(*this, FUNC(jaguar_state::cojagr3k_main_speedup_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x10006f0c, 0x10006f0f, read32smo_delegate(*this, FUNC(jaguar_state::cojagr3k_main_speedup_r)));
|
||||
m_main_speedup = m_mainram + 0x6f0c/4;
|
||||
#endif
|
||||
}
|
||||
@ -2583,7 +2583,7 @@ void jaguar_state::init_fishfren()
|
||||
#if ENABLE_SPEEDUP_HACKS
|
||||
/* install speedup for main CPU */
|
||||
m_main_speedup_max_cycles = 200;
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x10021b60, 0x10021b63, read32_delegate(*this, FUNC(jaguar_state::cojagr3k_main_speedup_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x10021b60, 0x10021b63, read32smo_delegate(*this, FUNC(jaguar_state::cojagr3k_main_speedup_r)));
|
||||
m_main_speedup = m_mainram + 0x21b60/4;
|
||||
#endif
|
||||
}
|
||||
@ -2597,10 +2597,10 @@ void jaguar_state::init_freeze_common(offs_t main_speedup_addr)
|
||||
/* install speedup for main CPU */
|
||||
m_main_speedup_max_cycles = 200;
|
||||
if (main_speedup_addr != 0) {
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(main_speedup_addr, main_speedup_addr + 3, read32_delegate(*this, FUNC(jaguar_state::cojagr3k_main_speedup_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(main_speedup_addr, main_speedup_addr + 3, read32smo_delegate(*this, FUNC(jaguar_state::cojagr3k_main_speedup_r)));
|
||||
m_main_speedup = m_mainram + (main_speedup_addr - 0x10000000)/4;
|
||||
}
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x0400d900, 0x0400d900 + 3, read32_delegate(*this, FUNC(jaguar_state::main_gpu_wait_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x0400d900, 0x0400d900 + 3, read32smo_delegate(*this, FUNC(jaguar_state::main_gpu_wait_r)));
|
||||
m_main_gpu_wait = m_shared_ram + 0xd900/4;
|
||||
#endif
|
||||
}
|
||||
@ -2620,7 +2620,7 @@ void jaguar_state::init_vcircle()
|
||||
#if ENABLE_SPEEDUP_HACKS
|
||||
/* install speedup for main CPU */
|
||||
m_main_speedup_max_cycles = 50;
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x12005b34, 0x12005b37, read32_delegate(*this, FUNC(jaguar_state::cojagr3k_main_speedup_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x12005b34, 0x12005b37, read32smo_delegate(*this, FUNC(jaguar_state::cojagr3k_main_speedup_r)));
|
||||
m_main_speedup = m_mainram + 0x5b34/4;
|
||||
m_main_speedup = m_mainram2 + 0x5b34/4;
|
||||
#endif
|
||||
|
@ -98,14 +98,14 @@ Notes:
|
||||
#include "speaker.h"
|
||||
|
||||
|
||||
WRITE8_MEMBER(jailbrek_state::ctrl_w)
|
||||
void jailbrek_state::ctrl_w(uint8_t data)
|
||||
{
|
||||
m_nmi_enable = data & 0x01;
|
||||
m_irq_enable = data & 0x02;
|
||||
flip_screen_set(data & 0x08);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(jailbrek_state::coin_w)
|
||||
void jailbrek_state::coin_w(uint8_t data)
|
||||
{
|
||||
machine().bookkeeping().coin_counter_w(0, data & 0x01);
|
||||
machine().bookkeeping().coin_counter_w(1, data & 0x02);
|
||||
@ -124,12 +124,12 @@ INTERRUPT_GEN_MEMBER(jailbrek_state::interrupt_nmi)
|
||||
}
|
||||
|
||||
|
||||
READ8_MEMBER(jailbrek_state::speech_r)
|
||||
uint8_t jailbrek_state::speech_r()
|
||||
{
|
||||
return (m_vlm->bsy() ? 1 : 0);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(jailbrek_state::speech_w)
|
||||
void jailbrek_state::speech_w(uint8_t data)
|
||||
{
|
||||
/* bit 0 could be latch direction like in yiear */
|
||||
m_vlm->st((data >> 1) & 1);
|
||||
|
@ -217,13 +217,13 @@ WRITE_LINE_MEMBER(jedi_state::coin_counter_right_w)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ8_MEMBER(jedi_state::novram_data_r)
|
||||
u8 jedi_state::novram_data_r(address_space &space, offs_t offset)
|
||||
{
|
||||
return (m_novram[0]->read(space, offset) & 0x0f) | (m_novram[1]->read(space, offset) << 4);
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER(jedi_state::novram_data_w)
|
||||
void jedi_state::novram_data_w(offs_t offset, u8 data)
|
||||
{
|
||||
m_novram[0]->write(offset, data & 0x0f);
|
||||
m_novram[1]->write(offset, data >> 4);
|
||||
|
@ -210,7 +210,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(jpmimpct_state::duart_1_timer_event)
|
||||
update_irqs();
|
||||
}
|
||||
|
||||
READ16_MEMBER(jpmimpct_state::duart_1_r)
|
||||
uint16_t jpmimpct_state::duart_1_r(offs_t offset)
|
||||
{
|
||||
struct duart_t &duart_1 = m_duart_1;
|
||||
uint16_t val = 0xffff;
|
||||
@ -274,7 +274,7 @@ READ16_MEMBER(jpmimpct_state::duart_1_r)
|
||||
return val;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(jpmimpct_state::duart_1_w)
|
||||
void jpmimpct_state::duart_1_w(offs_t offset, uint16_t data)
|
||||
{
|
||||
struct duart_t &duart_1 = m_duart_1;
|
||||
//int old_val;
|
||||
@ -360,7 +360,7 @@ WRITE16_MEMBER(jpmimpct_state::duart_1_w)
|
||||
Communication with a touchscreen interface PCB
|
||||
is handled via UART B.
|
||||
*/
|
||||
READ16_MEMBER(jpmimpct_state::duart_2_r)
|
||||
uint16_t jpmimpct_state::duart_2_r(offs_t offset)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
@ -401,7 +401,7 @@ READ16_MEMBER(jpmimpct_state::duart_2_r)
|
||||
/*
|
||||
Nothing important here?
|
||||
*/
|
||||
WRITE16_MEMBER(jpmimpct_state::duart_2_w)
|
||||
void jpmimpct_state::duart_2_w(uint16_t data)
|
||||
{
|
||||
}
|
||||
|
||||
@ -428,7 +428,7 @@ WRITE16_MEMBER(jpmimpct_state::duart_2_w)
|
||||
* 9: Coin mechanism
|
||||
*/
|
||||
|
||||
READ16_MEMBER(jpmimpct_state::inputs1_r)
|
||||
uint16_t jpmimpct_state::inputs1_r(offs_t offset)
|
||||
{
|
||||
uint16_t val = 0x00ff;
|
||||
|
||||
@ -465,7 +465,7 @@ READ16_MEMBER(jpmimpct_state::inputs1_r)
|
||||
* Sound control
|
||||
*
|
||||
*************************************/
|
||||
WRITE16_MEMBER(jpmimpct_state::volume_w)
|
||||
void jpmimpct_state::volume_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_0_7)
|
||||
{
|
||||
@ -474,7 +474,7 @@ WRITE16_MEMBER(jpmimpct_state::volume_w)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(jpmimpct_state::upd7759_w)
|
||||
void jpmimpct_state::upd7759_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_0_7)
|
||||
{
|
||||
@ -484,7 +484,7 @@ WRITE16_MEMBER(jpmimpct_state::upd7759_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(jpmimpct_state::upd7759_r)
|
||||
uint16_t jpmimpct_state::upd7759_r(offs_t offset, uint16_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_0_7)
|
||||
{
|
||||
@ -500,12 +500,12 @@ READ16_MEMBER(jpmimpct_state::upd7759_r)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ16_MEMBER(jpmimpct_state::unk_r)
|
||||
uint16_t jpmimpct_state::unk_r()
|
||||
{
|
||||
return 0xffff;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(jpmimpct_state::unk_w)
|
||||
void jpmimpct_state::unk_w(uint16_t data)
|
||||
{
|
||||
}
|
||||
|
||||
@ -520,12 +520,12 @@ void jpmimpct_state::jpm_draw_lamps(int data, int lamp_strobe)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(jpmimpct_state::jpmio_r)
|
||||
uint16_t jpmimpct_state::jpmio_r()
|
||||
{
|
||||
return 0xffff;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(jpmimpct_state::jpmio_w)
|
||||
void jpmimpct_state::jpmio_w(offs_t offset, uint16_t data)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
@ -1003,7 +1003,7 @@ MACHINE_RESET_MEMBER(jpmimpct_state,impctawp)
|
||||
* 8: Payslides
|
||||
* 9: Coin mechanism
|
||||
*/
|
||||
READ16_MEMBER(jpmimpct_state::inputs1awp_r)
|
||||
uint16_t jpmimpct_state::inputs1awp_r(offs_t offset)
|
||||
{
|
||||
uint16_t val = 0x00;
|
||||
|
||||
@ -1060,22 +1060,22 @@ READ16_MEMBER(jpmimpct_state::inputs1awp_r)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(jpmimpct_state::optos_r)
|
||||
uint16_t jpmimpct_state::optos_r()
|
||||
{
|
||||
return m_optic_pattern;
|
||||
}
|
||||
|
||||
READ16_MEMBER(jpmimpct_state::prot_1_r)
|
||||
uint16_t jpmimpct_state::prot_1_r()
|
||||
{
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
READ16_MEMBER(jpmimpct_state::prot_0_r)
|
||||
uint16_t jpmimpct_state::prot_0_r()
|
||||
{
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(jpmimpct_state::jpmioawp_w)
|
||||
void jpmimpct_state::jpmioawp_w(offs_t offset, uint16_t data)
|
||||
{
|
||||
int i,metno;
|
||||
switch (offset)
|
||||
@ -1176,7 +1176,7 @@ WRITE16_MEMBER(jpmimpct_state::jpmioawp_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(jpmimpct_state::ump_r)
|
||||
uint16_t jpmimpct_state::ump_r()
|
||||
{
|
||||
return 0xff;//0xffff;
|
||||
}
|
||||
|
@ -74,7 +74,7 @@ WRITE_LINE_MEMBER(jpmsys5v_state::generate_tms34061_interrupt)
|
||||
m_maincpu->set_input_line(INT_TMS34061, state);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(jpmsys5v_state::sys5_tms34061_w)
|
||||
void jpmsys5v_state::sys5_tms34061_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
int func = (offset >> 19) & 3;
|
||||
int row = (offset >> 7) & 0x1ff;
|
||||
@ -97,7 +97,7 @@ WRITE16_MEMBER(jpmsys5v_state::sys5_tms34061_w)
|
||||
m_tms34061->write(col | 1, row, func, data & 0xff);
|
||||
}
|
||||
|
||||
READ16_MEMBER(jpmsys5v_state::sys5_tms34061_r)
|
||||
uint16_t jpmsys5v_state::sys5_tms34061_r(offs_t offset, uint16_t mem_mask)
|
||||
{
|
||||
uint16_t data = 0;
|
||||
int func = (offset >> 19) & 3;
|
||||
@ -123,7 +123,7 @@ READ16_MEMBER(jpmsys5v_state::sys5_tms34061_r)
|
||||
return data;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(jpmsys5v_state::ramdac_w)
|
||||
void jpmsys5v_state::ramdac_w(offs_t offset, uint16_t data)
|
||||
{
|
||||
if (offset == 0)
|
||||
{
|
||||
@ -194,12 +194,12 @@ void jpmsys5_state::sys5_draw_lamps()
|
||||
*
|
||||
****************************************/
|
||||
|
||||
WRITE16_MEMBER(jpmsys5v_state::rombank_w)
|
||||
void jpmsys5v_state::rombank_w(uint16_t data)
|
||||
{
|
||||
m_rombank->set_entry(data & 0x1f);
|
||||
}
|
||||
|
||||
READ16_MEMBER(jpmsys5_state::coins_r)
|
||||
uint16_t jpmsys5_state::coins_r(offs_t offset)
|
||||
{
|
||||
if (offset == 2)
|
||||
return ioport("COINS")->read() << 8;
|
||||
@ -207,22 +207,22 @@ READ16_MEMBER(jpmsys5_state::coins_r)
|
||||
return 0xffff;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(jpmsys5_state::coins_w)
|
||||
void jpmsys5_state::coins_w(uint16_t data)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
READ16_MEMBER(jpmsys5_state::unk_r)
|
||||
uint16_t jpmsys5_state::unk_r()
|
||||
{
|
||||
return 0xffff;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(jpmsys5_state::mux_w)
|
||||
void jpmsys5_state::mux_w(offs_t offset, uint16_t data)
|
||||
{
|
||||
m_muxram[offset]=data;
|
||||
}
|
||||
|
||||
READ16_MEMBER(jpmsys5_state::mux_r)
|
||||
uint16_t jpmsys5_state::mux_r(offs_t offset)
|
||||
{
|
||||
if (offset == 0x81/2)
|
||||
return ioport("DSW")->read();
|
||||
@ -230,7 +230,7 @@ READ16_MEMBER(jpmsys5_state::mux_r)
|
||||
return 0xffff;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(jpmsys5_state::jpm_upd7759_w)
|
||||
void jpmsys5_state::jpm_upd7759_w(offs_t offset, uint16_t data)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
@ -263,7 +263,7 @@ WRITE16_MEMBER(jpmsys5_state::jpm_upd7759_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(jpmsys5_state::jpm_upd7759_r)
|
||||
uint16_t jpmsys5_state::jpm_upd7759_r()
|
||||
{
|
||||
return 0x14 | m_upd7759->busy_r();
|
||||
}
|
||||
@ -647,7 +647,7 @@ void jpmsys5v_state::jpmsys5v(machine_config &config)
|
||||
ptm.irq_callback().set(FUNC(jpmsys5v_state::ptm_irq));
|
||||
}
|
||||
|
||||
READ16_MEMBER(jpmsys5_state::mux_awp_r)
|
||||
uint16_t jpmsys5_state::mux_awp_r(offs_t offset)
|
||||
{
|
||||
static const char *const portnames[] = { "DSW", "DSW2", "ROTARY", "STROBE0", "STROBE1", "STROBE2", "STROBE3", "STROBE4" };
|
||||
|
||||
@ -661,7 +661,7 @@ READ16_MEMBER(jpmsys5_state::mux_awp_r)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(jpmsys5_state::coins_awp_r)
|
||||
uint16_t jpmsys5_state::coins_awp_r(offs_t offset)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
|
@ -185,7 +185,7 @@ void kangaroo_state::machine_start()
|
||||
MACHINE_START_MEMBER(kangaroo_state,kangaroo_mcu)
|
||||
{
|
||||
kangaroo_state::machine_start();
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xef00, 0xefff, read8_delegate(*this, FUNC(kangaroo_state::mcu_sim_r)), write8_delegate(*this, FUNC(kangaroo_state::mcu_sim_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xef00, 0xefff, read8smo_delegate(*this, FUNC(kangaroo_state::mcu_sim_r)), write8smo_delegate(*this, FUNC(kangaroo_state::mcu_sim_w)));
|
||||
save_item(NAME(m_mcu_clock));
|
||||
}
|
||||
|
||||
@ -220,12 +220,12 @@ void kangaroo_state::machine_reset()
|
||||
this just seems to do the trick -V-
|
||||
*/
|
||||
|
||||
READ8_MEMBER(kangaroo_state::mcu_sim_r)
|
||||
uint8_t kangaroo_state::mcu_sim_r()
|
||||
{
|
||||
return ++m_mcu_clock & 0x0f;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(kangaroo_state::mcu_sim_w)
|
||||
void kangaroo_state::mcu_sim_w(uint8_t data)
|
||||
{
|
||||
}
|
||||
|
||||
@ -237,7 +237,7 @@ WRITE8_MEMBER(kangaroo_state::mcu_sim_w)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
WRITE8_MEMBER(kangaroo_state::kangaroo_coin_counter_w)
|
||||
void kangaroo_state::kangaroo_coin_counter_w(uint8_t data)
|
||||
{
|
||||
machine().bookkeeping().coin_counter_w(0, data & 1);
|
||||
machine().bookkeeping().coin_counter_w(1, data & 2);
|
||||
|
@ -305,7 +305,7 @@ void karnov_state::wndrplnt_i8751_w( int data )
|
||||
*
|
||||
*************************************/
|
||||
|
||||
WRITE16_MEMBER(karnov_state::mcusim_ack_w)
|
||||
void karnov_state::mcusim_ack_w(u16 data)
|
||||
{
|
||||
m_maincpu->set_input_line(6, CLEAR_LINE);
|
||||
|
||||
@ -345,7 +345,7 @@ void karnov_state::mcusim_w(u16 data)
|
||||
wndrplnt_i8751_w(data);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(karnov_state::mcusim_reset_w)
|
||||
void karnov_state::mcusim_reset_w(u16 data)
|
||||
{
|
||||
logerror("Reset i8751\n");
|
||||
m_i8751_needs_ack = 0;
|
||||
@ -354,7 +354,7 @@ WRITE16_MEMBER(karnov_state::mcusim_reset_w)
|
||||
m_i8751_return = 0;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(karnov_state::vint_ack_w)
|
||||
void karnov_state::vint_ack_w(u16 data)
|
||||
{
|
||||
m_maincpu->set_input_line(7, CLEAR_LINE);
|
||||
}
|
||||
|
@ -56,7 +56,7 @@
|
||||
#include "speaker.h"
|
||||
|
||||
|
||||
READ8_MEMBER( kaypro_state::kaypro484_87_r ) { return 0x7f; } /* to bypass unemulated HD controller */
|
||||
uint8_t kaypro_state::kaypro484_87_r() { return 0x7f; } /* to bypass unemulated HD controller */
|
||||
|
||||
/***********************************************************
|
||||
|
||||
|
@ -150,14 +150,14 @@ void kchamp_state::kchampvs_sound_io_map(address_map &map)
|
||||
/********************
|
||||
* 1 Player Version *
|
||||
********************/
|
||||
READ8_MEMBER(kchamp_state::sound_reset_r)
|
||||
uint8_t kchamp_state::sound_reset_r()
|
||||
{
|
||||
if (!machine().side_effects_disabled())
|
||||
m_audiocpu->pulse_input_line(INPUT_LINE_RESET, attotime::zero);
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(kchamp_state::kc_sound_control_w)
|
||||
void kchamp_state::kc_sound_control_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
if (offset == 0)
|
||||
{
|
||||
|
@ -83,7 +83,7 @@ Action Hollywood
|
||||
*/
|
||||
|
||||
|
||||
WRITE16_MEMBER(kickgoal_state::actionhw_snd_w)
|
||||
void kickgoal_state::actionhw_snd_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
logerror("%s: Writing %04x to Sound CPU - mask %04x\n",machine().describe_context(),data,mem_mask);
|
||||
|
||||
@ -351,7 +351,7 @@ void kickgoal_state::oki_map(address_map &map)
|
||||
}
|
||||
|
||||
|
||||
void kickgoal_state::soundio_port_a_w(uint8_t data)
|
||||
void kickgoal_state::soundio_port_a_w(u8 data)
|
||||
{
|
||||
// only time this ever gets a different value is the high score name entry, these banks are correct based on sample positions
|
||||
switch (data)
|
||||
@ -362,23 +362,23 @@ void kickgoal_state::soundio_port_a_w(uint8_t data)
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t kickgoal_state::soundio_port_b_r()
|
||||
u8 kickgoal_state::soundio_port_b_r()
|
||||
{
|
||||
return m_pic_portb;
|
||||
}
|
||||
|
||||
void kickgoal_state::soundio_port_b_w(uint8_t data)
|
||||
void kickgoal_state::soundio_port_b_w(u8 data)
|
||||
{
|
||||
m_pic_portb = data;
|
||||
}
|
||||
|
||||
uint8_t kickgoal_state::soundio_port_c_r()
|
||||
u8 kickgoal_state::soundio_port_c_r()
|
||||
{
|
||||
// 0x20 = sound command ready?
|
||||
return (m_pic_portc & ~0x20) | m_sound_command_sent;
|
||||
}
|
||||
|
||||
void kickgoal_state::soundio_port_c_w(uint8_t data)
|
||||
void kickgoal_state::soundio_port_c_w(u8 data)
|
||||
{
|
||||
if ((data & 0x10) != (m_pic_portc & 0x10))
|
||||
{
|
||||
@ -409,7 +409,7 @@ void kickgoal_state::soundio_port_c_w(uint8_t data)
|
||||
}
|
||||
|
||||
|
||||
WRITE16_MEMBER(kickgoal_state::to_pic_w)
|
||||
void kickgoal_state::to_pic_w(u16 data)
|
||||
{
|
||||
m_soundlatch->write(data);
|
||||
m_sound_command_sent = 0x20;
|
||||
@ -578,7 +578,7 @@ void kickgoal_state::init_kickgoal()
|
||||
|
||||
void kickgoal_state::init_actionhw()
|
||||
{
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x800004, 0x800005, write16_delegate(*this, FUNC(kickgoal_state::actionhw_snd_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x800004, 0x800005, write16s_delegate(*this, FUNC(kickgoal_state::actionhw_snd_w)));
|
||||
}
|
||||
|
||||
GAME( 1995, kickgoal, 0, kickgoal, kickgoal, kickgoal_state, init_kickgoal, ROT0, "TCH", "Kick Goal (set 1)", MACHINE_SUPPORTS_SAVE )
|
||||
|
@ -69,7 +69,7 @@ PS4 J8635 PS4 J8541 PS4 J8648
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ8_MEMBER(kikikai_state::kiki_ym2203_r)
|
||||
uint8_t kikikai_state::kiki_ym2203_r(offs_t offset)
|
||||
{
|
||||
u8 result = m_ymsnd->read(offset);
|
||||
|
||||
@ -108,7 +108,7 @@ void kikikai_state::sound_map(address_map &map)
|
||||
map(0xc000, 0xc001).r(FUNC(kikikai_state::kiki_ym2203_r)).w(m_ymsnd, FUNC(ym2203_device::write));
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(kikikai_state::kicknrun_sub_output_w)
|
||||
void kikikai_state::kicknrun_sub_output_w(uint8_t data)
|
||||
{
|
||||
/*--x- ---- coin lockout 2*/
|
||||
/*---x ---- coin lockout 1*/
|
||||
|
@ -363,7 +363,7 @@ void konamigx_state::daiskiss_esc(address_space &space, uint32_t p1, uint32_t p2
|
||||
generate_sprites(space, 0xc00000, 0xd20000, 0x100);
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(konamigx_state::esc_w)
|
||||
void konamigx_state::esc_w(address_space &space, uint32_t data)
|
||||
{
|
||||
uint32_t opcode;
|
||||
uint32_t params;
|
||||
@ -453,7 +453,7 @@ CUSTOM_INPUT_MEMBER(konamigx_state::gx_rdport1_3_r)
|
||||
return (m_gx_rdport1_3 >> 1);
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(konamigx_state::eeprom_w)
|
||||
void konamigx_state::eeprom_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
uint32_t odata;
|
||||
|
||||
@ -501,7 +501,7 @@ WRITE32_MEMBER(konamigx_state::eeprom_w)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(konamigx_state::control_w)
|
||||
void konamigx_state::control_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
// TODO: derive from reported PCB XTALs
|
||||
const uint32_t pixclock[4] = { 6'000'000, 8'000'000, 12'000'000, 16'000'000 };
|
||||
@ -735,7 +735,7 @@ double konamigx_state::adc0834_callback(uint8_t input)
|
||||
}
|
||||
|
||||
|
||||
READ32_MEMBER(konamigx_state::le2_gun_H_r)
|
||||
uint32_t konamigx_state::le2_gun_H_r()
|
||||
{
|
||||
int p1x = m_light0_x->read()*290/0xff+20;
|
||||
int p2x = m_light1_x->read()*290/0xff+20;
|
||||
@ -743,7 +743,7 @@ READ32_MEMBER(konamigx_state::le2_gun_H_r)
|
||||
return (p1x<<16)|p2x;
|
||||
}
|
||||
|
||||
READ32_MEMBER(konamigx_state::le2_gun_V_r)
|
||||
uint32_t konamigx_state::le2_gun_V_r()
|
||||
{
|
||||
int p1y = m_light0_y->read()*224/0xff;
|
||||
int p2y = m_light1_y->read()*224/0xff;
|
||||
@ -758,14 +758,14 @@ READ32_MEMBER(konamigx_state::le2_gun_V_r)
|
||||
/**********************************************************************************/
|
||||
/* system or game dependent handlers */
|
||||
|
||||
READ32_MEMBER(konamigx_state::type1_roz_r1)
|
||||
uint32_t konamigx_state::type1_roz_r1(offs_t offset)
|
||||
{
|
||||
uint32_t *ROM = (uint32_t *)memregion("gfx3")->base();
|
||||
|
||||
return ROM[offset];
|
||||
}
|
||||
|
||||
READ32_MEMBER(konamigx_state::type1_roz_r2)
|
||||
uint32_t konamigx_state::type1_roz_r2(offs_t offset)
|
||||
{
|
||||
uint32_t *ROM = (uint32_t *)memregion("gfx3")->base();
|
||||
|
||||
@ -774,7 +774,7 @@ READ32_MEMBER(konamigx_state::type1_roz_r2)
|
||||
return ROM[offset];
|
||||
}
|
||||
|
||||
READ32_MEMBER(konamigx_state::type3_sync_r)
|
||||
uint32_t konamigx_state::type3_sync_r()
|
||||
{
|
||||
if(m_konamigx_current_frame==0)
|
||||
return -1; // return 0xfffffffe | 1;
|
||||
@ -859,7 +859,7 @@ READ32_MEMBER(konamigx_state::type3_sync_r)
|
||||
move.l #$C10400,($C102EC).l move.l #$C10400,($C102EC).l
|
||||
*/
|
||||
|
||||
WRITE32_MEMBER(konamigx_state::type4_prot_w)
|
||||
void konamigx_state::type4_prot_w(address_space &space, offs_t offset, uint32_t data)
|
||||
{
|
||||
int clk;
|
||||
int i;
|
||||
@ -1012,7 +1012,7 @@ WRITE32_MEMBER(konamigx_state::type4_prot_w)
|
||||
}
|
||||
|
||||
// cabinet lamps for type 1 games
|
||||
WRITE32_MEMBER(konamigx_state::type1_cablamps_w)
|
||||
void konamigx_state::type1_cablamps_w(uint32_t data)
|
||||
{
|
||||
m_lamp = BIT(data, 24);
|
||||
}
|
||||
@ -1118,14 +1118,14 @@ void konamigx_state::gx_type4_map(address_map &map)
|
||||
/**********************************************************************************/
|
||||
/* Sound handling */
|
||||
|
||||
READ16_MEMBER(konamigx_state::tms57002_status_word_r)
|
||||
uint16_t konamigx_state::tms57002_status_word_r()
|
||||
{
|
||||
return (m_dasp->dready_r() ? 4 : 0) |
|
||||
(m_dasp->pc0_r() ? 2 : 0) |
|
||||
(m_dasp->empty_r() ? 1 : 0);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(konamigx_state::tms57002_control_word_w)
|
||||
void konamigx_state::tms57002_control_word_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_0_7)
|
||||
{
|
||||
@ -3879,7 +3879,7 @@ static const GXGameInfoT gameDefs[] =
|
||||
{ "", 0xff,0xff,0xff },
|
||||
};
|
||||
|
||||
READ32_MEMBER( konamigx_state::k_6bpp_rom_long_r )
|
||||
uint32_t konamigx_state::k_6bpp_rom_long_r(offs_t offset, uint32_t mem_mask)
|
||||
{
|
||||
return m_k056832->k_6bpp_rom_long_r(offset, mem_mask);
|
||||
}
|
||||
@ -3908,8 +3908,8 @@ void konamigx_state::init_konamigx()
|
||||
switch (gameDefs[i].special)
|
||||
{
|
||||
case 1: // LE2 guns
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0xd44000, 0xd44003, read32_delegate(*this, FUNC(konamigx_state::le2_gun_H_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0xd44004, 0xd44007, read32_delegate(*this, FUNC(konamigx_state::le2_gun_V_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0xd44000, 0xd44003, read32smo_delegate(*this, FUNC(konamigx_state::le2_gun_H_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0xd44004, 0xd44007, read32smo_delegate(*this, FUNC(konamigx_state::le2_gun_V_r)));
|
||||
break;
|
||||
case 2: // tkmmpzdm hack
|
||||
{
|
||||
@ -3944,7 +3944,7 @@ void konamigx_state::init_konamigx()
|
||||
break;
|
||||
|
||||
case 7: // install type 4 Xilinx protection for non-type 3/4 games
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xcc0000, 0xcc0007, write32_delegate(*this, FUNC(konamigx_state::type4_prot_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xcc0000, 0xcc0007, write32m_delegate(*this, FUNC(konamigx_state::type4_prot_w)));
|
||||
break;
|
||||
|
||||
case 8: // tbyahhoo
|
||||
@ -3961,7 +3961,7 @@ void konamigx_state::init_konamigx()
|
||||
}
|
||||
|
||||
if (readback == BPP66)
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0xd00000, 0xd01fff, read32_delegate(*this, FUNC(konamigx_state::k_6bpp_rom_long_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0xd00000, 0xd01fff, read32s_delegate(*this, FUNC(konamigx_state::k_6bpp_rom_long_r)));
|
||||
|
||||
|
||||
#undef BPP5
|
||||
|
@ -261,7 +261,7 @@ uint32_t kron180_state::screen_update(screen_device &screen, bitmap_ind16 &bitma
|
||||
|
||||
/* Interrupt Handling */
|
||||
#if 0
|
||||
WRITE8_MEMBER(kron180_state::irq0_ack_w)
|
||||
void kron180_state::irq0_ack_w(uint8_t data)
|
||||
{
|
||||
m_irq0_ack = data;
|
||||
if ((data & 1) == 1)
|
||||
|
@ -78,7 +78,7 @@ SRAM:
|
||||
#define MAIN_CLOCK XTAL(18'432'000)
|
||||
|
||||
|
||||
WRITE8_MEMBER(ksayakyu_state::bank_select_w)
|
||||
void ksayakyu_state::bank_select_w(uint8_t data)
|
||||
{
|
||||
/*
|
||||
bits:
|
||||
@ -90,24 +90,24 @@ WRITE8_MEMBER(ksayakyu_state::bank_select_w)
|
||||
membank("bank1")->set_entry(data & 0x01);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ksayakyu_state::latch_w)
|
||||
void ksayakyu_state::latch_w(uint8_t data)
|
||||
{
|
||||
m_sound_status &= ~0x80;
|
||||
m_soundlatch->write(data | 0x80);
|
||||
}
|
||||
|
||||
READ8_MEMBER(ksayakyu_state::sound_status_r)
|
||||
uint8_t ksayakyu_state::sound_status_r()
|
||||
{
|
||||
return m_sound_status | 4;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ksayakyu_state::tomaincpu_w)
|
||||
void ksayakyu_state::tomaincpu_w(uint8_t data)
|
||||
{
|
||||
m_sound_status |= 0x80;
|
||||
m_soundlatch->write(data);
|
||||
}
|
||||
|
||||
READ8_MEMBER(ksayakyu_state::int_ack_r)
|
||||
uint8_t ksayakyu_state::int_ack_r()
|
||||
{
|
||||
m_maincpu->set_input_line(0, CLEAR_LINE);
|
||||
return 0xff; // value not used
|
||||
|
@ -34,7 +34,7 @@ INTERRUPT_GEN_MEMBER(labyrunr_state::labyrunr_timer_interrupt)
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER(labyrunr_state::labyrunr_bankswitch_w)
|
||||
void labyrunr_state::labyrunr_bankswitch_w(uint8_t data)
|
||||
{
|
||||
if (data & 0xe0) popmessage("bankswitch %02x", data);
|
||||
|
||||
|
@ -73,7 +73,7 @@ TODO:
|
||||
|
||||
|
||||
// Protection?
|
||||
READ8_MEMBER(sraider_state::sraider_8005_r)
|
||||
uint8_t sraider_state::sraider_8005_r()
|
||||
{
|
||||
// This must return X011111X or cpu #1 will hang
|
||||
// see code at rst $10
|
||||
@ -81,7 +81,7 @@ READ8_MEMBER(sraider_state::sraider_8005_r)
|
||||
}
|
||||
|
||||
// Unknown IO
|
||||
WRITE8_MEMBER(sraider_state::sraider_misc_w)
|
||||
void sraider_state::sraider_misc_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
|
@ -62,19 +62,19 @@ Notes:
|
||||
#include "speaker.h"
|
||||
|
||||
|
||||
READ8_MEMBER(ladyfrog_state::from_snd_r)
|
||||
uint8_t ladyfrog_state::from_snd_r()
|
||||
{
|
||||
m_snd_flag = 0;
|
||||
return m_snd_data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ladyfrog_state::to_main_w)
|
||||
void ladyfrog_state::to_main_w(uint8_t data)
|
||||
{
|
||||
m_snd_data = data;
|
||||
m_snd_flag = 2;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ladyfrog_state::sound_cpu_reset_w)
|
||||
void ladyfrog_state::sound_cpu_reset_w(uint8_t data)
|
||||
{
|
||||
m_audiocpu->set_input_line(INPUT_LINE_RESET, (data & 1 ) ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
@ -87,18 +87,18 @@ TIMER_CALLBACK_MEMBER(ladyfrog_state::nmi_callback)
|
||||
m_pending_nmi = 1;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ladyfrog_state::sound_command_w)
|
||||
void ladyfrog_state::sound_command_w(uint8_t data)
|
||||
{
|
||||
m_soundlatch->write(data);
|
||||
machine().scheduler().synchronize(timer_expired_delegate(FUNC(ladyfrog_state::nmi_callback),this), data);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ladyfrog_state::nmi_disable_w)
|
||||
void ladyfrog_state::nmi_disable_w(uint8_t data)
|
||||
{
|
||||
m_sound_nmi_enable = 0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ladyfrog_state::nmi_enable_w)
|
||||
void ladyfrog_state::nmi_enable_w(uint8_t data)
|
||||
{
|
||||
m_sound_nmi_enable = 1;
|
||||
if (m_pending_nmi)
|
||||
@ -112,7 +112,7 @@ void ladyfrog_state::unk_w(uint8_t data)
|
||||
{
|
||||
}
|
||||
|
||||
READ8_MEMBER(ladyfrog_state::snd_flag_r)
|
||||
uint8_t ladyfrog_state::snd_flag_r()
|
||||
{
|
||||
return m_snd_flag | 0xfd;
|
||||
}
|
||||
|
@ -91,11 +91,11 @@ protected:
|
||||
virtual void machine_reset() override;
|
||||
|
||||
private:
|
||||
READ8_MEMBER( ram_r );
|
||||
WRITE8_MEMBER( ram_w );
|
||||
READ8_MEMBER( io_r );
|
||||
WRITE8_MEMBER( io_w );
|
||||
READ8_MEMBER( io2_r );
|
||||
uint8_t ram_r(offs_t offset);
|
||||
void ram_w(offs_t offset, uint8_t data);
|
||||
uint8_t io_r(offs_t offset);
|
||||
void io_w(offs_t offset, uint8_t data);
|
||||
uint8_t io2_r(offs_t offset);
|
||||
|
||||
void laser3k_palette(palette_device &palette) const;
|
||||
uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
@ -249,12 +249,12 @@ void laser3k_state::machine_reset()
|
||||
rom[0x4607] = 0;
|
||||
}
|
||||
|
||||
READ8_MEMBER( laser3k_state::ram_r )
|
||||
uint8_t laser3k_state::ram_r(offs_t offset)
|
||||
{
|
||||
return m_ram->read(offset);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( laser3k_state::ram_w )
|
||||
void laser3k_state::ram_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
m_ram->write(offset, data);
|
||||
}
|
||||
@ -397,7 +397,7 @@ void laser3k_state::do_io(int offset)
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER( laser3k_state::io_r )
|
||||
uint8_t laser3k_state::io_r(offs_t offset)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
@ -431,7 +431,7 @@ READ8_MEMBER( laser3k_state::io_r )
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( laser3k_state::io_w )
|
||||
void laser3k_state::io_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
@ -472,7 +472,7 @@ WRITE8_MEMBER( laser3k_state::io_w )
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER( laser3k_state::io2_r )
|
||||
uint8_t laser3k_state::io2_r(offs_t offset)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
|
@ -86,7 +86,7 @@
|
||||
#include "speaker.h"
|
||||
|
||||
|
||||
WRITE8_MEMBER(laserbat_state_base::ct_io_w)
|
||||
void laserbat_state_base::ct_io_w(uint8_t data)
|
||||
{
|
||||
/*
|
||||
Uses a hex buffer, so bits 6 and 7 are not physically present.
|
||||
@ -134,7 +134,7 @@ WRITE8_MEMBER(laserbat_state_base::ct_io_w)
|
||||
// popmessage("ct io: %02X", data);
|
||||
}
|
||||
|
||||
READ8_MEMBER(laserbat_state_base::rrowx_r)
|
||||
uint8_t laserbat_state_base::rrowx_r()
|
||||
{
|
||||
return (m_mpx_p_1_2 ? m_row2 : m_mux_ports[m_input_mux])->read();
|
||||
}
|
||||
|
@ -50,19 +50,19 @@ INPUT_CHANGED_MEMBER(lasso_state::coin_inserted)
|
||||
|
||||
|
||||
/* Write to the sound latch and generate an IRQ on the sound CPU */
|
||||
WRITE8_MEMBER(lasso_state::sound_command_w)
|
||||
void lasso_state::sound_command_w(uint8_t data)
|
||||
{
|
||||
m_soundlatch->write(data);
|
||||
m_audiocpu->set_input_line(0, HOLD_LINE);
|
||||
}
|
||||
|
||||
READ8_MEMBER(lasso_state::sound_status_r)
|
||||
uint8_t lasso_state::sound_status_r()
|
||||
{
|
||||
/* 0x01: chip#0 ready; 0x02: chip#1 ready */
|
||||
return 0x03;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lasso_state::sound_select_w)
|
||||
void lasso_state::sound_select_w(uint8_t data)
|
||||
{
|
||||
uint8_t to_write = bitswap<8>(*m_chip_data, 0, 1, 2, 3, 4, 5, 6, 7);
|
||||
|
||||
|
@ -134,14 +134,14 @@ Notes:
|
||||
/******************************************************************************/
|
||||
|
||||
template<int Layer>
|
||||
WRITE16_MEMBER(lastduel_state::lastduel_vram_w)
|
||||
void lastduel_state::lastduel_vram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_vram[Layer][offset]);
|
||||
m_tilemap[Layer]->mark_tile_dirty(offset / 2);
|
||||
}
|
||||
|
||||
template<int Layer>
|
||||
WRITE16_MEMBER(lastduel_state::madgear_vram_w)
|
||||
void lastduel_state::madgear_vram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_vram[Layer][offset]);
|
||||
m_tilemap[Layer]->mark_tile_dirty(offset & 0x7ff);
|
||||
@ -197,7 +197,7 @@ void lastduel_state::sound_map(address_map &map)
|
||||
map(0xf800, 0xf800).r(m_soundlatch, FUNC(generic_latch_8_device::read));
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lastduel_state::mg_bankswitch_w)
|
||||
void lastduel_state::mg_bankswitch_w(uint8_t data)
|
||||
{
|
||||
m_audiobank->set_entry(data & 0x01);
|
||||
}
|
||||
|
@ -284,30 +284,30 @@ TIMER_DEVICE_CALLBACK_MEMBER(lazercmd_state::bbonk_timer)
|
||||
*************************************************************/
|
||||
|
||||
/* triggered by WRTC,r opcode */
|
||||
WRITE8_MEMBER(lazercmd_state::lazercmd_ctrl_port_w)
|
||||
void lazercmd_state::lazercmd_ctrl_port_w(uint8_t data)
|
||||
{
|
||||
}
|
||||
|
||||
/* triggered by REDC,r opcode */
|
||||
READ8_MEMBER(lazercmd_state::lazercmd_ctrl_port_r)
|
||||
uint8_t lazercmd_state::lazercmd_ctrl_port_r()
|
||||
{
|
||||
uint8_t data = 0;
|
||||
return data;
|
||||
}
|
||||
|
||||
/* triggered by WRTD,r opcode */
|
||||
WRITE8_MEMBER(lazercmd_state::lazercmd_data_port_w)
|
||||
void lazercmd_state::lazercmd_data_port_w(uint8_t data)
|
||||
{
|
||||
}
|
||||
|
||||
/* triggered by REDD,r opcode */
|
||||
READ8_MEMBER(lazercmd_state::lazercmd_data_port_r)
|
||||
uint8_t lazercmd_state::lazercmd_data_port_r()
|
||||
{
|
||||
uint8_t data = ioport("DSW")->read() & 0x0f;
|
||||
return data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lazercmd_state::lazercmd_hardware_w)
|
||||
void lazercmd_state::lazercmd_hardware_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
@ -329,7 +329,7 @@ WRITE8_MEMBER(lazercmd_state::lazercmd_hardware_w)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lazercmd_state::medlanes_hardware_w)
|
||||
void lazercmd_state::medlanes_hardware_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
@ -352,7 +352,7 @@ WRITE8_MEMBER(lazercmd_state::medlanes_hardware_w)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lazercmd_state::bbonk_hardware_w)
|
||||
void lazercmd_state::bbonk_hardware_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
@ -369,7 +369,7 @@ WRITE8_MEMBER(lazercmd_state::bbonk_hardware_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER(lazercmd_state::lazercmd_hardware_r)
|
||||
uint8_t lazercmd_state::lazercmd_hardware_r(offs_t offset)
|
||||
{
|
||||
uint8_t data = 0;
|
||||
|
||||
|
@ -28,7 +28,7 @@
|
||||
#include "speaker.h"
|
||||
|
||||
|
||||
WRITE16_MEMBER(lemmings_state::lemmings_control_w)
|
||||
void lemmings_state::lemmings_control_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
/* Offset==0 Pixel layer X scroll */
|
||||
if (offset == 4)
|
||||
@ -36,14 +36,14 @@ WRITE16_MEMBER(lemmings_state::lemmings_control_w)
|
||||
COMBINE_DATA(&m_control_data[offset]);
|
||||
}
|
||||
|
||||
READ16_MEMBER(lemmings_state::lemmings_trackball_r)
|
||||
uint16_t lemmings_state::lemmings_trackball_r(offs_t offset)
|
||||
{
|
||||
if ((offset & 2) == 0)
|
||||
return m_trackball_io[(offset & 1) | ((offset & 4) >> 1)]->read();
|
||||
return 0;
|
||||
}
|
||||
|
||||
READ16_MEMBER( lemmings_state::lem_protection_region_0_146_r )
|
||||
uint16_t lemmings_state::lem_protection_region_0_146_r(offs_t offset)
|
||||
{
|
||||
int real_address = 0 + (offset *2);
|
||||
int deco146_addr = bitswap<32>(real_address, /* NC */31,30,29,28,27,26,25,24,23,22,21,20,19,18, 13,12,11,/**/ 17,16,15,14, 10,9,8, 7,6,5,4, 3,2,1,0) & 0x7fff;
|
||||
@ -52,7 +52,7 @@ READ16_MEMBER( lemmings_state::lem_protection_region_0_146_r )
|
||||
return data;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER( lemmings_state::lem_protection_region_0_146_w )
|
||||
void lemmings_state::lem_protection_region_0_146_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
int real_address = 0 + (offset *2);
|
||||
int deco146_addr = bitswap<32>(real_address, /* NC */31,30,29,28,27,26,25,24,23,22,21,20,19,18, 13,12,11,/**/ 17,16,15,14, 10,9,8, 7,6,5,4, 3,2,1,0) & 0x7fff;
|
||||
|
@ -268,7 +268,7 @@ static const char *const gunnames[] = { "LIGHT0_X", "LIGHT0_Y", "LIGHT1_X", "LIG
|
||||
#define GUNX( a ) (( ( ioport(gunnames[2 * (a - 1)])->read() * 287 ) / 0xff ) + 16)
|
||||
#define GUNY( a ) (( ( ioport(gunnames[2 * (a - 1) + 1])->read() * 223 ) / 0xff ) + 10)
|
||||
|
||||
WRITE8_MEMBER(lethal_state::control2_w)
|
||||
void lethal_state::control2_w(uint8_t data)
|
||||
{
|
||||
/* bit 0 is data */
|
||||
/* bit 1 is cs (active low) */
|
||||
@ -291,23 +291,23 @@ INTERRUPT_GEN_MEMBER(lethal_state::lethalen_interrupt)
|
||||
device.execute().set_input_line(HD6309_IRQ_LINE, HOLD_LINE);
|
||||
}
|
||||
|
||||
READ8_MEMBER(lethal_state::sound_irq_r)
|
||||
uint8_t lethal_state::sound_irq_r()
|
||||
{
|
||||
m_soundcpu->set_input_line(0, HOLD_LINE);
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lethal_state::sound_irq_w)
|
||||
void lethal_state::sound_irq_w(uint8_t data)
|
||||
{
|
||||
m_soundcpu->set_input_line(0, HOLD_LINE);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lethal_state::le_bankswitch_w)
|
||||
void lethal_state::le_bankswitch_w(uint8_t data)
|
||||
{
|
||||
membank("bank1")->set_entry(data);
|
||||
}
|
||||
|
||||
READ8_MEMBER(lethal_state::guns_r)
|
||||
uint8_t lethal_state::guns_r(offs_t offset)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
@ -330,7 +330,7 @@ READ8_MEMBER(lethal_state::guns_r)
|
||||
return 0;
|
||||
}
|
||||
|
||||
READ8_MEMBER(lethal_state::gunsaux_r)
|
||||
uint8_t lethal_state::gunsaux_r()
|
||||
{
|
||||
int res = 0;
|
||||
|
||||
|
@ -213,7 +213,7 @@ CUSTOM_INPUT_MEMBER(lethalj_state::cclownz_paddle)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
WRITE16_MEMBER(lethalj_state::ripribit_control_w)
|
||||
void lethalj_state::ripribit_control_w(uint16_t data)
|
||||
{
|
||||
machine().bookkeeping().coin_counter_w(0, BIT(data, 0));
|
||||
m_ticket->motor_w(BIT(data, 1));
|
||||
@ -221,7 +221,7 @@ WRITE16_MEMBER(lethalj_state::ripribit_control_w)
|
||||
}
|
||||
|
||||
|
||||
WRITE16_MEMBER(lethalj_state::cfarm_control_w)
|
||||
void lethalj_state::cfarm_control_w(uint16_t data)
|
||||
{
|
||||
m_ticket->motor_w(BIT(data, 0));
|
||||
m_lamps[0] = BIT(data, 2);
|
||||
@ -231,7 +231,7 @@ WRITE16_MEMBER(lethalj_state::cfarm_control_w)
|
||||
}
|
||||
|
||||
|
||||
WRITE16_MEMBER(lethalj_state::cclownz_control_w)
|
||||
void lethalj_state::cclownz_control_w(uint16_t data)
|
||||
{
|
||||
m_ticket->motor_w(BIT(data, 0));
|
||||
m_lamps[0] = BIT(data, 2);
|
||||
@ -1204,19 +1204,19 @@ ROM_END
|
||||
|
||||
void lethalj_state::init_ripribit()
|
||||
{
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x04100010, 0x0410001f, write16_delegate(*this, FUNC(lethalj_state::ripribit_control_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x04100010, 0x0410001f, write16smo_delegate(*this, FUNC(lethalj_state::ripribit_control_w)));
|
||||
}
|
||||
|
||||
|
||||
void lethalj_state::init_cfarm()
|
||||
{
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x04100010, 0x0410001f, write16_delegate(*this, FUNC(lethalj_state::cfarm_control_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x04100010, 0x0410001f, write16smo_delegate(*this, FUNC(lethalj_state::cfarm_control_w)));
|
||||
}
|
||||
|
||||
|
||||
void lethalj_state::init_cclownz()
|
||||
{
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x04100010, 0x0410001f, write16_delegate(*this, FUNC(lethalj_state::cclownz_control_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x04100010, 0x0410001f, write16smo_delegate(*this, FUNC(lethalj_state::cclownz_control_w)));
|
||||
}
|
||||
|
||||
|
||||
|
@ -33,7 +33,7 @@
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ8_MEMBER(liberate_state::deco16_bank_r)
|
||||
uint8_t liberate_state::deco16_bank_r(offs_t offset)
|
||||
{
|
||||
const uint8_t *ROM = memregion("user1")->base();
|
||||
|
||||
@ -60,7 +60,7 @@ READ8_MEMBER(liberate_state::deco16_bank_r)
|
||||
return 0;
|
||||
}
|
||||
|
||||
READ8_MEMBER(liberate_state::deco16_io_r)
|
||||
uint8_t liberate_state::deco16_io_r(offs_t offset)
|
||||
{
|
||||
if (offset == 0) return ioport("IN1")->read(); /* Player 1 controls */
|
||||
if (offset == 1) return ioport("IN2")->read(); /* Player 2 controls */
|
||||
@ -72,17 +72,17 @@ READ8_MEMBER(liberate_state::deco16_io_r)
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(liberate_state::deco16_bank_w)
|
||||
void liberate_state::deco16_bank_w(uint8_t data)
|
||||
{
|
||||
m_bank = data;
|
||||
|
||||
if (m_bank)
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x8000, 0x800f, read8_delegate(*this, FUNC(liberate_state::deco16_io_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x8000, 0x800f, read8sm_delegate(*this, FUNC(liberate_state::deco16_io_r)));
|
||||
else
|
||||
m_maincpu->space(AS_PROGRAM).install_read_bank(0x8000, 0x800f, "bank1");
|
||||
}
|
||||
|
||||
READ8_MEMBER(liberate_state::prosoccr_bank_r)
|
||||
uint8_t liberate_state::prosoccr_bank_r(offs_t offset)
|
||||
{
|
||||
const uint8_t *ROM = memregion("user1")->base();
|
||||
|
||||
@ -111,7 +111,7 @@ READ8_MEMBER(liberate_state::prosoccr_bank_r)
|
||||
return 0;
|
||||
}
|
||||
|
||||
READ8_MEMBER(liberate_state::prosoccr_charram_r)
|
||||
uint8_t liberate_state::prosoccr_charram_r(offs_t offset)
|
||||
{
|
||||
uint8_t *SRC_GFX = memregion("shared_gfx")->base();
|
||||
|
||||
@ -132,11 +132,11 @@ READ8_MEMBER(liberate_state::prosoccr_charram_r)
|
||||
return m_charram[offset + m_gfx_rom_readback * 0x1800];
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(liberate_state::prosoccr_charram_w)
|
||||
void liberate_state::prosoccr_charram_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
if (m_bank)
|
||||
{
|
||||
prosoccr_io_w(space, offset & 0x0f, data);
|
||||
prosoccr_io_w(offset & 0x0f, data);
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -167,7 +167,7 @@ WRITE8_MEMBER(liberate_state::prosoccr_charram_w)
|
||||
// m_gfxdecode->gfx(0)->mark_dirty((offset | 0x1800) >> 3);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(liberate_state::prosoccr_char_bank_w)
|
||||
void liberate_state::prosoccr_char_bank_w(uint8_t data)
|
||||
{
|
||||
m_gfx_rom_readback = data & 1; //enable GFX rom read-back
|
||||
|
||||
@ -175,18 +175,18 @@ WRITE8_MEMBER(liberate_state::prosoccr_char_bank_w)
|
||||
printf("%02x\n", data);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(liberate_state::prosoccr_io_bank_w)
|
||||
void liberate_state::prosoccr_io_bank_w(uint8_t data)
|
||||
{
|
||||
m_bank = data & 1;
|
||||
|
||||
if (m_bank)
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x8000, 0x800f, read8_delegate(*this, FUNC(liberate_state::deco16_io_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x8000, 0x800f, read8sm_delegate(*this, FUNC(liberate_state::deco16_io_r)));
|
||||
else
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x8000, 0x800f, read8_delegate(*this, FUNC(liberate_state::prosoccr_charram_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x8000, 0x800f, read8sm_delegate(*this, FUNC(liberate_state::prosoccr_charram_r)));
|
||||
|
||||
}
|
||||
|
||||
READ8_MEMBER(liberate_state::prosport_charram_r)
|
||||
uint8_t liberate_state::prosport_charram_r(offs_t offset)
|
||||
{
|
||||
uint8_t *FG_GFX = memregion("progolf_fg_gfx")->base();
|
||||
|
||||
@ -206,7 +206,7 @@ READ8_MEMBER(liberate_state::prosport_charram_r)
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(liberate_state::prosport_charram_w)
|
||||
void liberate_state::prosport_charram_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
uint8_t *FG_GFX = memregion("progolf_fg_gfx")->base();
|
||||
|
||||
|
@ -170,7 +170,7 @@ void liberatr_state::machine_reset()
|
||||
*
|
||||
*************************************/
|
||||
|
||||
WRITE8_MEMBER(liberatr_state::output_latch_w)
|
||||
void liberatr_state::output_latch_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
m_outlatch->write_bit(offset, BIT(data, 4));
|
||||
}
|
||||
@ -209,7 +209,7 @@ WRITE_LINE_MEMBER(liberatr_state::trackball_reset_w)
|
||||
}
|
||||
|
||||
|
||||
READ8_MEMBER( liberatr_state::port0_r )
|
||||
uint8_t liberatr_state::port0_r()
|
||||
{
|
||||
/* if ctrld is high, the /ld signal on the LS191 is NOT set, meaning that the trackball is counting */
|
||||
if (m_ctrld)
|
||||
@ -231,14 +231,14 @@ READ8_MEMBER( liberatr_state::port0_r )
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ8_MEMBER( liberatr_state::earom_r )
|
||||
uint8_t liberatr_state::earom_r()
|
||||
{
|
||||
// return data latched from previous clock
|
||||
return m_earom->data();
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER( liberatr_state::earom_w )
|
||||
void liberatr_state::earom_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
// remember the value written
|
||||
m_earom_data = data;
|
||||
@ -252,7 +252,7 @@ WRITE8_MEMBER( liberatr_state::earom_w )
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER( liberatr_state::earom_control_w )
|
||||
void liberatr_state::earom_control_w(uint8_t data)
|
||||
{
|
||||
// remember the control state
|
||||
m_earom_control = data;
|
||||
|
@ -102,17 +102,17 @@ TODO:
|
||||
#define MCU_CLOCK (XTAL(12'000'000)/4)
|
||||
|
||||
|
||||
WRITE8_MEMBER(lkage_state::lkage_sh_nmi_disable_w)
|
||||
void lkage_state::lkage_sh_nmi_disable_w(uint8_t data)
|
||||
{
|
||||
m_soundnmi->in_w<1>(0);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lkage_state::lkage_sh_nmi_enable_w)
|
||||
void lkage_state::lkage_sh_nmi_enable_w(uint8_t data)
|
||||
{
|
||||
m_soundnmi->in_w<1>(1);
|
||||
}
|
||||
|
||||
READ8_MEMBER(lkage_state::sound_status_r)
|
||||
uint8_t lkage_state::sound_status_r()
|
||||
{
|
||||
return 0xff;
|
||||
}
|
||||
@ -155,7 +155,7 @@ void lkage_state::lkage_map_boot(address_map &map)
|
||||
}
|
||||
|
||||
|
||||
READ8_MEMBER(lkage_state::port_fetch_r)
|
||||
uint8_t lkage_state::port_fetch_r(offs_t offset)
|
||||
{
|
||||
return memregion("user1")->base()[offset];
|
||||
}
|
||||
@ -846,7 +846,7 @@ ROM_START( bygone )
|
||||
ROM_END
|
||||
|
||||
|
||||
READ8_MEMBER(lkage_state::mcu_status_r)
|
||||
uint8_t lkage_state::mcu_status_r()
|
||||
{
|
||||
// bit 0 = when 1, MCU is ready to receive data from main CPU
|
||||
// bit 1 = when 1, MCU has sent data to the main CPU
|
||||
@ -857,7 +857,7 @@ READ8_MEMBER(lkage_state::mcu_status_r)
|
||||
|
||||
// Note: This probably uses another MCU program, which is undumped.
|
||||
|
||||
READ8_MEMBER(lkage_state::fake_mcu_r)
|
||||
uint8_t lkage_state::fake_mcu_r()
|
||||
{
|
||||
int result = 0;
|
||||
|
||||
@ -892,12 +892,12 @@ READ8_MEMBER(lkage_state::fake_mcu_r)
|
||||
return result;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lkage_state::fake_mcu_w)
|
||||
void lkage_state::fake_mcu_w(uint8_t data)
|
||||
{
|
||||
m_mcu_val = data;
|
||||
}
|
||||
|
||||
READ8_MEMBER(lkage_state::fake_status_r)
|
||||
uint8_t lkage_state::fake_status_r()
|
||||
{
|
||||
return m_mcu_ready;
|
||||
}
|
||||
|
@ -49,7 +49,7 @@
|
||||
|
||||
*************************************/
|
||||
|
||||
WRITE16_MEMBER(lockon_state::adrst_w)
|
||||
void lockon_state::adrst_w(uint16_t data)
|
||||
{
|
||||
m_ctrl_reg = data & 0xff;
|
||||
|
||||
@ -59,13 +59,13 @@ WRITE16_MEMBER(lockon_state::adrst_w)
|
||||
m_audiocpu->set_input_line(INPUT_LINE_HALT, data & 0x40 ? CLEAR_LINE : ASSERT_LINE);
|
||||
}
|
||||
|
||||
READ16_MEMBER(lockon_state::main_gnd_r)
|
||||
uint16_t lockon_state::main_gnd_r(offs_t offset)
|
||||
{
|
||||
address_space &gndspace = m_ground->space(AS_PROGRAM);
|
||||
return gndspace.read_word(V30_GND_ADDR | offset * 2);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(lockon_state::main_gnd_w)
|
||||
void lockon_state::main_gnd_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
address_space &gndspace = m_ground->space(AS_PROGRAM);
|
||||
|
||||
@ -75,13 +75,13 @@ WRITE16_MEMBER(lockon_state::main_gnd_w)
|
||||
gndspace.write_byte(V30_GND_ADDR | (offset * 2 + 1), data >> 8);
|
||||
}
|
||||
|
||||
READ16_MEMBER(lockon_state::main_obj_r)
|
||||
uint16_t lockon_state::main_obj_r(offs_t offset)
|
||||
{
|
||||
address_space &objspace = m_object->space(AS_PROGRAM);
|
||||
return objspace.read_word(V30_OBJ_ADDR | offset * 2);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(lockon_state::main_obj_w)
|
||||
void lockon_state::main_obj_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
address_space &objspace =m_object->space(AS_PROGRAM);
|
||||
|
||||
@ -91,7 +91,7 @@ WRITE16_MEMBER(lockon_state::main_obj_w)
|
||||
objspace.write_byte(V30_OBJ_ADDR | (offset * 2 + 1), data >> 8);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(lockon_state::tst_w)
|
||||
void lockon_state::tst_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
if (offset < 0x800)
|
||||
{
|
||||
@ -110,24 +110,24 @@ WRITE16_MEMBER(lockon_state::tst_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(lockon_state::main_z80_r)
|
||||
uint16_t lockon_state::main_z80_r(offs_t offset)
|
||||
{
|
||||
address_space &sndspace = m_audiocpu->space(AS_PROGRAM);
|
||||
return 0xff00 | sndspace.read_byte(offset);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(lockon_state::main_z80_w)
|
||||
void lockon_state::main_z80_w(offs_t offset, uint16_t data)
|
||||
{
|
||||
address_space &sndspace = m_audiocpu->space(AS_PROGRAM);
|
||||
sndspace.write_byte(offset, data);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(lockon_state::inten_w)
|
||||
void lockon_state::inten_w(uint16_t data)
|
||||
{
|
||||
m_main_inten = 1;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(lockon_state::emres_w)
|
||||
void lockon_state::emres_w(uint16_t data)
|
||||
{
|
||||
m_watchdog->watchdog_reset();
|
||||
m_main_inten = 0;
|
||||
@ -352,7 +352,7 @@ GFXDECODE_END
|
||||
*
|
||||
*************************************/
|
||||
|
||||
WRITE8_MEMBER(lockon_state::sound_vol)
|
||||
void lockon_state::sound_vol(uint8_t data)
|
||||
{
|
||||
#define LO_SHUNT 250.0
|
||||
#define LO_R0 5600.0
|
||||
|
@ -56,7 +56,7 @@ Notes:
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
WRITE16_MEMBER(lordgun_state::lordgun_protection_w)
|
||||
void lordgun_state::lordgun_protection_w(offs_t offset, uint16_t data)
|
||||
{
|
||||
switch (offset & 0x60)
|
||||
{
|
||||
@ -77,7 +77,7 @@ WRITE16_MEMBER(lordgun_state::lordgun_protection_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(lordgun_state::lordgun_protection_r)
|
||||
uint16_t lordgun_state::lordgun_protection_r(offs_t offset)
|
||||
{
|
||||
switch (offset & 0x60)
|
||||
{
|
||||
@ -107,7 +107,7 @@ READ16_MEMBER(lordgun_state::lordgun_protection_r)
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(lordgun_state::aliencha_protection_w)
|
||||
void lordgun_state::aliencha_protection_w(offs_t offset, uint16_t data)
|
||||
{
|
||||
switch (offset & 0x60)
|
||||
{
|
||||
@ -120,7 +120,7 @@ WRITE16_MEMBER(lordgun_state::aliencha_protection_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(lordgun_state::aliencha_protection_r)
|
||||
uint16_t lordgun_state::aliencha_protection_r(offs_t offset)
|
||||
{
|
||||
switch (offset & 0x60)
|
||||
{
|
||||
@ -244,33 +244,33 @@ void lordgun_state::aliencha_dip_w(uint8_t data)
|
||||
}
|
||||
|
||||
// Unknown, always equal to 7 in lordgun, aliencha.
|
||||
WRITE16_MEMBER(lordgun_state::priority_w)
|
||||
void lordgun_state::priority_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_priority);
|
||||
}
|
||||
|
||||
|
||||
READ16_MEMBER(lordgun_state::lordgun_gun_0_x_r)
|
||||
uint16_t lordgun_state::lordgun_gun_0_x_r()
|
||||
{
|
||||
return m_gun[0].hw_x;
|
||||
}
|
||||
|
||||
READ16_MEMBER(lordgun_state::lordgun_gun_0_y_r)
|
||||
uint16_t lordgun_state::lordgun_gun_0_y_r()
|
||||
{
|
||||
return m_gun[0].hw_y;
|
||||
}
|
||||
|
||||
READ16_MEMBER(lordgun_state::lordgun_gun_1_x_r)
|
||||
uint16_t lordgun_state::lordgun_gun_1_x_r()
|
||||
{
|
||||
return m_gun[1].hw_x;
|
||||
}
|
||||
|
||||
READ16_MEMBER(lordgun_state::lordgun_gun_1_y_r)
|
||||
uint16_t lordgun_state::lordgun_gun_1_y_r()
|
||||
{
|
||||
return m_gun[1].hw_y;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(lordgun_state::soundlatch_w)
|
||||
void lordgun_state::soundlatch_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_0_7) m_soundlatch->write((data >> 0) & 0xff);
|
||||
if (ACCESSING_BITS_8_15) m_soundlatch2->write((data >> 8) & 0xff);
|
||||
@ -279,7 +279,7 @@ WRITE16_MEMBER(lordgun_state::soundlatch_w)
|
||||
}
|
||||
|
||||
template<int Layer>
|
||||
WRITE16_MEMBER(lordgun_state::vram_w)
|
||||
void lordgun_state::vram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_vram[Layer][offset]);
|
||||
m_tilemap[Layer]->mark_tile_dirty(offset/2);
|
||||
|
@ -157,7 +157,7 @@ Notes:
|
||||
#define MASTER_CLOCK XTAL(24'000'000)
|
||||
|
||||
|
||||
WRITE8_MEMBER(lsasquad_state::lsasquad_bankswitch_w)
|
||||
void lsasquad_state::lsasquad_bankswitch_w(uint8_t data)
|
||||
{
|
||||
/* bits 0-2 select ROM bank */
|
||||
membank("bank1")->set_entry(data & 0x07);
|
||||
|
@ -807,7 +807,7 @@ void lucky74_state::machine_reset()
|
||||
* Read/Write Handlers *
|
||||
*****************************/
|
||||
|
||||
READ8_MEMBER(lucky74_state::custom_09R81P_port_r)
|
||||
uint8_t lucky74_state::custom_09R81P_port_r(offs_t offset)
|
||||
{
|
||||
if (offset != 0x00)
|
||||
{
|
||||
@ -819,7 +819,7 @@ READ8_MEMBER(lucky74_state::custom_09R81P_port_r)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lucky74_state::custom_09R81P_port_w)
|
||||
void lucky74_state::custom_09R81P_port_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
m_adpcm_reg[offset] = data;
|
||||
}
|
||||
@ -836,28 +836,28 @@ void lucky74_state::ym2149_portb_w(uint8_t data)
|
||||
flip_screen_set(data & 0x01);
|
||||
}
|
||||
|
||||
READ8_MEMBER(lucky74_state::usart_8251_r)
|
||||
uint8_t lucky74_state::usart_8251_r()
|
||||
{
|
||||
/* reads to USART 8251 port */
|
||||
logerror("read from USART port.\n");
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lucky74_state::usart_8251_w)
|
||||
void lucky74_state::usart_8251_w(uint8_t data)
|
||||
{
|
||||
/* writes to USART 8251 port */
|
||||
m_usart_8251 = data;
|
||||
logerror("write to USART port: %02x \n", m_usart_8251);
|
||||
}
|
||||
|
||||
READ8_MEMBER(lucky74_state::copro_sm7831_r)
|
||||
uint8_t lucky74_state::copro_sm7831_r()
|
||||
{
|
||||
/* read from SM7831 co-processor */
|
||||
logerror("read from co-processor.\n");
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lucky74_state::copro_sm7831_w)
|
||||
void lucky74_state::copro_sm7831_w(uint8_t data)
|
||||
{
|
||||
/* write to SM7831 co-processor */
|
||||
m_copro_sm7831 = data;
|
||||
|
@ -101,7 +101,7 @@ void lvpoker_state::machine_reset()
|
||||
m_result = 0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lvpoker_state::control_port_2_w)
|
||||
void lvpoker_state::control_port_2_w(uint8_t data)
|
||||
{
|
||||
switch (data)
|
||||
{
|
||||
@ -117,7 +117,7 @@ WRITE8_MEMBER(lvpoker_state::control_port_2_w)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lvpoker_state::control_port_2a_w)
|
||||
void lvpoker_state::control_port_2a_w(uint8_t data)
|
||||
{
|
||||
switch (data)
|
||||
{
|
||||
@ -133,7 +133,7 @@ WRITE8_MEMBER(lvpoker_state::control_port_2a_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER(lvpoker_state::payout_r)
|
||||
uint8_t lvpoker_state::payout_r()
|
||||
{
|
||||
m_result = ioport("IN2")->read();
|
||||
|
||||
|
@ -73,17 +73,17 @@ Notes:
|
||||
* a code reflecting the direction (8 angles) from one point to the other.
|
||||
*/
|
||||
|
||||
WRITE8_MEMBER(lwings_state::avengers_adpcm_w)
|
||||
void lwings_state::avengers_adpcm_w(uint8_t data)
|
||||
{
|
||||
m_adpcm = data;
|
||||
}
|
||||
|
||||
READ8_MEMBER(lwings_state::avengers_adpcm_r)
|
||||
uint8_t lwings_state::avengers_adpcm_r()
|
||||
{
|
||||
return m_adpcm;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lwings_state::lwings_bankswitch_w)
|
||||
void lwings_state::lwings_bankswitch_w(uint8_t data)
|
||||
{
|
||||
// if (data & 0xe0) printf("bankswitch_w %02x\n", data);
|
||||
// Fireball writes 0x20 on startup, maybe reset soundcpu?
|
||||
@ -116,7 +116,7 @@ WRITE_LINE_MEMBER(lwings_state::avengers_interrupt)
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER(lwings_state::avengers_protection_w)
|
||||
void lwings_state::avengers_protection_w(uint8_t data)
|
||||
{
|
||||
int pc = m_maincpu->pc();
|
||||
|
||||
@ -143,7 +143,7 @@ WRITE8_MEMBER(lwings_state::avengers_protection_w)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lwings_state::avengers_prot_bank_w)
|
||||
void lwings_state::avengers_prot_bank_w(uint8_t data)
|
||||
{
|
||||
m_palette_pen = data * 64;
|
||||
}
|
||||
@ -239,7 +239,7 @@ int lwings_state::avengers_fetch_paldata( )
|
||||
return result;
|
||||
}
|
||||
|
||||
READ8_MEMBER(lwings_state::avengers_protection_r)
|
||||
uint8_t lwings_state::avengers_protection_r()
|
||||
{
|
||||
static const int xpos[8] = { 10, 7, 0, -7, -10, -7, 0, 7 };
|
||||
static const int ypos[8] = { 0, 7, 10, 7, 0, -7, -10, -7 };
|
||||
@ -275,14 +275,14 @@ READ8_MEMBER(lwings_state::avengers_protection_r)
|
||||
return best_dir << 5;
|
||||
}
|
||||
|
||||
READ8_MEMBER(lwings_state::avengers_soundlatch2_r)
|
||||
uint8_t lwings_state::avengers_soundlatch2_r()
|
||||
{
|
||||
uint8_t data = *m_soundlatch2 | m_soundstate;
|
||||
m_soundstate = 0;
|
||||
return(data);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(lwings_state::msm5205_w)
|
||||
void lwings_state::msm5205_w(uint8_t data)
|
||||
{
|
||||
m_msm->reset_w(BIT(data, 7));
|
||||
m_msm->data_w(data);
|
||||
@ -402,7 +402,7 @@ void lwings_state::fball_map(address_map &map)
|
||||
|
||||
|
||||
|
||||
WRITE8_MEMBER(lwings_state::fball_oki_bank_w)
|
||||
void lwings_state::fball_oki_bank_w(uint8_t data)
|
||||
{
|
||||
//printf("fball_oki_bank_w %02x\n", data);
|
||||
membank("samplebank")->set_entry((data >> 1) & 0x7);
|
||||
|
@ -87,7 +87,7 @@ WRITE8_MEMBER(m107_state::bankswitch_w)
|
||||
logerror("%05x: bankswitch %04x\n", m_maincpu->pc(), data);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(m107_state::sound_reset_w)
|
||||
void m107_state::sound_reset_w(uint16_t data)
|
||||
{
|
||||
m_soundcpu->set_input_line(INPUT_LINE_RESET, (data) ? CLEAR_LINE : ASSERT_LINE);
|
||||
}
|
||||
@ -143,7 +143,7 @@ void m107_state::dsoccr94_io_map(address_map &map)
|
||||
}
|
||||
|
||||
/* same as M107 but with an extra i/o board */
|
||||
WRITE16_MEMBER(m107_state::wpksoc_output_w)
|
||||
void m107_state::wpksoc_output_w(uint16_t data)
|
||||
{
|
||||
/*
|
||||
x--- ---- ?
|
||||
|
@ -442,25 +442,25 @@ INTERRUPT_GEN_MEMBER(m72_state::fake_nmi)
|
||||
}
|
||||
|
||||
|
||||
WRITE16_MEMBER(m72_state::bchopper_sample_trigger_w)
|
||||
void m72_state::bchopper_sample_trigger_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
static const int a[6] = { 0x0000, 0x0010, 0x2510, 0x6510, 0x8510, 0x9310 };
|
||||
if (ACCESSING_BITS_0_7 && (data & 0xff) < 6) m_audio->set_sample_start(a[data & 0xff]);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(m72_state::nspirit_sample_trigger_w)
|
||||
void m72_state::nspirit_sample_trigger_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
static const int a[9] = { 0x0000, 0x0020, 0x2020, 0, 0x5720, 0, 0x7b60, 0x9b60, 0xc360 };
|
||||
if (ACCESSING_BITS_0_7 && (data & 0xff) < 9) m_audio->set_sample_start(a[data & 0xff]);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(m72_state::imgfight_sample_trigger_w)
|
||||
void m72_state::imgfight_sample_trigger_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
static const int a[7] = { 0x0000, 0x0020, 0x44e0, 0x98a0, 0xc820, 0xf7a0, 0x108c0 };
|
||||
if (ACCESSING_BITS_0_7 && (data & 0xff) < 7) m_audio->set_sample_start(a[data & 0xff]);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(m72_state::loht_sample_trigger_w)
|
||||
void m72_state::loht_sample_trigger_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
static const int a[7] = { 0x0000, 0x0020, 0, 0x2c40, 0x4320, 0x7120, 0xb200 };
|
||||
if (ACCESSING_BITS_0_7 && (data & 0xff) < 7) m_audio->set_sample_start(a[data & 0xff]);
|
||||
@ -468,13 +468,13 @@ WRITE16_MEMBER(m72_state::loht_sample_trigger_w)
|
||||
|
||||
|
||||
|
||||
WRITE16_MEMBER(m72_state::dbreedm72_sample_trigger_w)
|
||||
void m72_state::dbreedm72_sample_trigger_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
static const int a[9] = { 0x00000, 0x00020, 0x02c40, 0x08160, 0x0c8c0, 0x0ffe0, 0x13000, 0x15820, 0x15f40 };
|
||||
if (ACCESSING_BITS_0_7 && (data & 0xff) < 9) m_audio->set_sample_start(a[data & 0xff]);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(m72_state::dkgenm72_sample_trigger_w)
|
||||
void m72_state::dkgenm72_sample_trigger_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
static const int a[28] = {
|
||||
0x00000, 0x00020, 0x01800, 0x02da0, 0x03be0, 0x05ae0, 0x06100, 0x06de0,
|
||||
@ -485,7 +485,7 @@ WRITE16_MEMBER(m72_state::dkgenm72_sample_trigger_w)
|
||||
if (ACCESSING_BITS_0_7 && (data & 0xff) < 28) m_audio->set_sample_start(a[data & 0xff]);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(m72_state::gallop_sample_trigger_w)
|
||||
void m72_state::gallop_sample_trigger_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
static const int a[31] = {
|
||||
0x00000, 0x00020, 0x00040, 0x01360, 0x02580, 0x04f20, 0x06240, 0x076e0,
|
||||
@ -632,14 +632,14 @@ void m72_state::copy_le(u16 *dest, const u8 *src, u8 bytes)
|
||||
dest[i/2] = src[i+0] | (src[i+1] << 8);
|
||||
}
|
||||
|
||||
READ16_MEMBER(m72_state::protection_r)
|
||||
u16 m72_state::protection_r(offs_t offset, u16 mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_8_15)
|
||||
copy_le(m_protection_ram.get(),m_protection_code,CODE_LEN);
|
||||
return m_protection_ram[0xffa/2+offset];
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(m72_state::protection_w)
|
||||
void m72_state::protection_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
data ^= 0xffff;
|
||||
COMBINE_DATA(&m_protection_ram[offset]);
|
||||
@ -655,8 +655,8 @@ void m72_state::install_protection_handler(const u8 *code,const u8 *crc)
|
||||
m_protection_code = code;
|
||||
m_protection_crc = crc;
|
||||
m_maincpu->space(AS_PROGRAM).install_read_bank(0xb0000, 0xb0fff, "bank1");
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0xb0ffa, 0xb0ffb, read16_delegate(*this, FUNC(m72_state::protection_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xb0000, 0xb0fff, write16_delegate(*this, FUNC(m72_state::protection_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0xb0ffa, 0xb0ffb, read16s_delegate(*this, FUNC(m72_state::protection_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xb0000, 0xb0fff, write16s_delegate(*this, FUNC(m72_state::protection_w)));
|
||||
membank("bank1")->configure_entry(0, m_protection_ram.get());
|
||||
|
||||
save_pointer(NAME(m_protection_ram), 0x1000/2);
|
||||
@ -665,36 +665,36 @@ void m72_state::install_protection_handler(const u8 *code,const u8 *crc)
|
||||
void m72_state::init_bchopper()
|
||||
{
|
||||
install_protection_handler(bchopper_code,bchopper_crc);
|
||||
m_maincpu->space(AS_IO).install_write_handler(0xc0, 0xc1, write16_delegate(*this, FUNC(m72_state::bchopper_sample_trigger_w)));
|
||||
m_maincpu->space(AS_IO).install_write_handler(0xc0, 0xc1, write16s_delegate(*this, FUNC(m72_state::bchopper_sample_trigger_w)));
|
||||
}
|
||||
|
||||
void m72_state::init_nspirit()
|
||||
{
|
||||
install_protection_handler(nspirit_code,nspirit_crc);
|
||||
m_maincpu->space(AS_IO).install_write_handler(0xc0, 0xc1, write16_delegate(*this, FUNC(m72_state::nspirit_sample_trigger_w)));
|
||||
m_maincpu->space(AS_IO).install_write_handler(0xc0, 0xc1, write16s_delegate(*this, FUNC(m72_state::nspirit_sample_trigger_w)));
|
||||
}
|
||||
|
||||
void m72_state::init_imgfight()
|
||||
{
|
||||
install_protection_handler(imgfight_code,imgfightj_crc);
|
||||
m_maincpu->space(AS_IO).install_write_handler(0xc0, 0xc1, write16_delegate(*this, FUNC(m72_state::imgfight_sample_trigger_w)));
|
||||
m_maincpu->space(AS_IO).install_write_handler(0xc0, 0xc1, write16s_delegate(*this, FUNC(m72_state::imgfight_sample_trigger_w)));
|
||||
}
|
||||
|
||||
void m72_state::init_dbreedm72()
|
||||
{
|
||||
install_protection_handler(dbreedm72_code,dbreedm72_crc);
|
||||
m_maincpu->space(AS_IO).install_write_handler(0xc0, 0xc1, write16_delegate(*this, FUNC(m72_state::dbreedm72_sample_trigger_w)));
|
||||
m_maincpu->space(AS_IO).install_write_handler(0xc0, 0xc1, write16s_delegate(*this, FUNC(m72_state::dbreedm72_sample_trigger_w)));
|
||||
}
|
||||
|
||||
void m72_state::init_dkgenm72()
|
||||
{
|
||||
install_protection_handler(dkgenm72_code,dkgenm72_crc);
|
||||
m_maincpu->space(AS_IO).install_write_handler(0xc0, 0xc1, write16_delegate(*this, FUNC(m72_state::dkgenm72_sample_trigger_w)));
|
||||
m_maincpu->space(AS_IO).install_write_handler(0xc0, 0xc1, write16s_delegate(*this, FUNC(m72_state::dkgenm72_sample_trigger_w)));
|
||||
}
|
||||
|
||||
void m72_state::init_gallop()
|
||||
{
|
||||
m_maincpu->space(AS_IO).install_write_handler(0xc0, 0xc1, write16_delegate(*this, FUNC(m72_state::gallop_sample_trigger_w)));
|
||||
m_maincpu->space(AS_IO).install_write_handler(0xc0, 0xc1, write16s_delegate(*this, FUNC(m72_state::gallop_sample_trigger_w)));
|
||||
}
|
||||
|
||||
|
||||
|
@ -39,7 +39,7 @@ void m90_state::machine_start()
|
||||
|
||||
/***************************************************************************/
|
||||
|
||||
WRITE16_MEMBER(m90_state::coincounter_w)
|
||||
void m90_state::coincounter_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_0_7)
|
||||
{
|
||||
@ -50,14 +50,14 @@ WRITE16_MEMBER(m90_state::coincounter_w)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(m90_state::quizf1_bankswitch_w)
|
||||
void m90_state::quizf1_bankswitch_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_0_7)
|
||||
m_mainbank->set_entry(data & 0xf);
|
||||
}
|
||||
|
||||
#ifdef UNUSED_FUNCTION
|
||||
WRITE16_MEMBER(m90_state::unknown_w)
|
||||
void m90_state::unknown_w(uint16_t data)
|
||||
{
|
||||
printf("%04x ",data);
|
||||
}
|
||||
|
@ -254,13 +254,13 @@ TIMER_DEVICE_CALLBACK_MEMBER(m92_state::scanline_interrupt)
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
READ16_MEMBER(m92_state::eeprom_r)
|
||||
uint16_t m92_state::eeprom_r(offs_t offset)
|
||||
{
|
||||
// logerror("%05x: EEPROM RE %04x\n",m_maincpu->pc(),offset);
|
||||
return m_eeprom[offset] | 0xff00;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(m92_state::eeprom_w)
|
||||
void m92_state::eeprom_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
// logerror("%05x: EEPROM WR %04x\n",m_maincpu->pc(),offset);
|
||||
if (ACCESSING_BITS_0_7)
|
||||
@ -289,7 +289,7 @@ READ_LINE_MEMBER(m92_state::sprite_busy_r)
|
||||
}
|
||||
|
||||
template<int Layer>
|
||||
WRITE16_MEMBER(m92_state::pf_control_w)
|
||||
void m92_state::pf_control_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
//Fix for nbbm stage start screen
|
||||
//m_screen->update_partial(m_screen->vpos());
|
||||
@ -298,7 +298,7 @@ WRITE16_MEMBER(m92_state::pf_control_w)
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
WRITE16_MEMBER(m92_state::sound_reset_w)
|
||||
void m92_state::sound_reset_w(uint16_t data)
|
||||
{
|
||||
if (m_soundcpu)
|
||||
m_soundcpu->set_input_line(INPUT_LINE_RESET, (data) ? CLEAR_LINE : ASSERT_LINE);
|
||||
@ -371,7 +371,7 @@ void m92_state::m92_banked_portmap(address_map &map)
|
||||
map(0x20, 0x20).w(FUNC(m92_state::bankswitch_w));
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(m92_state::oki_bank_w)
|
||||
void m92_state::oki_bank_w(uint16_t data)
|
||||
{
|
||||
m_oki->set_rom_bank((data+1) & 0x3); // +1?
|
||||
}
|
||||
|
@ -117,12 +117,12 @@ WRITE_LINE_MEMBER(mac_state::mac_rbv_vbl)
|
||||
}
|
||||
}
|
||||
|
||||
READ32_MEMBER( mac_state::rbv_ramdac_r )
|
||||
uint32_t mac_state::rbv_ramdac_r()
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER( mac_state::rbv_ramdac_w )
|
||||
void mac_state::rbv_ramdac_w(offs_t offset, uint32_t data)
|
||||
{
|
||||
if (!offset)
|
||||
{
|
||||
@ -158,7 +158,7 @@ WRITE32_MEMBER( mac_state::rbv_ramdac_w )
|
||||
}
|
||||
}
|
||||
|
||||
WRITE32_MEMBER( mac_state::ariel_ramdac_w ) // this is for the "Ariel" style RAMDAC
|
||||
void mac_state::ariel_ramdac_w(offs_t offset, uint32_t data, uint32_t mem_mask) // this is for the "Ariel" style RAMDAC
|
||||
{
|
||||
if (mem_mask == 0xff000000)
|
||||
{
|
||||
@ -422,19 +422,19 @@ VIDEO_START_MEMBER(mac_state,macprtb)
|
||||
{
|
||||
}
|
||||
|
||||
READ16_MEMBER(mac_state::mac_config_r)
|
||||
uint16_t mac_state::mac_config_r()
|
||||
{
|
||||
return 0xffff; // returns nonzero if no PDS RAM expansion, 0 if present
|
||||
}
|
||||
|
||||
// IIfx
|
||||
READ32_MEMBER(mac_state::biu_r)
|
||||
uint32_t mac_state::biu_r(offs_t offset, uint32_t mem_mask)
|
||||
{
|
||||
// printf("biu_r @ %x, mask %08x\n", offset, mem_mask);
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(mac_state::biu_w)
|
||||
void mac_state::biu_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
// printf("biu_w %x @ %x, mask %08x\n", data, offset, mem_mask);
|
||||
}
|
||||
@ -456,7 +456,7 @@ WRITE8_MEMBER(mac_state::oss_w)
|
||||
m_oss_regs[offset] = data;
|
||||
}
|
||||
|
||||
READ32_MEMBER(mac_state::buserror_r)
|
||||
uint32_t mac_state::buserror_r()
|
||||
{
|
||||
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
|
||||
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
|
||||
|
@ -47,14 +47,14 @@
|
||||
#include "softlist.h"
|
||||
#include "speaker.h"
|
||||
|
||||
READ64_MEMBER( macpci_state::unk1_r )
|
||||
uint64_t macpci_state::unk1_r()
|
||||
{
|
||||
m_unk1_test ^= 0x0400; //PC=ff808760
|
||||
|
||||
return m_unk1_test << 16;
|
||||
}
|
||||
|
||||
READ64_MEMBER( macpci_state::unk2_r )
|
||||
uint64_t macpci_state::unk2_r(offs_t offset, uint64_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_32_47)
|
||||
return (uint64_t)0xe1 << 32; //PC=fff04810
|
||||
|
@ -293,7 +293,7 @@ Notes:
|
||||
|
||||
/*** VARIOUS READ / WRITE HANDLERS *******************************************/
|
||||
|
||||
READ32_MEMBER(macrossp_state::macrossp_soundstatus_r)
|
||||
uint32_t macrossp_state::macrossp_soundstatus_r()
|
||||
{
|
||||
// logerror("%08x read soundstatus\n", m_maincpu->pc());
|
||||
|
||||
@ -305,7 +305,7 @@ READ32_MEMBER(macrossp_state::macrossp_soundstatus_r)
|
||||
return (m_sndpending << 1) | m_snd_toggle;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(macrossp_state::macrossp_soundcmd_w)
|
||||
void macrossp_state::macrossp_soundcmd_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_16_31)
|
||||
{
|
||||
@ -318,14 +318,14 @@ WRITE32_MEMBER(macrossp_state::macrossp_soundcmd_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(macrossp_state::macrossp_soundcmd_r)
|
||||
uint16_t macrossp_state::macrossp_soundcmd_r()
|
||||
{
|
||||
// logerror("%06x read soundcmd\n",m_audiocpu->pc());
|
||||
m_sndpending = 0;
|
||||
return m_soundlatch->read();
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(macrossp_state::palette_fade_w)
|
||||
void macrossp_state::palette_fade_w(uint16_t data)
|
||||
{
|
||||
// 0xff is written a few times on startup
|
||||
if (data >> 8 != 0xff)
|
||||
@ -690,7 +690,7 @@ ROM_END
|
||||
|
||||
|
||||
|
||||
WRITE32_MEMBER(macrossp_state::macrossp_speedup_w)
|
||||
void macrossp_state::macrossp_speedup_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
/*
|
||||
PC :00018104 018104: addq.w #1, $f1015a.l
|
||||
@ -703,7 +703,7 @@ PC :00018110 018110: beq 18104
|
||||
}
|
||||
|
||||
#ifdef UNUSED_FUNCTION
|
||||
WRITE32_MEMBER(macrossp_state::quizmoon_speedup_w)
|
||||
void macrossp_state::quizmoon_speedup_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_mainram[0x00020 / 4]);
|
||||
if (m_maincpu->pc() == 0x1cc) m_maincpu->spin_until_interrupt();
|
||||
@ -712,13 +712,13 @@ WRITE32_MEMBER(macrossp_state::quizmoon_speedup_w)
|
||||
|
||||
void macrossp_state::init_macrossp()
|
||||
{
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xf10158, 0xf1015b, write32_delegate(*this, FUNC(macrossp_state::macrossp_speedup_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xf10158, 0xf1015b, write32s_delegate(*this, FUNC(macrossp_state::macrossp_speedup_w)));
|
||||
}
|
||||
|
||||
void macrossp_state::init_quizmoon()
|
||||
{
|
||||
#ifdef UNUSED_FUNCTION
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xf00020, 0xf00023, write32_delegate(*this, FUNC(macrossp_state::quizmoon_speedup_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xf00020, 0xf00023, write32s_delegate(*this, FUNC(macrossp_state::quizmoon_speedup_w)));
|
||||
#endif
|
||||
}
|
||||
|
||||
|
@ -33,7 +33,7 @@ Stephh's notes (based on the game M68000 code and some tests) :
|
||||
#include "speaker.h"
|
||||
|
||||
|
||||
WRITE16_MEMBER(magmax_state::cpu_irq_ack_w)
|
||||
void magmax_state::cpu_irq_ack_w(uint16_t data)
|
||||
{
|
||||
m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
|
||||
}
|
||||
@ -169,7 +169,7 @@ bit3 - SOUND Chan#8 name=AY-3-8910 #2 Ch C
|
||||
m_ay[2]->set_output_gain(2, percent);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(magmax_state::vreg_w)
|
||||
void magmax_state::vreg_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
/* VRAM CONTROL REGISTER */
|
||||
/* bit0 - coin counter 1 */
|
||||
|
@ -74,7 +74,7 @@
|
||||
*
|
||||
*************************************/
|
||||
|
||||
WRITE16_MEMBER(mcr68_state::xenophobe_control_w)
|
||||
void mcr68_state::xenophobe_control_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_control_word);
|
||||
/* m_sounds_good->reset_write(~m_control_word & 0x0020);*/
|
||||
@ -89,7 +89,7 @@ WRITE16_MEMBER(mcr68_state::xenophobe_control_w)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
WRITE16_MEMBER(mcr68_state::blasted_control_w)
|
||||
void mcr68_state::blasted_control_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_control_word);
|
||||
/* m_sounds_good->reset_write(~m_control_word & 0x0020);*/
|
||||
@ -104,7 +104,7 @@ WRITE16_MEMBER(mcr68_state::blasted_control_w)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ16_MEMBER(mcr68_state::spyhunt2_port_0_r)
|
||||
uint16_t mcr68_state::spyhunt2_port_0_r()
|
||||
{
|
||||
int result = ioport("IN0")->read();
|
||||
int analog = m_adc->read();
|
||||
@ -113,14 +113,14 @@ READ16_MEMBER(mcr68_state::spyhunt2_port_0_r)
|
||||
}
|
||||
|
||||
|
||||
READ16_MEMBER(mcr68_state::spyhunt2_port_1_r)
|
||||
uint16_t mcr68_state::spyhunt2_port_1_r()
|
||||
{
|
||||
int result = ioport("IN1")->read();
|
||||
return result | ((m_turbo_cheap_squeak->read() & 1) << 7);
|
||||
}
|
||||
|
||||
|
||||
WRITE16_MEMBER(mcr68_state::spyhunt2_control_w)
|
||||
void mcr68_state::spyhunt2_control_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_control_word);
|
||||
|
||||
@ -168,7 +168,7 @@ WRITE16_MEMBER(mcr68_state::spyhunt2_control_w)
|
||||
|
||||
static const uint8_t translate49[7] = { 0x7, 0x3, 0x1, 0x0, 0xc, 0xe, 0xf };
|
||||
|
||||
READ16_MEMBER(mcr68_state::archrivl_port_1_r)
|
||||
uint16_t mcr68_state::archrivl_port_1_r()
|
||||
{
|
||||
return (translate49[ioport("49WAYY2")->read() >> 4] << 12) |
|
||||
(translate49[ioport("49WAYX2")->read() >> 4] << 8) |
|
||||
@ -177,7 +177,7 @@ READ16_MEMBER(mcr68_state::archrivl_port_1_r)
|
||||
}
|
||||
|
||||
|
||||
WRITE16_MEMBER(mcr68_state::archrivl_control_w)
|
||||
void mcr68_state::archrivl_control_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_control_word);
|
||||
m_cvsd_sound->reset_write(~m_control_word & 0x0400);
|
||||
@ -192,7 +192,7 @@ WRITE16_MEMBER(mcr68_state::archrivl_control_w)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
WRITE16_MEMBER(mcr68_state::pigskin_protection_w)
|
||||
void mcr68_state::pigskin_protection_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
/* ignore upper-byte only */
|
||||
if (ACCESSING_BITS_0_7)
|
||||
@ -209,7 +209,7 @@ WRITE16_MEMBER(mcr68_state::pigskin_protection_w)
|
||||
}
|
||||
|
||||
|
||||
READ16_MEMBER(mcr68_state::pigskin_protection_r)
|
||||
uint16_t mcr68_state::pigskin_protection_r()
|
||||
{
|
||||
/* based on the last 5 bytes return a value */
|
||||
if (m_protection_data[4] == 0xe3 && m_protection_data[3] == 0x94)
|
||||
@ -229,7 +229,7 @@ READ16_MEMBER(mcr68_state::pigskin_protection_r)
|
||||
}
|
||||
|
||||
|
||||
READ16_MEMBER(mcr68_state::pigskin_port_1_r)
|
||||
uint16_t mcr68_state::pigskin_port_1_r()
|
||||
{
|
||||
/* see archrivl_port_1_r for 49-way joystick description */
|
||||
return ioport("IN1")->read() |
|
||||
@ -238,7 +238,7 @@ READ16_MEMBER(mcr68_state::pigskin_port_1_r)
|
||||
}
|
||||
|
||||
|
||||
READ16_MEMBER(mcr68_state::pigskin_port_2_r)
|
||||
uint16_t mcr68_state::pigskin_port_2_r()
|
||||
{
|
||||
/* see archrivl_port_1_r for 49-way joystick description */
|
||||
return ioport("DSW")->read() |
|
||||
@ -254,7 +254,7 @@ READ16_MEMBER(mcr68_state::pigskin_port_2_r)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ16_MEMBER(mcr68_state::trisport_port_1_r)
|
||||
uint16_t mcr68_state::trisport_port_1_r()
|
||||
{
|
||||
int xaxis = (int8_t)ioport("AN1")->read();
|
||||
int yaxis = (int8_t)ioport("AN2")->read();
|
||||
@ -1488,7 +1488,7 @@ void mcr68_state::init_xenophob()
|
||||
m_timing_factor = attotime::from_hz(m_maincpu->unscaled_clock() / 10) * (256 + 16);
|
||||
|
||||
/* install control port handler */
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x0c0000, 0x0cffff, write16_delegate(*this, FUNC(mcr68_state::xenophobe_control_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x0c0000, 0x0cffff, write16s_delegate(*this, FUNC(mcr68_state::xenophobe_control_w)));
|
||||
}
|
||||
|
||||
|
||||
@ -1500,9 +1500,9 @@ void mcr68_state::init_spyhunt2()
|
||||
m_timing_factor = attotime::from_hz(m_maincpu->unscaled_clock() / 10) * (256 + 16);
|
||||
|
||||
/* analog port handling is a bit tricky */
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x0c0000, 0x0cffff, write16_delegate(*this, FUNC(mcr68_state::spyhunt2_control_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x0d0000, 0x0dffff, read16_delegate(*this, FUNC(mcr68_state::spyhunt2_port_0_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x0e0000, 0x0effff, read16_delegate(*this, FUNC(mcr68_state::spyhunt2_port_1_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x0c0000, 0x0cffff, write16s_delegate(*this, FUNC(mcr68_state::spyhunt2_control_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x0d0000, 0x0dffff, read16smo_delegate(*this, FUNC(mcr68_state::spyhunt2_port_0_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x0e0000, 0x0effff, read16smo_delegate(*this, FUNC(mcr68_state::spyhunt2_port_1_r)));
|
||||
}
|
||||
|
||||
|
||||
@ -1516,7 +1516,7 @@ void mcr68_state::init_blasted()
|
||||
m_timing_factor = attotime::from_hz(m_maincpu->unscaled_clock() / 10) * (256 + 16);
|
||||
|
||||
/* handle control writes */
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x0c0000, 0x0cffff, write16_delegate(*this, FUNC(mcr68_state::blasted_control_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x0c0000, 0x0cffff, write16s_delegate(*this, FUNC(mcr68_state::blasted_control_w)));
|
||||
}
|
||||
|
||||
void mcr68_state::init_intlaser()
|
||||
@ -1527,7 +1527,7 @@ void mcr68_state::init_intlaser()
|
||||
m_timing_factor = attotime::from_hz(m_maincpu->unscaled_clock() / 10) * (256 + 16);
|
||||
|
||||
/* handle control writes */
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x0c0000, 0x0cffff, write16_delegate(*this, FUNC(mcr68_state::blasted_control_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x0c0000, 0x0cffff, write16s_delegate(*this, FUNC(mcr68_state::blasted_control_w)));
|
||||
|
||||
}
|
||||
|
||||
@ -1541,13 +1541,13 @@ void mcr68_state::init_archrivl()
|
||||
m_timing_factor = attotime::from_hz(m_maincpu->unscaled_clock() / 10) * (256 + 16);
|
||||
|
||||
/* handle control writes */
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x0c0000, 0x0cffff, write16_delegate(*this, FUNC(mcr68_state::archrivl_control_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x0c0000, 0x0cffff, write16s_delegate(*this, FUNC(mcr68_state::archrivl_control_w)));
|
||||
|
||||
/* 49-way joystick handling is a bit tricky */
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x0e0000, 0x0effff, read16_delegate(*this, FUNC(mcr68_state::archrivl_port_1_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x0e0000, 0x0effff, read16smo_delegate(*this, FUNC(mcr68_state::archrivl_port_1_r)));
|
||||
}
|
||||
|
||||
READ16_MEMBER(mcr68_state::archrivlb_port_1_r)
|
||||
uint16_t mcr68_state::archrivlb_port_1_r()
|
||||
{
|
||||
return ioport("IN1")->read();
|
||||
}
|
||||
@ -1560,10 +1560,10 @@ void mcr68_state::init_archrivlb()
|
||||
m_timing_factor = attotime::from_hz(m_maincpu->unscaled_clock() / 10) * (256 + 16);
|
||||
|
||||
/* handle control writes */
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x0c0000, 0x0cffff, write16_delegate(*this, FUNC(mcr68_state::archrivl_control_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x0c0000, 0x0cffff, write16s_delegate(*this, FUNC(mcr68_state::archrivl_control_w)));
|
||||
|
||||
/* 49-way joystick replaced by standard 8way stick */
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x0e0000, 0x0effff, read16_delegate(*this, FUNC(mcr68_state::archrivlb_port_1_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x0e0000, 0x0effff, read16smo_delegate(*this, FUNC(mcr68_state::archrivlb_port_1_r)));
|
||||
}
|
||||
|
||||
|
||||
|
@ -301,7 +301,7 @@ void md_boot_state::md_bootleg(machine_config &config)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
WRITE16_MEMBER(md_boot_state::aladmdb_w )
|
||||
void md_boot_state::aladmdb_w(uint16_t data)
|
||||
{
|
||||
/*
|
||||
Values returned from the log file :
|
||||
@ -313,7 +313,7 @@ WRITE16_MEMBER(md_boot_state::aladmdb_w )
|
||||
logerror("aladmdb_w : %06x - data = %04x\n",m_maincpu->pc(),data);
|
||||
}
|
||||
|
||||
READ16_MEMBER(md_boot_state::aladmdb_r )
|
||||
uint16_t md_boot_state::aladmdb_r()
|
||||
{
|
||||
if (m_maincpu->pc()==0x1b2a56)
|
||||
{
|
||||
@ -332,7 +332,7 @@ READ16_MEMBER(md_boot_state::aladmdb_r )
|
||||
return 0x0000;
|
||||
}
|
||||
|
||||
READ16_MEMBER(md_boot_state::twinktmb_r )
|
||||
uint16_t md_boot_state::twinktmb_r()
|
||||
{
|
||||
if (m_maincpu->pc()==0x02f81e)
|
||||
return ioport("COIN")->read(); // TODO: coins don't respond well
|
||||
@ -344,7 +344,7 @@ READ16_MEMBER(md_boot_state::twinktmb_r )
|
||||
return 0x0000;
|
||||
}
|
||||
|
||||
READ16_MEMBER(md_boot_state::jparkmb_r )
|
||||
uint16_t md_boot_state::jparkmb_r()
|
||||
{
|
||||
if (m_maincpu->pc()==0x1e327a)
|
||||
return ioport("COIN")->read(); // TODO: coins don't respond well
|
||||
@ -356,31 +356,31 @@ READ16_MEMBER(md_boot_state::jparkmb_r )
|
||||
return 0x0000;
|
||||
}
|
||||
|
||||
READ16_MEMBER(md_boot_state::mk3mdb_dsw_r )
|
||||
uint16_t md_boot_state::mk3mdb_dsw_r(offs_t offset)
|
||||
{
|
||||
static const char *const dswname[3] = { "DSWA", "DSWB", "DSWC" };
|
||||
return ioport(dswname[offset])->read();
|
||||
}
|
||||
|
||||
READ16_MEMBER(md_boot_state::ssf2mdb_dsw_r )
|
||||
uint16_t md_boot_state::ssf2mdb_dsw_r(offs_t offset)
|
||||
{
|
||||
static const char *const dswname[3] = { "DSWA", "DSWB", "DSWC" };
|
||||
return ioport(dswname[offset])->read();
|
||||
}
|
||||
|
||||
READ16_MEMBER(md_boot_state::srmdb_dsw_r )
|
||||
uint16_t md_boot_state::srmdb_dsw_r(offs_t offset)
|
||||
{
|
||||
static const char *const dswname[3] = { "DSWA", "DSWB", "DSWC" };
|
||||
return ioport(dswname[offset])->read();
|
||||
}
|
||||
|
||||
READ16_MEMBER(md_boot_state::topshoot_200051_r )
|
||||
uint16_t md_boot_state::topshoot_200051_r()
|
||||
{
|
||||
return -0x5b;
|
||||
}
|
||||
|
||||
// jzth protection
|
||||
WRITE16_MEMBER(md_boot_state::bl_710000_w)
|
||||
void md_boot_state::bl_710000_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
int pc = m_maincpu->pc();
|
||||
|
||||
@ -435,7 +435,7 @@ WRITE16_MEMBER(md_boot_state::bl_710000_w)
|
||||
}
|
||||
|
||||
|
||||
READ16_MEMBER(md_boot_state::bl_710000_r)
|
||||
uint16_t md_boot_state::bl_710000_r()
|
||||
{
|
||||
uint16_t ret;
|
||||
int pc = m_maincpu->pc();
|
||||
@ -956,8 +956,8 @@ void md_boot_state::init_aladmdb()
|
||||
#endif
|
||||
|
||||
// 220000 = writes to mcu? 330000 = reads?
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x220000, 0x220001, write16_delegate(*this, FUNC(md_boot_state::aladmdb_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x330000, 0x330001, read16_delegate(*this, FUNC(md_boot_state::aladmdb_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x220000, 0x220001, write16smo_delegate(*this, FUNC(md_boot_state::aladmdb_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x330000, 0x330001, read16smo_delegate(*this, FUNC(md_boot_state::aladmdb_r)));
|
||||
|
||||
init_megadrij();
|
||||
}
|
||||
@ -1005,7 +1005,7 @@ void md_boot_state::init_mk3mdb()
|
||||
rom[0x07] = 0x02;
|
||||
rom[0x06] = 0x10;
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x770070, 0x770075, read16_delegate(*this, FUNC(md_boot_state::mk3mdb_dsw_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x770070, 0x770075, read16sm_delegate(*this, FUNC(md_boot_state::mk3mdb_dsw_r)));
|
||||
|
||||
init_megadriv();
|
||||
// 6 button game, so overwrite 3 button io handlers
|
||||
@ -1021,7 +1021,7 @@ void md_boot_state::init_ssf2mdb()
|
||||
|
||||
membank("bank5")->set_base(memregion( "maincpu" )->base() + 0x400000 );
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x770070, 0x770075, read16_delegate(*this, FUNC(md_boot_state::ssf2mdb_dsw_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x770070, 0x770075, read16sm_delegate(*this, FUNC(md_boot_state::ssf2mdb_dsw_r)));
|
||||
|
||||
init_megadrij();
|
||||
// 6 button game, so overwrite 3 button io handlers
|
||||
@ -1052,14 +1052,14 @@ void md_boot_state::init_srmdb()
|
||||
rom[0x06] = 0xd2;
|
||||
rom[0x07] = 0x00;
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x770070, 0x770075, read16_delegate(*this, FUNC(md_boot_state::srmdb_dsw_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x770070, 0x770075, read16sm_delegate(*this, FUNC(md_boot_state::srmdb_dsw_r)));
|
||||
|
||||
init_megadriv();
|
||||
}
|
||||
|
||||
void md_boot_state::init_topshoot()
|
||||
{
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x200050, 0x200051, read16_delegate(*this, FUNC(md_boot_state::topshoot_200051_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x200050, 0x200051, read16smo_delegate(*this, FUNC(md_boot_state::topshoot_200051_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_port(0x200042, 0x200043, "IN0");
|
||||
m_maincpu->space(AS_PROGRAM).install_read_port(0x200044, 0x200045, "IN1");
|
||||
m_maincpu->space(AS_PROGRAM).install_read_port(0x200046, 0x200047, "IN2");
|
||||
@ -1086,7 +1086,7 @@ void md_boot_state::init_barek3()
|
||||
void md_boot_state::init_sonic2mb()
|
||||
{
|
||||
// 100000 = writes to unpopulated MCU?
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x100000, 0x100001, write16_delegate(*this, FUNC(md_boot_state::aladmdb_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x100000, 0x100001, write16smo_delegate(*this, FUNC(md_boot_state::aladmdb_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_port(0x300000, 0x300001, "DSW");
|
||||
|
||||
init_megadrij();
|
||||
@ -1103,15 +1103,15 @@ void md_boot_state::init_twinktmb()
|
||||
rom[0x06] = 0xcc;
|
||||
|
||||
init_megadrij();
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x100000, 0x100001, write16_delegate(*this, FUNC(md_boot_state::aladmdb_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x300000, 0x300001, read16_delegate(*this, FUNC(md_boot_state::twinktmb_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x100000, 0x100001, write16smo_delegate(*this, FUNC(md_boot_state::aladmdb_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x300000, 0x300001, read16smo_delegate(*this, FUNC(md_boot_state::twinktmb_r)));
|
||||
}
|
||||
|
||||
void md_boot_state::init_jparkmb()
|
||||
{
|
||||
init_megadrij();
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x100000, 0x100001, write16_delegate(*this, FUNC(md_boot_state::aladmdb_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x300000, 0x300001, read16_delegate(*this, FUNC(md_boot_state::jparkmb_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x100000, 0x100001, write16smo_delegate(*this, FUNC(md_boot_state::aladmdb_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x300000, 0x300001, read16smo_delegate(*this, FUNC(md_boot_state::jparkmb_r)));
|
||||
}
|
||||
|
||||
/*************************************
|
||||
|
@ -39,12 +39,12 @@ void megadriv_radica_state::megadriv_radica_map(address_map &map)
|
||||
map(0xe00000, 0xe0ffff).ram().mirror(0x1f0000).share("megadrive_ram");
|
||||
}
|
||||
|
||||
READ16_MEMBER(megadriv_radica_state::read)
|
||||
uint16_t megadriv_radica_state::read(offs_t offset)
|
||||
{
|
||||
return m_rom[(((m_bank * 0x10000) + (offset << 1)) & (0x400000 - 1))/2];
|
||||
}
|
||||
|
||||
READ16_MEMBER(megadriv_radica_state::read_a13)
|
||||
uint16_t megadriv_radica_state::read_a13(offs_t offset)
|
||||
{
|
||||
if (offset < 0x80)
|
||||
m_bank = offset & 0x3f;
|
||||
|
@ -264,14 +264,14 @@ TIMER_DEVICE_CALLBACK_MEMBER(megasys1_state::megasys1B_scanline)
|
||||
|
||||
in that order. */
|
||||
|
||||
READ16_MEMBER(megasys1_state::ip_select_r) // FROM MCU
|
||||
u16 megasys1_state::ip_select_r() // FROM MCU
|
||||
{
|
||||
return m_ip_latched;
|
||||
}
|
||||
|
||||
|
||||
|
||||
WRITE16_MEMBER(megasys1_state::ip_select_w) // TO MCU
|
||||
void megasys1_state::ip_select_w(u16 data) // TO MCU
|
||||
{
|
||||
int i;
|
||||
|
||||
@ -362,7 +362,7 @@ void megasys1_state::megasys1B_monkelf_map(address_map &map)
|
||||
#define INTERRUPT_NUM_C INTERRUPT_NUM_B
|
||||
#define interrupt_C interrupt_B
|
||||
|
||||
WRITE16_MEMBER(megasys1_state::ram_w)
|
||||
void megasys1_state::ram_w(offs_t offset, u16 data)
|
||||
{
|
||||
// DON'T use COMBINE_DATA
|
||||
// byte writes end up mirroring in both bytes of the word like nmk16.cpp
|
||||
@ -1639,7 +1639,7 @@ INPUT_PORTS_END
|
||||
|
||||
|
||||
/* Read the input ports, through a protection device */
|
||||
READ16_MEMBER(megasys1_state::protection_peekaboo_r)
|
||||
u16 megasys1_state::protection_peekaboo_r()
|
||||
{
|
||||
switch (m_protection_val)
|
||||
{
|
||||
@ -1650,7 +1650,7 @@ READ16_MEMBER(megasys1_state::protection_peekaboo_r)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(megasys1_state::protection_peekaboo_w)
|
||||
void megasys1_state::protection_peekaboo_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_protection_val);
|
||||
|
||||
@ -4644,7 +4644,7 @@ void megasys1_state::init_64street()
|
||||
save_item(NAME(m_sprite_bank));
|
||||
}
|
||||
|
||||
READ16_MEMBER(megasys1_state::megasys1A_mcu_hs_r)
|
||||
u16 megasys1_state::megasys1A_mcu_hs_r(offs_t offset, u16 mem_mask)
|
||||
{
|
||||
if(m_mcu_hs && ((m_mcu_hs_ram[8/2] << 6) & 0x3ffc0) == ((offset*2) & 0x3ffc0))
|
||||
{
|
||||
@ -4657,7 +4657,7 @@ READ16_MEMBER(megasys1_state::megasys1A_mcu_hs_r)
|
||||
return m_rom_maincpu[offset];
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(megasys1_state::megasys1A_mcu_hs_w)
|
||||
void megasys1_state::megasys1A_mcu_hs_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
// following is hachoo, other games differs slightly
|
||||
// R 0x5f0, if bit 0 == 0 then skips hs seq (debug?)
|
||||
@ -4683,8 +4683,8 @@ WRITE16_MEMBER(megasys1_state::megasys1A_mcu_hs_w)
|
||||
void megasys1_state::init_astyanax()
|
||||
{
|
||||
astyanax_rom_decode(machine(), "maincpu");
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x00000, 0x3ffff, read16_delegate(*this, FUNC(megasys1_state::megasys1A_mcu_hs_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x20000, 0x20009, write16_delegate(*this, FUNC(megasys1_state::megasys1A_mcu_hs_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x00000, 0x3ffff, read16s_delegate(*this, FUNC(megasys1_state::megasys1A_mcu_hs_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x20000, 0x20009, write16s_delegate(*this, FUNC(megasys1_state::megasys1A_mcu_hs_w)));
|
||||
|
||||
m_mcu_hs = 0;
|
||||
memset(m_mcu_hs_ram, 0, sizeof(m_mcu_hs_ram));
|
||||
@ -4791,7 +4791,7 @@ void megasys1_state::init_hayaosi1()
|
||||
save_item(NAME(m_ip_latched));
|
||||
}
|
||||
|
||||
READ16_MEMBER(megasys1_state::iganinju_mcu_hs_r)
|
||||
u16 megasys1_state::iganinju_mcu_hs_r(offs_t offset, u16 mem_mask)
|
||||
{
|
||||
if(m_mcu_hs && ((m_mcu_hs_ram[8/2] << 6) & 0x3ffc0) == ((offset*2) & 0x3ffc0))
|
||||
{
|
||||
@ -4804,7 +4804,7 @@ READ16_MEMBER(megasys1_state::iganinju_mcu_hs_r)
|
||||
return m_rom_maincpu[offset];
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(megasys1_state::iganinju_mcu_hs_w)
|
||||
void megasys1_state::iganinju_mcu_hs_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
// [0/2]: 0x0000
|
||||
// [2/2]: 0x0055
|
||||
@ -4828,8 +4828,8 @@ void megasys1_state::init_iganinju()
|
||||
{
|
||||
phantasm_rom_decode(machine(), "maincpu");
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x00000, 0x3ffff, read16_delegate(*this, FUNC(megasys1_state::iganinju_mcu_hs_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x2f000, 0x2f009, write16_delegate(*this, FUNC(megasys1_state::iganinju_mcu_hs_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x00000, 0x3ffff, read16s_delegate(*this, FUNC(megasys1_state::iganinju_mcu_hs_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x2f000, 0x2f009, write16s_delegate(*this, FUNC(megasys1_state::iganinju_mcu_hs_w)));
|
||||
|
||||
//m_rom_maincpu[0x00006e/2] = 0x0420; // the only game that does
|
||||
// not like lev 3 interrupts
|
||||
@ -4847,8 +4847,8 @@ void megasys1_state::init_jitsupro()
|
||||
|
||||
jitsupro_gfx_unmangle("scroll0"); // Gfx
|
||||
jitsupro_gfx_unmangle("sprites");
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x00000, 0x3ffff, read16_delegate(*this, FUNC(megasys1_state::megasys1A_mcu_hs_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x20000, 0x20009, write16_delegate(*this, FUNC(megasys1_state::megasys1A_mcu_hs_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x00000, 0x3ffff, read16s_delegate(*this, FUNC(megasys1_state::megasys1A_mcu_hs_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x20000, 0x20009, write16s_delegate(*this, FUNC(megasys1_state::megasys1A_mcu_hs_w)));
|
||||
|
||||
m_mcu_hs = 0;
|
||||
memset(m_mcu_hs_ram, 0, sizeof(m_mcu_hs_ram));
|
||||
@ -4864,7 +4864,8 @@ void megasys1_state::init_peekaboo()
|
||||
m_okibank->configure_entry(7, &ROM[0x20000]);
|
||||
m_okibank->configure_entries(0, 7, &ROM[0x20000], 0x20000);
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x100000, 0x100001, read16_delegate(*this, FUNC(megasys1_state::protection_peekaboo_r)), write16_delegate(*this, FUNC(megasys1_state::protection_peekaboo_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x100000, 0x100001, read16smo_delegate(*this, FUNC(megasys1_state::protection_peekaboo_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x100000, 0x100001, write16s_delegate(*this, FUNC(megasys1_state::protection_peekaboo_w)));
|
||||
|
||||
save_item(NAME(m_protection_val));
|
||||
}
|
||||
@ -4901,12 +4902,12 @@ void megasys1_state::init_rittam()
|
||||
astyanax_rom_decode(machine(), "maincpu");
|
||||
}
|
||||
|
||||
READ16_MEMBER(megasys1_state::soldamj_spriteram16_r)
|
||||
u16 megasys1_state::soldamj_spriteram16_r(offs_t offset)
|
||||
{
|
||||
return m_spriteram[offset];
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(megasys1_state::soldamj_spriteram16_w)
|
||||
void megasys1_state::soldamj_spriteram16_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
if (offset < 0x800/2) COMBINE_DATA(&m_spriteram[offset]);
|
||||
}
|
||||
@ -4915,18 +4916,20 @@ void megasys1_state::init_soldamj()
|
||||
{
|
||||
astyanax_rom_decode(machine(), "maincpu");
|
||||
/* Sprite RAM is mirrored */
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x8c000, 0x8cfff, read16_delegate(*this, FUNC(megasys1_state::soldamj_spriteram16_r)), write16_delegate(*this, FUNC(megasys1_state::soldamj_spriteram16_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x8c000, 0x8cfff, read16sm_delegate(*this, FUNC(megasys1_state::soldamj_spriteram16_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x8c000, 0x8cfff, write16s_delegate(*this, FUNC(megasys1_state::soldamj_spriteram16_w)));
|
||||
}
|
||||
|
||||
void megasys1_state::init_soldam()
|
||||
{
|
||||
phantasm_rom_decode(machine(), "maincpu");
|
||||
/* Sprite RAM is mirrored */
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x8c000, 0x8cfff, read16_delegate(*this, FUNC(megasys1_state::soldamj_spriteram16_r)), write16_delegate(*this, FUNC(megasys1_state::soldamj_spriteram16_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x8c000, 0x8cfff, read16sm_delegate(*this, FUNC(megasys1_state::soldamj_spriteram16_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x8c000, 0x8cfff, write16s_delegate(*this, FUNC(megasys1_state::soldamj_spriteram16_w)));
|
||||
}
|
||||
|
||||
|
||||
READ16_MEMBER(megasys1_state::stdragon_mcu_hs_r)
|
||||
u16 megasys1_state::stdragon_mcu_hs_r(offs_t offset, u16 mem_mask)
|
||||
{
|
||||
if(m_mcu_hs && ((m_mcu_hs_ram[8/2] << 6) & 0x3ffc0) == ((offset*2) & 0x3ffc0))
|
||||
{
|
||||
@ -4939,7 +4942,7 @@ READ16_MEMBER(megasys1_state::stdragon_mcu_hs_r)
|
||||
return m_rom_maincpu[offset];
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(megasys1_state::stdragon_mcu_hs_w)
|
||||
void megasys1_state::stdragon_mcu_hs_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_mcu_hs_ram[offset]);
|
||||
|
||||
@ -4956,8 +4959,8 @@ WRITE16_MEMBER(megasys1_state::stdragon_mcu_hs_w)
|
||||
void megasys1_state::init_stdragon()
|
||||
{
|
||||
phantasm_rom_decode(machine(), "maincpu");
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x00000, 0x3ffff, read16_delegate(*this, FUNC(megasys1_state::stdragon_mcu_hs_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x23ff0, 0x23ff9, write16_delegate(*this, FUNC(megasys1_state::stdragon_mcu_hs_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x00000, 0x3ffff, read16s_delegate(*this, FUNC(megasys1_state::stdragon_mcu_hs_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x23ff0, 0x23ff9, write16s_delegate(*this, FUNC(megasys1_state::stdragon_mcu_hs_w)));
|
||||
|
||||
m_mcu_hs = 0;
|
||||
memset(m_mcu_hs_ram, 0, sizeof(m_mcu_hs_ram));
|
||||
@ -4973,8 +4976,8 @@ void megasys1_state::init_stdragona()
|
||||
stdragona_gfx_unmangle("scroll0");
|
||||
stdragona_gfx_unmangle("sprites");
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x00000, 0x3ffff, read16_delegate(*this, FUNC(megasys1_state::stdragon_mcu_hs_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x23ff0, 0x23ff9, write16_delegate(*this, FUNC(megasys1_state::stdragon_mcu_hs_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x00000, 0x3ffff, read16s_delegate(*this, FUNC(megasys1_state::stdragon_mcu_hs_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x23ff0, 0x23ff9, write16s_delegate(*this, FUNC(megasys1_state::stdragon_mcu_hs_w)));
|
||||
|
||||
m_mcu_hs = 0;
|
||||
memset(m_mcu_hs_ram, 0, sizeof(m_mcu_hs_ram));
|
||||
|
@ -301,25 +301,25 @@ uint32_t metalmx_state::screen_update_metalmx(screen_device &screen, bitmap_ind1
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ32_MEMBER(metalmx_state::unk_r)
|
||||
uint32_t metalmx_state::unk_r()
|
||||
{
|
||||
return 0;//machine().rand();
|
||||
}
|
||||
|
||||
READ32_MEMBER(metalmx_state::watchdog_r)
|
||||
uint32_t metalmx_state::watchdog_r()
|
||||
{
|
||||
return 0xffffffff;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(metalmx_state::shifter_w)
|
||||
void metalmx_state::shifter_w(uint32_t data)
|
||||
{
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(metalmx_state::motor_w)
|
||||
void metalmx_state::motor_w(uint32_t data)
|
||||
{
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(metalmx_state::reset_w)
|
||||
void metalmx_state::reset_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_16_31)
|
||||
{
|
||||
@ -336,7 +336,7 @@ WRITE32_MEMBER(metalmx_state::reset_w)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ32_MEMBER(metalmx_state::sound_data_r)
|
||||
uint32_t metalmx_state::sound_data_r(offs_t offset, uint32_t mem_mask)
|
||||
{
|
||||
uint32_t result = 0;
|
||||
|
||||
@ -347,7 +347,7 @@ READ32_MEMBER(metalmx_state::sound_data_r)
|
||||
return result;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(metalmx_state::sound_data_w)
|
||||
void metalmx_state::sound_data_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_0_15)
|
||||
m_cage->control_w(data);
|
||||
@ -367,7 +367,7 @@ void metalmx_state::cage_irq_callback(uint8_t data)
|
||||
*************************************/
|
||||
|
||||
template<int Chip>
|
||||
WRITE32_MEMBER(metalmx_state::dsp32c_w)
|
||||
void metalmx_state::dsp32c_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
offset <<= 1;
|
||||
|
||||
@ -380,7 +380,7 @@ WRITE32_MEMBER(metalmx_state::dsp32c_w)
|
||||
}
|
||||
|
||||
template<int Chip>
|
||||
READ32_MEMBER(metalmx_state::dsp32c_r)
|
||||
uint32_t metalmx_state::dsp32c_r(offs_t offset, uint32_t mem_mask)
|
||||
{
|
||||
uint32_t data;
|
||||
|
||||
@ -404,7 +404,7 @@ READ32_MEMBER(metalmx_state::dsp32c_r)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
WRITE32_MEMBER(metalmx_state::host_gsp_w)
|
||||
void metalmx_state::host_gsp_w(offs_t offset, uint32_t data)
|
||||
{
|
||||
address_space &gsp_space = m_gsp->space(AS_PROGRAM);
|
||||
|
||||
@ -412,7 +412,7 @@ WRITE32_MEMBER(metalmx_state::host_gsp_w)
|
||||
gsp_space.write_word((0xc0000000 + (offset << 5))/ 8 , data >> 16);
|
||||
}
|
||||
|
||||
READ32_MEMBER(metalmx_state::host_gsp_r)
|
||||
uint32_t metalmx_state::host_gsp_r(offs_t offset)
|
||||
{
|
||||
address_space &gsp_space = m_gsp->space(AS_PROGRAM);
|
||||
uint32_t val;
|
||||
@ -423,12 +423,12 @@ READ32_MEMBER(metalmx_state::host_gsp_r)
|
||||
}
|
||||
|
||||
|
||||
READ32_MEMBER(metalmx_state::host_dram_r)
|
||||
uint32_t metalmx_state::host_dram_r(offs_t offset)
|
||||
{
|
||||
return (m_gsp_dram[offset * 2] << 16) | m_gsp_dram[offset * 2 + 1];
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(metalmx_state::host_dram_w)
|
||||
void metalmx_state::host_dram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(m_gsp_dram + offset * 2 + 1);
|
||||
data >>= 16;
|
||||
@ -436,12 +436,12 @@ WRITE32_MEMBER(metalmx_state::host_dram_w)
|
||||
COMBINE_DATA(m_gsp_dram + offset * 2);
|
||||
}
|
||||
|
||||
READ32_MEMBER(metalmx_state::host_vram_r)
|
||||
uint32_t metalmx_state::host_vram_r(offs_t offset)
|
||||
{
|
||||
return (m_gsp_vram[offset * 2] << 16) | m_gsp_vram[offset * 2 + 1];
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(metalmx_state::host_vram_w)
|
||||
void metalmx_state::host_vram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(m_gsp_vram + offset * 2 + 1);
|
||||
data >>= 16;
|
||||
@ -450,7 +450,7 @@ WRITE32_MEMBER(metalmx_state::host_vram_w)
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(metalmx_state::timer_w)
|
||||
void metalmx_state::timer_w(offs_t offset, uint32_t data)
|
||||
{
|
||||
// Offsets
|
||||
// 9000 with 1 changes to external clock source
|
||||
|
@ -270,7 +270,7 @@ WRITE_LINE_MEMBER(metro_state::karatour_vblank_irq)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(metro_state::mouja_irq_timer_ctrl_w)
|
||||
void metro_state::mouja_irq_timer_ctrl_w(uint16_t data)
|
||||
{
|
||||
double freq = 58.0 + (0xff - (data & 0xff)) / 2.2; /* 0xff=58Hz, 0x80=116Hz? */
|
||||
|
||||
@ -478,7 +478,7 @@ WRITE8_MEMBER(metro_state::coin_lockout_1word_w)
|
||||
|
||||
// value written doesn't matter, also each counted coin gets reported after one full second.
|
||||
// TODO: maybe the counter also controls lockout?
|
||||
WRITE16_MEMBER(metro_state::coin_lockout_4words_w)
|
||||
void metro_state::coin_lockout_4words_w(offs_t offset, uint16_t data)
|
||||
{
|
||||
machine().bookkeeping().coin_counter_w((offset >> 1) & 1, offset & 1);
|
||||
// machine().bookkeeping().coin_lockout_w((offset >> 1) & 1, offset & 1);
|
||||
@ -528,7 +528,7 @@ void metro_state::ymf278_map(address_map &map)
|
||||
***************************************************************************/
|
||||
|
||||
/* Really weird way of mapping 3 DSWs */
|
||||
READ16_MEMBER(metro_state::balcube_dsw_r)
|
||||
uint16_t metro_state::balcube_dsw_r(offs_t offset)
|
||||
{
|
||||
uint16_t dsw1 = ioport("DSW0")->read() >> 0;
|
||||
uint16_t dsw2 = ioport("DSW0")->read() >> 8;
|
||||
@ -813,7 +813,7 @@ WRITE8_MEMBER(metro_state::gakusai_oki_bank_lo_w)
|
||||
}
|
||||
|
||||
|
||||
READ16_MEMBER(metro_state::gakusai_input_r)
|
||||
uint16_t metro_state::gakusai_input_r()
|
||||
{
|
||||
uint16_t input_sel = (*m_input_sel) ^ 0x3e;
|
||||
// Bit 0 ??
|
||||
@ -1238,7 +1238,7 @@ WRITE_LINE_MEMBER(puzzlet_io_device::clk_w)
|
||||
}
|
||||
|
||||
|
||||
WRITE16_MEMBER(metro_state::puzzlet_irq_enable_w)
|
||||
void metro_state::puzzlet_irq_enable_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_0_7)
|
||||
*m_irq_enable = data ^ 0xffff;
|
||||
|
@ -90,7 +90,7 @@ MACHINE_RESET_MEMBER(midvunit_state,midvplus)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ32_MEMBER(midvunit_state::port0_r)
|
||||
uint32_t midvunit_state::port0_r()
|
||||
{
|
||||
uint16_t val = ioport("IN0")->read();
|
||||
uint16_t diff = val ^ m_last_port0;
|
||||
@ -118,7 +118,7 @@ READ32_MEMBER(midvunit_state::port0_r)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ32_MEMBER( midvunit_state::adc_r )
|
||||
uint32_t midvunit_state::adc_r()
|
||||
{
|
||||
if (!(m_control_data & 0x40))
|
||||
return m_adc->read() << m_adc_shift;
|
||||
@ -128,7 +128,7 @@ READ32_MEMBER( midvunit_state::adc_r )
|
||||
return 0xffffffff;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER( midvunit_state::adc_w )
|
||||
void midvunit_state::adc_w(uint32_t data)
|
||||
{
|
||||
if (!(m_control_data & 0x20))
|
||||
m_adc->write(data >> m_adc_shift);
|
||||
@ -144,20 +144,20 @@ WRITE32_MEMBER( midvunit_state::adc_w )
|
||||
*
|
||||
*************************************/
|
||||
|
||||
WRITE32_MEMBER(midvunit_state::midvunit_cmos_protect_w)
|
||||
void midvunit_state::midvunit_cmos_protect_w(uint32_t data)
|
||||
{
|
||||
m_cmos_protected = ((data & 0xc00) != 0xc00);
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(midvunit_state::midvunit_cmos_w)
|
||||
void midvunit_state::midvunit_cmos_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
if (!m_cmos_protected)
|
||||
COMBINE_DATA(m_nvram + offset);
|
||||
}
|
||||
|
||||
|
||||
READ32_MEMBER(midvunit_state::midvunit_cmos_r)
|
||||
uint32_t midvunit_state::midvunit_cmos_r(offs_t offset)
|
||||
{
|
||||
return m_nvram[offset];
|
||||
}
|
||||
@ -170,7 +170,7 @@ READ32_MEMBER(midvunit_state::midvunit_cmos_r)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
WRITE32_MEMBER(midvunit_state::midvunit_control_w)
|
||||
void midvunit_state::midvunit_control_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
uint16_t olddata = m_control_data;
|
||||
COMBINE_DATA(&m_control_data);
|
||||
@ -190,7 +190,7 @@ WRITE32_MEMBER(midvunit_state::midvunit_control_w)
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(midvunit_state::crusnwld_control_w)
|
||||
void midvunit_state::crusnwld_control_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
uint16_t olddata = m_control_data;
|
||||
COMBINE_DATA(&m_control_data);
|
||||
@ -210,7 +210,7 @@ WRITE32_MEMBER(midvunit_state::crusnwld_control_w)
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(midvunit_state::midvunit_sound_w)
|
||||
void midvunit_state::midvunit_sound_w(uint32_t data)
|
||||
{
|
||||
logerror("Sound W = %02X\n", data);
|
||||
m_dcs->data_w(data & 0xff);
|
||||
@ -224,7 +224,7 @@ WRITE32_MEMBER(midvunit_state::midvunit_sound_w)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ32_MEMBER(midvunit_state::tms32031_control_r)
|
||||
uint32_t midvunit_state::tms32031_control_r(offs_t offset)
|
||||
{
|
||||
/* watch for accesses to the timers */
|
||||
if (offset == 0x24 || offset == 0x34)
|
||||
@ -244,7 +244,7 @@ READ32_MEMBER(midvunit_state::tms32031_control_r)
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(midvunit_state::tms32031_control_w)
|
||||
void midvunit_state::tms32031_control_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_tms32031_control[offset]);
|
||||
|
||||
@ -278,20 +278,20 @@ WRITE32_MEMBER(midvunit_state::tms32031_control_w)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ32_MEMBER(midvunit_state::crusnwld_serial_status_r)
|
||||
uint32_t midvunit_state::crusnwld_serial_status_r()
|
||||
{
|
||||
uint16_t in1 = (m_in1->read() & 0x7fff) | (m_midway_serial_pic->status_r() << 15);
|
||||
return in1 | in1 << 16;
|
||||
}
|
||||
|
||||
|
||||
READ32_MEMBER(midvunit_state::crusnwld_serial_data_r)
|
||||
uint32_t midvunit_state::crusnwld_serial_data_r()
|
||||
{
|
||||
return m_midway_serial_pic->read() << 16;
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(midvunit_state::crusnwld_serial_data_w)
|
||||
void midvunit_state::crusnwld_serial_data_w(uint32_t data)
|
||||
{
|
||||
if ((data & 0xf0000) == 0x10000)
|
||||
{
|
||||
@ -319,7 +319,7 @@ static const uint32_t bit_data[0x10] =
|
||||
};
|
||||
|
||||
|
||||
READ32_MEMBER(midvunit_state::bit_data_r)
|
||||
uint32_t midvunit_state::bit_data_r(offs_t offset)
|
||||
{
|
||||
int bit = (bit_data[m_bit_index / 32] >> (31 - (m_bit_index % 32))) & 1;
|
||||
m_bit_index = (m_bit_index + 1) % 512;
|
||||
@ -327,7 +327,7 @@ READ32_MEMBER(midvunit_state::bit_data_r)
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(midvunit_state::bit_reset_w)
|
||||
void midvunit_state::bit_reset_w(uint32_t data)
|
||||
{
|
||||
m_bit_index = 0;
|
||||
}
|
||||
@ -340,25 +340,25 @@ WRITE32_MEMBER(midvunit_state::bit_reset_w)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ32_MEMBER(midvunit_state::offroadc_serial_status_r)
|
||||
uint32_t midvunit_state::offroadc_serial_status_r()
|
||||
{
|
||||
uint16_t in1 = (m_in1->read() & 0x7fff) | (m_midway_serial_pic2->status_r() << 15);
|
||||
return in1 | in1 << 16;
|
||||
}
|
||||
|
||||
|
||||
READ32_MEMBER(midvunit_state::offroadc_serial_data_r)
|
||||
uint32_t midvunit_state::offroadc_serial_data_r()
|
||||
{
|
||||
return m_midway_serial_pic2->read() << 16;
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(midvunit_state::offroadc_serial_data_w)
|
||||
void midvunit_state::offroadc_serial_data_w(uint32_t data)
|
||||
{
|
||||
m_midway_serial_pic2->write(data >> 16);
|
||||
}
|
||||
|
||||
READ32_MEMBER(midvunit_state::midvunit_wheel_board_r)
|
||||
uint32_t midvunit_state::midvunit_wheel_board_r()
|
||||
{
|
||||
//logerror("midvunit_wheel_board_r: %08X\n", m_wheel_board_output);
|
||||
return m_wheel_board_output << 8;
|
||||
@ -371,7 +371,7 @@ void midvunit_state::set_input(const char *s)
|
||||
m_galil_input_length = strlen(s);
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(midvunit_state::midvunit_wheel_board_w)
|
||||
void midvunit_state::midvunit_wheel_board_w(uint32_t data)
|
||||
{
|
||||
//logerror("midvunit_wheel_board_w: %08X\n", data);
|
||||
|
||||
@ -500,7 +500,7 @@ DECLARE_CUSTOM_INPUT_MEMBER(midvunit_state::motion_r)
|
||||
}
|
||||
|
||||
|
||||
READ32_MEMBER(midvunit_state::midvunit_intcs_r)
|
||||
uint32_t midvunit_state::midvunit_intcs_r()
|
||||
{
|
||||
return 4;
|
||||
}
|
||||
@ -523,7 +523,7 @@ uint16_t midvunit_state::comm_bus_in()
|
||||
return comm_bus_out();
|
||||
}
|
||||
|
||||
READ32_MEMBER(midvunit_state::midvunit_comcs_r)
|
||||
uint32_t midvunit_state::midvunit_comcs_r(offs_t offset)
|
||||
{
|
||||
if (offset != 0)
|
||||
{
|
||||
@ -541,7 +541,7 @@ READ32_MEMBER(midvunit_state::midvunit_comcs_r)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(midvunit_state::midvunit_comcs_w)
|
||||
void midvunit_state::midvunit_comcs_w(offs_t offset, uint32_t data)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
@ -558,7 +558,7 @@ WRITE32_MEMBER(midvunit_state::midvunit_comcs_w)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ32_MEMBER(midvunit_state::midvplus_misc_r)
|
||||
uint32_t midvunit_state::midvplus_misc_r(offs_t offset)
|
||||
{
|
||||
uint32_t result = m_midvplus_misc[offset];
|
||||
|
||||
@ -583,7 +583,7 @@ READ32_MEMBER(midvunit_state::midvplus_misc_r)
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(midvunit_state::midvplus_misc_w)
|
||||
void midvunit_state::midvplus_misc_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
uint32_t olddata = m_midvplus_misc[offset];
|
||||
bool logit = true;
|
||||
@ -1854,7 +1854,7 @@ ROM_END
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ32_MEMBER(midvunit_state::generic_speedup_r)
|
||||
uint32_t midvunit_state::generic_speedup_r(offs_t offset)
|
||||
{
|
||||
m_maincpu->eat_cycles(100);
|
||||
return m_generic_speedup[offset];
|
||||
@ -1866,7 +1866,7 @@ void midvunit_state::init_crusnusa_common(offs_t speedup)
|
||||
m_adc_shift = 24;
|
||||
|
||||
/* speedups */
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(speedup, speedup + 1, read32_delegate(*this, FUNC(midvunit_state::generic_speedup_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(speedup, speedup + 1, read32sm_delegate(*this, FUNC(midvunit_state::generic_speedup_r)));
|
||||
m_generic_speedup = m_ram_base + speedup;
|
||||
}
|
||||
void midvunit_state::init_crusnusa() { init_crusnusa_common(0xc93e); }
|
||||
@ -1879,19 +1879,19 @@ void midvunit_state::init_crusnwld_common(offs_t speedup)
|
||||
m_adc_shift = 16;
|
||||
|
||||
/* control register is different */
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x994000, 0x994000, write32_delegate(*this, FUNC(midvunit_state::crusnwld_control_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x994000, 0x994000, write32s_delegate(*this, FUNC(midvunit_state::crusnwld_control_w)));
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x991030, 0x991030, read32_delegate(*this, FUNC(midvunit_state::crusnwld_serial_status_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x996000, 0x996000, read32_delegate(*this, FUNC(midvunit_state::crusnwld_serial_data_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x996000, 0x996000, write32_delegate(*this, FUNC(midvunit_state::crusnwld_serial_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x991030, 0x991030, read32smo_delegate(*this, FUNC(midvunit_state::crusnwld_serial_status_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x996000, 0x996000, read32smo_delegate(*this, FUNC(midvunit_state::crusnwld_serial_data_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x996000, 0x996000, write32smo_delegate(*this, FUNC(midvunit_state::crusnwld_serial_data_w)));
|
||||
|
||||
/* install strange protection device */
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x9d0000, 0x9d1fff, read32_delegate(*this, FUNC(midvunit_state::bit_data_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x9d0000, 0x9d0000, write32_delegate(*this, FUNC(midvunit_state::bit_reset_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x9d0000, 0x9d1fff, read32sm_delegate(*this, FUNC(midvunit_state::bit_data_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x9d0000, 0x9d0000, write32smo_delegate(*this, FUNC(midvunit_state::bit_reset_w)));
|
||||
|
||||
/* speedups */
|
||||
if (speedup) {
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(speedup, speedup + 1, read32_delegate(*this, FUNC(midvunit_state::generic_speedup_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(speedup, speedup + 1, read32sm_delegate(*this, FUNC(midvunit_state::generic_speedup_r)));
|
||||
m_generic_speedup = m_ram_base + speedup;
|
||||
}
|
||||
}
|
||||
@ -1906,13 +1906,13 @@ void midvunit_state::init_offroadc()
|
||||
m_adc_shift = 16;
|
||||
|
||||
/* control register is different */
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x994000, 0x994000, write32_delegate(*this, FUNC(midvunit_state::crusnwld_control_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x994000, 0x994000, write32s_delegate(*this, FUNC(midvunit_state::crusnwld_control_w)));
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x991030, 0x991030, read32_delegate(*this, FUNC(midvunit_state::offroadc_serial_status_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x996000, 0x996000, read32_delegate(*this, FUNC(midvunit_state::offroadc_serial_data_r)), write32_delegate(*this, FUNC(midvunit_state::offroadc_serial_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x991030, 0x991030, read32smo_delegate(*this, FUNC(midvunit_state::offroadc_serial_status_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x996000, 0x996000, read32smo_delegate(*this, FUNC(midvunit_state::offroadc_serial_data_r)), write32smo_delegate(*this, FUNC(midvunit_state::offroadc_serial_data_w)));
|
||||
|
||||
/* speedups */
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x195aa, 0x195aa, read32_delegate(*this, FUNC(midvunit_state::generic_speedup_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x195aa, 0x195aa, read32sm_delegate(*this, FUNC(midvunit_state::generic_speedup_r)));
|
||||
m_generic_speedup = m_ram_base + 0x195aa;
|
||||
}
|
||||
|
||||
@ -1933,7 +1933,7 @@ void midvunit_state::init_wargods()
|
||||
m_midway_ioasic->set_default_nvram(default_nvram);
|
||||
|
||||
/* speedups */
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x2f4c, 0x2f4c, read32_delegate(*this, FUNC(midvunit_state::generic_speedup_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x2f4c, 0x2f4c, read32sm_delegate(*this, FUNC(midvunit_state::generic_speedup_r)));
|
||||
m_generic_speedup = m_ram_base + 0x2f4c;
|
||||
}
|
||||
|
||||
|
@ -139,7 +139,7 @@ Notes:
|
||||
*
|
||||
*************************************/
|
||||
|
||||
WRITE8_MEMBER(midyunit_state::yawdim_oki_bank_w)
|
||||
void midyunit_state::yawdim_oki_bank_w(uint8_t data)
|
||||
{
|
||||
if (data & 4)
|
||||
m_oki->set_rom_bank(data & 3);
|
||||
|
@ -155,7 +155,7 @@ WRITE_LINE_MEMBER(midzeus2_state::zeus_irq)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
WRITE32_MEMBER(midzeus_state::cmos_w)
|
||||
void midzeus_state::cmos_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
if (disk_asic_jr[2] && !cmos_protected)
|
||||
COMBINE_DATA(&m_nvram[offset]);
|
||||
@ -165,13 +165,13 @@ WRITE32_MEMBER(midzeus_state::cmos_w)
|
||||
}
|
||||
|
||||
|
||||
READ32_MEMBER(midzeus_state::cmos_r)
|
||||
uint32_t midzeus_state::cmos_r(offs_t offset)
|
||||
{
|
||||
return m_nvram[offset] | 0xffffff00;
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(midzeus_state::cmos_protect_w)
|
||||
void midzeus_state::cmos_protect_w(uint32_t data)
|
||||
{
|
||||
cmos_protected = false;
|
||||
}
|
||||
@ -200,13 +200,13 @@ void midzeus2_state::zeus2_timekeeper_w(offs_t offset, uint32_t data)
|
||||
}
|
||||
|
||||
|
||||
READ32_MEMBER(midzeus_state::zpram_r)
|
||||
uint32_t midzeus_state::zpram_r(offs_t offset)
|
||||
{
|
||||
return m_nvram[offset] | 0xffffff00;
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(midzeus_state::zpram_w)
|
||||
void midzeus_state::zpram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
if (disk_asic_jr[2])
|
||||
COMBINE_DATA(&m_nvram[offset]);
|
||||
@ -221,7 +221,7 @@ WRITE32_MEMBER(midzeus_state::zpram_w)
|
||||
* Disk ASIC registers
|
||||
*
|
||||
*************************************/
|
||||
READ32_MEMBER(midzeus_state::disk_asic_r)
|
||||
uint32_t midzeus_state::disk_asic_r(offs_t offset)
|
||||
{
|
||||
uint32_t retVal = disk_asic[offset];
|
||||
switch (offset)
|
||||
@ -260,7 +260,7 @@ READ32_MEMBER(midzeus_state::disk_asic_r)
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(midzeus_state::disk_asic_w)
|
||||
void midzeus_state::disk_asic_w(offs_t offset, uint32_t data)
|
||||
{
|
||||
disk_asic[offset] = data;
|
||||
|
||||
@ -300,7 +300,7 @@ WRITE32_MEMBER(midzeus_state::disk_asic_w)
|
||||
* Disk ASIC JR registers
|
||||
*
|
||||
*************************************/
|
||||
READ32_MEMBER(midzeus_state::disk_asic_jr_r)
|
||||
uint32_t midzeus_state::disk_asic_jr_r(offs_t offset)
|
||||
{
|
||||
uint32_t retVal = disk_asic_jr[offset];
|
||||
switch (offset)
|
||||
@ -341,7 +341,7 @@ READ32_MEMBER(midzeus_state::disk_asic_jr_r)
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(midzeus_state::disk_asic_jr_w)
|
||||
void midzeus_state::disk_asic_jr_w(offs_t offset, uint32_t data)
|
||||
{
|
||||
//uint32_t oldval = disk_asic_jr[offset];
|
||||
disk_asic_jr[offset] = data;
|
||||
@ -462,7 +462,7 @@ void midzeus2_state::crusnexo_leds_w(offs_t offset, uint32_t data)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ32_MEMBER(midzeus_state::firewire_r)
|
||||
uint32_t midzeus_state::firewire_r(offs_t offset)
|
||||
{
|
||||
uint32_t retVal = 0;
|
||||
if (offset < 0x40)
|
||||
@ -498,7 +498,7 @@ READ32_MEMBER(midzeus_state::firewire_r)
|
||||
return retVal;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(midzeus_state::firewire_w)
|
||||
void midzeus_state::firewire_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
// 0x08 // Control
|
||||
// Bit 0: Flush bad packets from Rx FIFO
|
||||
@ -538,7 +538,7 @@ WRITE32_MEMBER(midzeus_state::firewire_w)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ32_MEMBER(midzeus_state::tms32031_control_r)
|
||||
uint32_t midzeus_state::tms32031_control_r(offs_t offset)
|
||||
{
|
||||
/* watch for accesses to the timers */
|
||||
if (offset == 0x24 || offset == 0x34)
|
||||
@ -557,7 +557,7 @@ READ32_MEMBER(midzeus_state::tms32031_control_r)
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(midzeus_state::tms32031_control_w)
|
||||
void midzeus_state::tms32031_control_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_tms32031_control[offset]);
|
||||
|
||||
@ -591,7 +591,7 @@ CUSTOM_INPUT_MEMBER(midzeus_state::custom_49way_r)
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(midzeus_state::keypad_select_w)
|
||||
void midzeus_state::keypad_select_w(offs_t offset, uint32_t data)
|
||||
{
|
||||
if (offset == 1)
|
||||
keypad_select = data;
|
||||
@ -610,13 +610,13 @@ CUSTOM_INPUT_MEMBER(midzeus_state::keypad_r)
|
||||
return bits;
|
||||
}
|
||||
|
||||
READ32_MEMBER(midzeus_state::grid_keypad_r)
|
||||
uint32_t midzeus_state::grid_keypad_r(offs_t offset)
|
||||
{
|
||||
uint32_t bits = (m_io_keypad->read() >> ((offset >> 1) << 2)) & 0xf;
|
||||
return bits;
|
||||
}
|
||||
|
||||
READ32_MEMBER(midzeus_state::trackball_r)
|
||||
uint32_t midzeus_state::trackball_r(offs_t offset)
|
||||
{
|
||||
if (offset==0)
|
||||
return m_io_tracky->read();
|
||||
@ -632,7 +632,7 @@ READ32_MEMBER(midzeus_state::trackball_r)
|
||||
*
|
||||
*************************************/
|
||||
|
||||
READ32_MEMBER(midzeus_state::analog_r)
|
||||
uint32_t midzeus_state::analog_r(offs_t offset)
|
||||
{
|
||||
if (offset < 8 || offset > 11)
|
||||
logerror("%06X:analog_r(%X)\n", m_maincpu->pc(), offset);
|
||||
@ -640,7 +640,7 @@ READ32_MEMBER(midzeus_state::analog_r)
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(midzeus_state::analog_w)
|
||||
void midzeus_state::analog_w(uint32_t data)
|
||||
{
|
||||
/* 16 writes to the location before a read */
|
||||
}
|
||||
@ -679,7 +679,7 @@ TIMER_CALLBACK_MEMBER(midzeus_state::invasn_gun_callback)
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(midzeus_state::invasn_gun_w)
|
||||
void midzeus_state::invasn_gun_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
uint32_t old_control = gun_control;
|
||||
int player;
|
||||
@ -705,7 +705,7 @@ WRITE32_MEMBER(midzeus_state::invasn_gun_w)
|
||||
}
|
||||
|
||||
|
||||
READ32_MEMBER(midzeus_state::invasn_gun_r)
|
||||
uint32_t midzeus_state::invasn_gun_r()
|
||||
{
|
||||
int beamx = m_screen->hpos();
|
||||
int beamy = m_screen->vpos();
|
||||
@ -1678,7 +1678,8 @@ void midzeus_state::init_mk4()
|
||||
|
||||
void midzeus_state::init_invasn()
|
||||
{
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x9c0000, 0x9c0000, read32_delegate(*this, FUNC(midzeus_state::invasn_gun_r)), write32_delegate(*this, FUNC(midzeus_state::invasn_gun_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x9c0000, 0x9c0000, read32smo_delegate(*this, FUNC(midzeus_state::invasn_gun_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0x9c0000, 0x9c0000, write32s_delegate(*this, FUNC(midzeus_state::invasn_gun_w)));
|
||||
}
|
||||
|
||||
|
||||
@ -1686,15 +1687,15 @@ void midzeus2_state::init_crusnexo()
|
||||
{
|
||||
membank("bank1")->configure_entries(0, 3, memregion("user2")->base(), 0x400000*4);
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x9b0004, 0x9b0007, read32sm_delegate(*this, FUNC(midzeus2_state::crusnexo_leds_r)), write32sm_delegate(*this, FUNC(midzeus2_state::crusnexo_leds_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler (0x8d0009, 0x8d000a, write32_delegate(*this, FUNC(midzeus_state::keypad_select_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler (0x8d0009, 0x8d000a, write32sm_delegate(*this, FUNC(midzeus_state::keypad_select_w)));
|
||||
}
|
||||
|
||||
|
||||
void midzeus2_state::init_thegrid()
|
||||
{
|
||||
membank("bank1")->configure_entries(0, 3, memregion("user2")->base(), 0x400000*4);
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x8c0000, 0x8c0001, read32_delegate(*this, FUNC(midzeus_state::trackball_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x9b0000, 0x9b0004, read32_delegate(*this, FUNC(midzeus_state::grid_keypad_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x8c0000, 0x8c0001, read32sm_delegate(*this, FUNC(midzeus_state::trackball_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x9b0000, 0x9b0004, read32sm_delegate(*this, FUNC(midzeus_state::grid_keypad_r)));
|
||||
}
|
||||
|
||||
|
||||
|
@ -765,12 +765,12 @@ void model1_state::r360_w(uint8_t data)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(model1_state::fifoin_status_r)
|
||||
u16 model1_state::fifoin_status_r()
|
||||
{
|
||||
return 0xffff;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(model1_state::bank_w)
|
||||
void model1_state::bank_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
|
||||
if(ACCESSING_BITS_0_7) {
|
||||
|
@ -109,7 +109,7 @@
|
||||
#include "segabill.lh"
|
||||
|
||||
/* Timers - these count down at 25 MHz and pull IRQ2 when they hit 0 */
|
||||
READ32_MEMBER(model2_state::timers_r)
|
||||
u32 model2_state::timers_r(offs_t offset)
|
||||
{
|
||||
m_maincpu->i960_noburst();
|
||||
|
||||
@ -117,7 +117,7 @@ READ32_MEMBER(model2_state::timers_r)
|
||||
if (m_timerrun[offset])
|
||||
{
|
||||
// get elapsed time, convert to units of 25 MHz
|
||||
uint32_t cur = (m_timers[offset]->time_elapsed() * 25000000).as_double();
|
||||
u32 cur = (m_timers[offset]->time_elapsed() * 25000000).as_double();
|
||||
|
||||
// subtract units from starting value
|
||||
m_timervals[offset] = m_timerorig[offset] - cur;
|
||||
@ -126,7 +126,7 @@ READ32_MEMBER(model2_state::timers_r)
|
||||
return m_timervals[offset];
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_state::timers_w)
|
||||
void model2_state::timers_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
attotime period;
|
||||
|
||||
@ -328,37 +328,37 @@ void model2c_state::machine_reset()
|
||||
m_copro_tgpx4->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(model2_state::palette_w)
|
||||
void model2_state::palette_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_palram[offset]);
|
||||
u16 color = m_palram[offset];
|
||||
m_palette->set_pen_color(offset, pal5bit(color >> 0), pal5bit(color >> 5), pal5bit(color >> 10));
|
||||
}
|
||||
|
||||
READ16_MEMBER(model2_state::palette_r)
|
||||
u16 model2_state::palette_r(offs_t offset)
|
||||
{
|
||||
return m_palram[offset];
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(model2_state::colorxlat_w)
|
||||
void model2_state::colorxlat_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_colorxlat[offset]);
|
||||
}
|
||||
|
||||
READ16_MEMBER(model2_state::colorxlat_r)
|
||||
u16 model2_state::colorxlat_r(offs_t offset)
|
||||
{
|
||||
return m_colorxlat[offset];
|
||||
}
|
||||
|
||||
// Apparently original Model 2 doesn't have fifo control?
|
||||
READ32_MEMBER(model2o_state::fifo_control_2o_r)
|
||||
u32 model2o_state::fifo_control_2o_r()
|
||||
{
|
||||
return 0xffffffff;
|
||||
}
|
||||
|
||||
READ32_MEMBER(model2_state::fifo_control_2a_r)
|
||||
u32 model2_state::fifo_control_2a_r()
|
||||
{
|
||||
uint32_t r = 0;
|
||||
u32 r = 0;
|
||||
|
||||
if (m_copro_fifo_out->is_empty())
|
||||
{
|
||||
@ -371,9 +371,9 @@ READ32_MEMBER(model2_state::fifo_control_2a_r)
|
||||
// return r | 0x04;
|
||||
}
|
||||
|
||||
READ32_MEMBER(model2_state::videoctl_r)
|
||||
u32 model2_state::videoctl_r()
|
||||
{
|
||||
uint8_t framenum;
|
||||
u8 framenum;
|
||||
|
||||
if(m_render_mode == false)
|
||||
framenum = (m_screen->frame_number() & 2) << 1;
|
||||
@ -383,23 +383,23 @@ READ32_MEMBER(model2_state::videoctl_r)
|
||||
return (framenum) | (m_videocontrol & 3);
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_state::videoctl_w)
|
||||
void model2_state::videoctl_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_videocontrol);
|
||||
}
|
||||
|
||||
// Coprocessor - Common
|
||||
READ32_MEMBER(model2_state::copro_prg_r)
|
||||
u32 model2_state::copro_prg_r()
|
||||
{
|
||||
return 0xffffffff;
|
||||
}
|
||||
|
||||
READ32_MEMBER(model2_state::copro_ctl1_r)
|
||||
u32 model2_state::copro_ctl1_r()
|
||||
{
|
||||
return m_coproctl;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_state::copro_ctl1_w)
|
||||
void model2_state::copro_ctl1_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
// did hi bit change?
|
||||
if ((data ^ m_coproctl) == 0x80000000)
|
||||
@ -457,7 +457,7 @@ void model2_tgp_state::copro_tgp_rf_map(address_map &map)
|
||||
map(0x3, 0x3).w(FUNC(model2_tgp_state::copro_tgp_bank_w));
|
||||
}
|
||||
|
||||
READ32_MEMBER(model2_tgp_state::copro_tgp_memory_r)
|
||||
u32 model2_tgp_state::copro_tgp_memory_r(offs_t offset)
|
||||
{
|
||||
offs_t adr = (m_copro_tgp_bank_reg & 0xff0000) | offset;
|
||||
|
||||
@ -474,7 +474,7 @@ READ32_MEMBER(model2_tgp_state::copro_tgp_memory_r)
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_tgp_state::copro_tgp_memory_w)
|
||||
void model2_tgp_state::copro_tgp_memory_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
offs_t adr = (m_copro_tgp_bank_reg & 0xff0000) | offset;
|
||||
if(adr & 0x400000) {
|
||||
@ -483,18 +483,18 @@ WRITE32_MEMBER(model2_tgp_state::copro_tgp_memory_w)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_tgp_state::copro_tgp_bank_w)
|
||||
void model2_tgp_state::copro_tgp_bank_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_copro_tgp_bank_reg);
|
||||
m_copro_tgp_bank->set_bank(m_copro_tgp_bank_reg & 0xc00000 ? 1 : 0);
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_tgp_state::copro_sincos_w)
|
||||
void model2_tgp_state::copro_sincos_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_copro_sincos_base);
|
||||
}
|
||||
|
||||
READ32_MEMBER(model2_tgp_state::copro_sincos_r)
|
||||
u32 model2_tgp_state::copro_sincos_r(offs_t offset)
|
||||
{
|
||||
offs_t ang = m_copro_sincos_base + offset * 0x4000;
|
||||
offs_t index = ang & 0x3fff;
|
||||
@ -506,12 +506,12 @@ READ32_MEMBER(model2_tgp_state::copro_sincos_r)
|
||||
return result;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_tgp_state::copro_inv_w)
|
||||
void model2_tgp_state::copro_inv_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_copro_inv_base);
|
||||
}
|
||||
|
||||
READ32_MEMBER(model2_tgp_state::copro_inv_r)
|
||||
u32 model2_tgp_state::copro_inv_r(offs_t offset)
|
||||
{
|
||||
offs_t index = ((m_copro_inv_base >> 9) & 0x3ffe) | (offset & 1);
|
||||
u32 result = m_copro_tgp_tables[index | 0x8000];
|
||||
@ -523,12 +523,12 @@ READ32_MEMBER(model2_tgp_state::copro_inv_r)
|
||||
return result;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_tgp_state::copro_isqrt_w)
|
||||
void model2_tgp_state::copro_isqrt_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_copro_isqrt_base);
|
||||
}
|
||||
|
||||
READ32_MEMBER(model2_tgp_state::copro_isqrt_r)
|
||||
u32 model2_tgp_state::copro_isqrt_r(offs_t offset)
|
||||
{
|
||||
offs_t index = 0x2000 ^ (((m_copro_isqrt_base>> 10) & 0x3ffe) | (offset & 1));
|
||||
u32 result = m_copro_tgp_tables[index | 0xc000];
|
||||
@ -540,13 +540,13 @@ READ32_MEMBER(model2_tgp_state::copro_isqrt_r)
|
||||
return result;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_tgp_state::copro_atan_w)
|
||||
void model2_tgp_state::copro_atan_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_copro_atan_base[offset]);
|
||||
m_copro_tgp->gpio0_w((m_copro_atan_base[0] & 0x7fffffff) <= (m_copro_atan_base[1] & 0x7fffffff));
|
||||
}
|
||||
|
||||
READ32_MEMBER(model2_tgp_state::copro_atan_r)
|
||||
u32 model2_tgp_state::copro_atan_r()
|
||||
{
|
||||
u8 ie = 0x88 - (m_copro_atan_base[3] >> 23);
|
||||
|
||||
@ -571,10 +571,10 @@ READ32_MEMBER(model2_tgp_state::copro_atan_r)
|
||||
return result & 0xffff;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_tgp_state::copro_function_port_w)
|
||||
void model2_tgp_state::copro_function_port_w(offs_t offset, u32 data)
|
||||
{
|
||||
uint32_t d = data & 0x800fffff;
|
||||
uint32_t a = (offset >> 2) & 0xff;
|
||||
u32 d = data & 0x800fffff;
|
||||
u32 a = (offset >> 2) & 0xff;
|
||||
d |= a << 23;
|
||||
|
||||
m_copro_fifo_in->push(u32(d));
|
||||
@ -591,13 +591,13 @@ void model2_tgp_state::copro_boot()
|
||||
m_copro_tgp->pulse_input_line(INPUT_LINE_RESET, attotime::zero);
|
||||
}
|
||||
|
||||
READ32_MEMBER(model2_tgp_state::copro_fifo_r)
|
||||
u32 model2_tgp_state::copro_fifo_r()
|
||||
{
|
||||
m_maincpu->i960_noburst();
|
||||
return m_copro_fifo_out->pop();
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_tgp_state::copro_fifo_w)
|
||||
void model2_tgp_state::copro_fifo_w(u32 data)
|
||||
{
|
||||
m_maincpu->i960_noburst();
|
||||
if (m_coproctl & 0x80000000)
|
||||
@ -613,12 +613,12 @@ WRITE32_MEMBER(model2_tgp_state::copro_fifo_w)
|
||||
|
||||
// Coprocessor - SHARC
|
||||
|
||||
READ32_MEMBER(model2b_state::copro_sharc_buffer_r)
|
||||
u32 model2b_state::copro_sharc_buffer_r(offs_t offset)
|
||||
{
|
||||
return m_bufferram[offset & 0x7fff];
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2b_state::copro_sharc_buffer_w)
|
||||
void model2b_state::copro_sharc_buffer_w(offs_t offset, u32 data)
|
||||
{
|
||||
m_bufferram[offset & 0x7fff] = data;
|
||||
}
|
||||
@ -640,13 +640,13 @@ void model2b_state::copro_boot()
|
||||
m_copro_adsp->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
|
||||
}
|
||||
|
||||
READ32_MEMBER(model2b_state::copro_fifo_r)
|
||||
u32 model2b_state::copro_fifo_r()
|
||||
{
|
||||
m_maincpu->i960_noburst();
|
||||
return m_copro_fifo_out->pop();
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2b_state::copro_fifo_w)
|
||||
void model2b_state::copro_fifo_w(u32 data)
|
||||
{
|
||||
m_maincpu->i960_noburst();
|
||||
if (m_coproctl & 0x80000000)
|
||||
@ -660,7 +660,7 @@ WRITE32_MEMBER(model2b_state::copro_fifo_w)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2b_state::copro_sharc_iop_w)
|
||||
void model2b_state::copro_sharc_iop_w(offs_t offset, u32 data)
|
||||
{
|
||||
/* FIXME: clean this mess */
|
||||
if ((strcmp(machine().system().name, "schamp" ) == 0) ||
|
||||
@ -698,10 +698,10 @@ WRITE32_MEMBER(model2b_state::copro_sharc_iop_w)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2b_state::copro_function_port_w)
|
||||
void model2b_state::copro_function_port_w(offs_t offset, u32 data)
|
||||
{
|
||||
uint32_t d = data & 0x800fffff;
|
||||
uint32_t a = (offset >> 2) & 0xff;
|
||||
u32 d = data & 0x800fffff;
|
||||
u32 a = (offset >> 2) & 0xff;
|
||||
d |= a << 23;
|
||||
|
||||
m_copro_fifo_in->push(u32(d));
|
||||
@ -719,13 +719,13 @@ void model2c_state::copro_boot()
|
||||
m_copro_tgpx4->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
|
||||
}
|
||||
|
||||
READ32_MEMBER(model2c_state::copro_fifo_r)
|
||||
u32 model2c_state::copro_fifo_r()
|
||||
{
|
||||
m_maincpu->i960_noburst();
|
||||
return m_copro_fifo_out->pop();
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2c_state::copro_fifo_w)
|
||||
void model2c_state::copro_fifo_w(u32 data)
|
||||
{
|
||||
m_maincpu->i960_noburst();
|
||||
if (m_coproctl & 0x80000000)
|
||||
@ -749,10 +749,10 @@ WRITE32_MEMBER(model2c_state::copro_fifo_w)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2c_state::copro_function_port_w)
|
||||
void model2c_state::copro_function_port_w(offs_t offset, u32 data)
|
||||
{
|
||||
uint32_t d = data & 0x800fffff;
|
||||
uint32_t a = (offset >> 2) & 0xff;
|
||||
u32 d = data & 0x800fffff;
|
||||
u32 a = (offset >> 2) & 0xff;
|
||||
d |= a << 23;
|
||||
|
||||
m_copro_fifo_in->push(u32(d));
|
||||
@ -775,7 +775,7 @@ void model2c_state::copro_tgpx4_data_map(address_map &map)
|
||||
/* GEO */
|
||||
|
||||
|
||||
WRITE32_MEMBER(model2_state::geo_ctl1_w)
|
||||
void model2_state::geo_ctl1_w(u32 data)
|
||||
{
|
||||
// did hi bit change?
|
||||
if ((data ^ m_geoctl) == 0x80000000)
|
||||
@ -794,20 +794,20 @@ WRITE32_MEMBER(model2_state::geo_ctl1_w)
|
||||
m_geoctl = data;
|
||||
}
|
||||
|
||||
void model2_state::push_geo_data(uint32_t data)
|
||||
void model2_state::push_geo_data(u32 data)
|
||||
{
|
||||
//osd_printf_debug("push_geo_data: %08X: %08X\n", 0x900000+m_geo_write_start_address, data);
|
||||
m_bufferram[m_geo_write_start_address/4] = data;
|
||||
m_geo_write_start_address += 4;
|
||||
}
|
||||
|
||||
READ32_MEMBER(model2_state::geo_prg_r)
|
||||
u32 model2_state::geo_prg_r(offs_t offset)
|
||||
{
|
||||
popmessage("Read from Geometry FIFO at %08x, contact MAMEdev",offset*4);
|
||||
return 0xffffffff;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_state::geo_prg_w)
|
||||
void model2_state::geo_prg_w(u32 data)
|
||||
{
|
||||
if (m_geoctl & 0x80000000)
|
||||
{
|
||||
@ -821,7 +821,7 @@ WRITE32_MEMBER(model2_state::geo_prg_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ32_MEMBER(model2_state::geo_r)
|
||||
u32 model2_state::geo_r(offs_t offset)
|
||||
{
|
||||
int address = offset * 4;
|
||||
if (address == 0x2008)
|
||||
@ -839,7 +839,7 @@ READ32_MEMBER(model2_state::geo_r)
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_state::geo_w)
|
||||
void model2_state::geo_w(offs_t offset, u32 data)
|
||||
{
|
||||
int address = offset * 4;
|
||||
|
||||
@ -848,7 +848,7 @@ WRITE32_MEMBER(model2_state::geo_w)
|
||||
/*if (data & 0x80000000)
|
||||
{
|
||||
int i;
|
||||
uint32_t a;
|
||||
u32 a;
|
||||
osd_printf_debug("GEO: jump to %08X\n", (data & 0xfffff));
|
||||
a = (data & 0xfffff) / 4;
|
||||
for (i=0; i < 4; i++)
|
||||
@ -875,7 +875,7 @@ WRITE32_MEMBER(model2_state::geo_w)
|
||||
|
||||
if (data & 0x80000000)
|
||||
{
|
||||
uint32_t r = 0;
|
||||
u32 r = 0;
|
||||
r |= data & 0x800fffff;
|
||||
r |= ((address >> 4) & 0x3f) << 23;
|
||||
push_geo_data(r);
|
||||
@ -884,12 +884,12 @@ WRITE32_MEMBER(model2_state::geo_w)
|
||||
{
|
||||
if ((address & 0xf) == 0)
|
||||
{
|
||||
uint32_t r = 0;
|
||||
u32 r = 0;
|
||||
r |= data & 0x000fffff;
|
||||
r |= ((address >> 4) & 0x3f) << 23;
|
||||
if((address >> 4) & 0xc0)
|
||||
{
|
||||
uint8_t function = (address >> 4) & 0x3f;
|
||||
u8 function = (address >> 4) & 0x3f;
|
||||
if(function == 1)
|
||||
{
|
||||
r |= ((address>>10)&3)<<29; // Eye Mode, used by Sega Rally on car select
|
||||
@ -918,21 +918,21 @@ WRITE32_MEMBER(model2_state::geo_w)
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
READ32_MEMBER(model2_state::irq_request_r)
|
||||
u32 model2_state::irq_request_r()
|
||||
{
|
||||
m_maincpu->i960_noburst();
|
||||
|
||||
return m_intreq;
|
||||
}
|
||||
|
||||
READ32_MEMBER(model2_state::irq_enable_r)
|
||||
u32 model2_state::irq_enable_r()
|
||||
{
|
||||
m_maincpu->i960_noburst();
|
||||
|
||||
return m_intena;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_state::irq_ack_w)
|
||||
void model2_state::irq_ack_w(u32 data)
|
||||
{
|
||||
m_maincpu->i960_noburst();
|
||||
|
||||
@ -941,7 +941,7 @@ WRITE32_MEMBER(model2_state::irq_ack_w)
|
||||
model2_check_irqack_state(data ^ 0xffffffff);
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_state::irq_enable_w)
|
||||
void model2_state::irq_enable_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
m_maincpu->i960_noburst();
|
||||
|
||||
@ -966,7 +966,7 @@ void model2_state::model2_check_irq_state()
|
||||
}
|
||||
}
|
||||
|
||||
void model2_state::model2_check_irqack_state(uint32_t data)
|
||||
void model2_state::model2_check_irqack_state(u32 data)
|
||||
{
|
||||
const int irq_type[12]= {I960_IRQ0,I960_IRQ1,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ2,I960_IRQ3,I960_IRQ3};
|
||||
|
||||
@ -978,7 +978,7 @@ void model2_state::model2_check_irqack_state(uint32_t data)
|
||||
}
|
||||
|
||||
/* TODO: rewrite this part. It's a 8251-compatible chip */
|
||||
READ32_MEMBER(model2_state::model2_serial_r)
|
||||
u32 model2_state::model2_serial_r(offs_t offset, u32 mem_mask)
|
||||
{
|
||||
if (offset == 0)
|
||||
{
|
||||
@ -994,7 +994,7 @@ READ32_MEMBER(model2_state::model2_serial_r)
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(model2_state::model2_serial_w)
|
||||
void model2_state::model2_serial_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_0_7 && (offset == 0))
|
||||
{
|
||||
@ -1017,7 +1017,7 @@ WRITE32_MEMBER(model2_state::model2_serial_w)
|
||||
|
||||
|
||||
#ifdef UNUSED_FUNCTION
|
||||
WRITE32_MEMBER(model2_state::copro_w)
|
||||
void model2_state::copro_w(offs_t offset, u32 data)
|
||||
{
|
||||
int address = offset * 4;
|
||||
|
||||
@ -1036,12 +1036,12 @@ WRITE32_MEMBER(model2_state::copro_w)
|
||||
}
|
||||
#endif
|
||||
|
||||
READ32_MEMBER(model2_state::render_mode_r)
|
||||
u32 model2_state::render_mode_r()
|
||||
{
|
||||
return (m_render_unk << 14) | (m_render_mode << 2) | (m_render_test_mode << 0);
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_state::render_mode_w)
|
||||
void model2_state::render_mode_w(u32 data)
|
||||
{
|
||||
// ---- -x-- (1) 60 Hz mode
|
||||
// (0) 30 Hz mode - skytargt, desert, vstriker, vcop
|
||||
@ -1056,7 +1056,7 @@ WRITE32_MEMBER(model2_state::render_mode_w)
|
||||
// osd_printf_debug("Mode = %08X\n", data);
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_tgp_state::tex0_w)
|
||||
void model2_tgp_state::tex0_w(offs_t offset, u32 data)
|
||||
{
|
||||
if ( (offset & 1) == 0 )
|
||||
{
|
||||
@ -1070,7 +1070,7 @@ WRITE32_MEMBER(model2_tgp_state::tex0_w)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(model2_tgp_state::tex1_w)
|
||||
void model2_tgp_state::tex1_w(offs_t offset, u32 data)
|
||||
{
|
||||
if ( (offset & 1) == 0 )
|
||||
{
|
||||
@ -1084,12 +1084,12 @@ WRITE32_MEMBER(model2_tgp_state::tex1_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(model2_state::lumaram_r)
|
||||
u16 model2_state::lumaram_r(offs_t offset)
|
||||
{
|
||||
return m_lumaram[offset];
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(model2_state::lumaram_w)
|
||||
void model2_state::lumaram_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_lumaram[offset]);
|
||||
}
|
||||
@ -1102,10 +1102,10 @@ READ8_MEMBER(model2_state::tgpid_r)
|
||||
return ID[offset];
|
||||
}
|
||||
|
||||
READ16_MEMBER(model2_state::fbvram_bankA_r) { return m_fbvramA[offset]; }
|
||||
READ16_MEMBER(model2_state::fbvram_bankB_r) { return m_fbvramB[offset]; }
|
||||
WRITE16_MEMBER(model2_state::fbvram_bankA_w) { COMBINE_DATA(&m_fbvramA[offset]); }
|
||||
WRITE16_MEMBER(model2_state::fbvram_bankB_w) { COMBINE_DATA(&m_fbvramB[offset]); }
|
||||
u16 model2_state::fbvram_bankA_r(offs_t offset) { return m_fbvramA[offset]; }
|
||||
u16 model2_state::fbvram_bankB_r(offs_t offset) { return m_fbvramB[offset]; }
|
||||
void model2_state::fbvram_bankA_w(offs_t offset, u16 data, u16 mem_mask) { COMBINE_DATA(&m_fbvramA[offset]); }
|
||||
void model2_state::fbvram_bankB_w(offs_t offset, u16 data, u16 mem_mask) { COMBINE_DATA(&m_fbvramB[offset]); }
|
||||
|
||||
/* common map for all Model 2 versions */
|
||||
void model2_state::model2_base_mem(address_map &map)
|
||||
@ -1182,13 +1182,13 @@ void model2_state::model2_5881_mem(address_map &map)
|
||||
// Interface board ID: 837-12079
|
||||
// ALTERA FLEX + Sega 315-5338A
|
||||
|
||||
uint8_t model2_state::lightgun_data_r(offs_t offset)
|
||||
u8 model2_state::lightgun_data_r(offs_t offset)
|
||||
{
|
||||
uint16_t data = m_lightgun_ports[offset >> 1].read_safe(0);
|
||||
u16 data = m_lightgun_ports[offset >> 1].read_safe(0);
|
||||
return BIT(offset, 0) ? (data >> 8) : data;
|
||||
}
|
||||
|
||||
uint8_t model2_state::lightgun_mux_r()
|
||||
u8 model2_state::lightgun_mux_r()
|
||||
{
|
||||
if (m_lightgun_mux < 8)
|
||||
return lightgun_data_r(m_lightgun_mux);
|
||||
@ -1196,13 +1196,13 @@ uint8_t model2_state::lightgun_mux_r()
|
||||
return lightgun_offscreen_r(0);
|
||||
}
|
||||
|
||||
void model2_state::lightgun_mux_w(uint8_t data)
|
||||
void model2_state::lightgun_mux_w(u8 data)
|
||||
{
|
||||
m_lightgun_mux = data;
|
||||
}
|
||||
|
||||
// handles offscreen gun trigger detection here
|
||||
uint8_t model2_state::lightgun_offscreen_r(offs_t offset)
|
||||
u8 model2_state::lightgun_offscreen_r(offs_t offset)
|
||||
{
|
||||
// 5 percent border size
|
||||
const float BORDER_SIZE = 0.05f;
|
||||
@ -1213,12 +1213,12 @@ uint8_t model2_state::lightgun_offscreen_r(offs_t offset)
|
||||
const int BORDER_P2X = (m_lightgun_ports[3]->field(0x3ff)->maxval() - m_lightgun_ports[3]->field(0x3ff)->minval()) * BORDER_SIZE;
|
||||
const int BORDER_P2Y = (m_lightgun_ports[2]->field(0x3ff)->maxval() - m_lightgun_ports[2]->field(0x3ff)->minval()) * BORDER_SIZE;
|
||||
|
||||
uint16_t data = 0xfffc;
|
||||
u16 data = 0xfffc;
|
||||
|
||||
const uint16_t P1X = m_lightgun_ports[1].read_safe(0);
|
||||
const uint16_t P1Y = m_lightgun_ports[0].read_safe(0);
|
||||
const uint16_t P2X = m_lightgun_ports[3].read_safe(0);
|
||||
const uint16_t P2Y = m_lightgun_ports[2].read_safe(0);
|
||||
const u16 P1X = m_lightgun_ports[1].read_safe(0);
|
||||
const u16 P1Y = m_lightgun_ports[0].read_safe(0);
|
||||
const u16 P2X = m_lightgun_ports[3].read_safe(0);
|
||||
const u16 P2Y = m_lightgun_ports[2].read_safe(0);
|
||||
|
||||
// border hit test for player 1 and 2
|
||||
if (P1X <= (m_lightgun_ports[1]->field(0x3ff)->minval() + BORDER_P1X)) data |= 1;
|
||||
@ -1238,7 +1238,7 @@ uint8_t model2_state::lightgun_offscreen_r(offs_t offset)
|
||||
// OUTPUTS
|
||||
//**************************************************************************
|
||||
|
||||
void model2o_state::daytona_output_w(uint8_t data)
|
||||
void model2o_state::daytona_output_w(u8 data)
|
||||
{
|
||||
// 7------- leader led
|
||||
// -6------ vr4 led
|
||||
@ -1253,7 +1253,7 @@ void model2o_state::daytona_output_w(uint8_t data)
|
||||
machine().bookkeeping().coin_counter_w(0, BIT(data, 0));
|
||||
}
|
||||
|
||||
void model2o_state::desert_output_w(uint8_t data)
|
||||
void model2o_state::desert_output_w(u8 data)
|
||||
{
|
||||
// 7------- cannon motor
|
||||
// -6------ machine gun motor
|
||||
@ -1268,7 +1268,7 @@ void model2o_state::desert_output_w(uint8_t data)
|
||||
machine().bookkeeping().coin_counter_w(0, BIT(data, 0));
|
||||
}
|
||||
|
||||
void model2o_state::vcop_output_w(uint8_t data)
|
||||
void model2o_state::vcop_output_w(u8 data)
|
||||
{
|
||||
// 7654---- unknown (not used?)
|
||||
// ----32-- start leds (always set together)
|
||||
@ -1318,9 +1318,9 @@ void model2o_state::model2o_mem(address_map &map)
|
||||
}
|
||||
|
||||
/* Daytona "To The MAXX" PIC protection simulation */
|
||||
READ32_MEMBER(model2o_maxx_state::maxx_r)
|
||||
u32 model2o_maxx_state::maxx_r(offs_t offset, u32 mem_mask)
|
||||
{
|
||||
uint32_t *ROM = (uint32_t *)memregion("maincpu")->base();
|
||||
u32 *ROM = (u32 *)memregion("maincpu")->base();
|
||||
|
||||
if (offset <= 0x1f/4)
|
||||
{
|
||||
@ -1367,7 +1367,7 @@ void model2o_maxx_state::model2o_maxx_mem(address_map &map)
|
||||
|
||||
READ8_MEMBER(model2o_gtx_state::gtx_r)
|
||||
{
|
||||
uint8_t *ROM = memregion("prot_data")->base();
|
||||
u8 *ROM = memregion("prot_data")->base();
|
||||
|
||||
if(offset == 0xffffc) // disable protection ROM overlay (fallbacks to data rom?)
|
||||
m_gtx_state = 2;
|
||||
@ -1386,7 +1386,7 @@ void model2o_gtx_state::model2o_gtx_mem(address_map &map)
|
||||
}
|
||||
|
||||
/* TODO: read by Sonic the Fighters (bit 1), unknown purpose */
|
||||
READ32_MEMBER(model2_state::copro_status_r)
|
||||
u32 model2_state::copro_status_r()
|
||||
{
|
||||
if(m_coprocnt == 0)
|
||||
return -1;
|
||||
@ -1569,9 +1569,9 @@ void model2c_state::model2c_5881_mem(address_map &map)
|
||||
*/
|
||||
|
||||
// simulate this so that it passes the initial checks
|
||||
uint8_t model2_state::rchase2_drive_board_r()
|
||||
u8 model2_state::rchase2_drive_board_r()
|
||||
{
|
||||
uint8_t data = 0xff;
|
||||
u8 data = 0xff;
|
||||
|
||||
if(m_cmd_data == 0xe0 || m_cmd_data == 0x0e)
|
||||
data &= ~1;
|
||||
@ -1585,12 +1585,12 @@ uint8_t model2_state::rchase2_drive_board_r()
|
||||
return data;
|
||||
}
|
||||
|
||||
void model2_state::rchase2_drive_board_w(uint8_t data)
|
||||
void model2_state::rchase2_drive_board_w(u8 data)
|
||||
{
|
||||
m_cmd_data = data;
|
||||
}
|
||||
|
||||
void model2_state::drive_board_w(uint8_t data)
|
||||
void model2_state::drive_board_w(u8 data)
|
||||
{
|
||||
m_driveio_comm_data = data;
|
||||
m_drivecpu->set_input_line(0, HOLD_LINE);
|
||||
@ -1601,7 +1601,7 @@ void model2_state::drive_board_w(uint8_t data)
|
||||
// INPUT HANDLING
|
||||
//**************************************************************************
|
||||
|
||||
void model2_state::eeprom_w(uint8_t data)
|
||||
void model2_state::eeprom_w(u8 data)
|
||||
{
|
||||
m_ctrlmode = BIT(data, 0);
|
||||
|
||||
@ -1610,9 +1610,9 @@ void model2_state::eeprom_w(uint8_t data)
|
||||
m_eeprom->cs_write(BIT(data, 6) ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
|
||||
uint8_t model2_state::in0_r()
|
||||
u8 model2_state::in0_r()
|
||||
{
|
||||
uint8_t data = m_in0->read();
|
||||
u8 data = m_in0->read();
|
||||
|
||||
if (m_ctrlmode)
|
||||
return (0xc0) | (m_eeprom->do_read() << 5) | (0x10) | (data & 0x0f);
|
||||
@ -1633,9 +1633,9 @@ uint8_t model2_state::in0_r()
|
||||
// Used by Sega Rally and Daytona USA, others might be different
|
||||
CUSTOM_INPUT_MEMBER(model2_state::daytona_gearbox_r)
|
||||
{
|
||||
uint8_t res = m_gears.read_safe(0);
|
||||
u8 res = m_gears.read_safe(0);
|
||||
int i;
|
||||
const uint8_t gearvalue[5] = { 0, 2, 1, 6, 5 };
|
||||
const u8 gearvalue[5] = { 0, 2, 1, 6, 5 };
|
||||
|
||||
for(i=0;i<5;i++)
|
||||
{
|
||||
@ -2419,12 +2419,12 @@ TIMER_DEVICE_CALLBACK_MEMBER(model2c_state::model2c_interrupt)
|
||||
|
||||
/* Model 2 sound board emulation */
|
||||
|
||||
WRITE16_MEMBER(model2_state::model2snd_ctrl)
|
||||
void model2_state::model2snd_ctrl(u16 data)
|
||||
{
|
||||
// handle sample banking
|
||||
if (memregion("samples")->bytes() > 0x800000)
|
||||
{
|
||||
uint8_t *snd = memregion("samples")->base();
|
||||
u8 *snd = memregion("samples")->base();
|
||||
if (data & 0x20)
|
||||
{
|
||||
membank("bank4")->set_base(snd + 0x200000);
|
||||
@ -2454,7 +2454,7 @@ void model2_state::scsp_map(address_map &map)
|
||||
map(0x000000, 0x07ffff).ram().share("soundram");
|
||||
}
|
||||
|
||||
void model2_state::scsp_irq(offs_t offset, uint8_t data)
|
||||
void model2_state::scsp_irq(offs_t offset, u8 data)
|
||||
{
|
||||
m_audiocpu->set_input_line(offset, data);
|
||||
}
|
||||
@ -2571,17 +2571,17 @@ void model2o_state::model2o(machine_config &config)
|
||||
M2COMM(config, "m2comm", 0);
|
||||
}
|
||||
|
||||
uint8_t model2_state::driveio_portg_r()
|
||||
u8 model2_state::driveio_portg_r()
|
||||
{
|
||||
return m_driveio_comm_data;
|
||||
}
|
||||
|
||||
uint8_t model2_state::driveio_porth_r()
|
||||
u8 model2_state::driveio_porth_r()
|
||||
{
|
||||
return m_driveio_comm_data;
|
||||
}
|
||||
|
||||
void model2_state::driveio_port_w(uint8_t data)
|
||||
void model2_state::driveio_port_w(u8 data)
|
||||
{
|
||||
// TODO: hook up to the main CPU
|
||||
// popmessage("%02x",data);
|
||||
@ -2710,7 +2710,7 @@ void model2a_state::model2a(machine_config &config)
|
||||
io.in_pc_callback().set_ioport("IN1");
|
||||
io.in_pd_callback().set_ioport("IN2");
|
||||
io.in_pg_callback().set_ioport("SW");
|
||||
io.out_pe_callback().set([this] (uint8_t data) { m_billboard->write(data); });
|
||||
io.out_pe_callback().set([this] (u8 data) { m_billboard->write(data); });
|
||||
|
||||
model2_timers(config);
|
||||
model2_screen(config);
|
||||
@ -2774,9 +2774,9 @@ void model2a_state::skytargt(machine_config &config)
|
||||
io.an_port_callback<2>().set_ioport("STICKX");
|
||||
}
|
||||
|
||||
uint16_t model2_state::crypt_read_callback(uint32_t addr)
|
||||
u16 model2_state::crypt_read_callback(u32 addr)
|
||||
{
|
||||
uint16_t dat= m_maincpu->space().read_word((0x1d80000+2*addr));
|
||||
u16 dat= m_maincpu->space().read_word((0x1d80000+2*addr));
|
||||
return ((dat&0xff00)>>8)|((dat&0x00ff)<<8);
|
||||
}
|
||||
|
||||
@ -2835,7 +2835,7 @@ void model2b_state::model2b(machine_config &config)
|
||||
io.in_pc_callback().set_ioport("IN1");
|
||||
io.in_pd_callback().set_ioport("IN2");
|
||||
io.in_pg_callback().set_ioport("SW");
|
||||
io.out_pe_callback().set([this] (uint8_t data) { m_billboard->write(data); });
|
||||
io.out_pe_callback().set([this] (u8 data) { m_billboard->write(data); });
|
||||
|
||||
model2_timers(config);
|
||||
model2_screen(config);
|
||||
@ -6967,20 +6967,20 @@ ROM_END
|
||||
void model2_state::init_pltkids()
|
||||
{
|
||||
// fix bug in program: it destroys the interrupt table and never fixes it
|
||||
uint32_t *ROM = (uint32_t *)memregion("maincpu")->base();
|
||||
u32 *ROM = (u32 *)memregion("maincpu")->base();
|
||||
ROM[0x730/4] = 0x08000004;
|
||||
}
|
||||
|
||||
void model2_state::init_zerogun()
|
||||
{
|
||||
// fix bug in program: it destroys the interrupt table and never fixes it
|
||||
uint32_t *ROM = (uint32_t *)memregion("maincpu")->base();
|
||||
u32 *ROM = (u32 *)memregion("maincpu")->base();
|
||||
ROM[0x700/4] = 0x08000004;
|
||||
}
|
||||
|
||||
void model2_state::init_sgt24h()
|
||||
{
|
||||
uint32_t *ROM = (uint32_t *)memregion("maincpu")->base();
|
||||
u32 *ROM = (u32 *)memregion("maincpu")->base();
|
||||
ROM[0x56578/4] = 0x08000004;
|
||||
//ROM[0x5b3e8/4] = 0x08000004;
|
||||
}
|
||||
@ -6993,7 +6993,7 @@ void model2_state::init_powsledm ()
|
||||
ROM[0x1585D] = 0xFD; // inverted node ID
|
||||
}
|
||||
|
||||
READ32_MEMBER(model2_state::doa_prot_r)
|
||||
u32 model2_state::doa_prot_r(offs_t offset, u32 mem_mask)
|
||||
{
|
||||
// doa only reads 16-bits at a time, while STV reads 32-bits
|
||||
uint32 ret = 0;
|
||||
@ -7004,9 +7004,9 @@ READ32_MEMBER(model2_state::doa_prot_r)
|
||||
return ret;
|
||||
}
|
||||
|
||||
READ32_MEMBER(model2_state::doa_unk_r)
|
||||
u32 model2_state::doa_unk_r()
|
||||
{
|
||||
uint32_t retval = 0;
|
||||
u32 retval = 0;
|
||||
|
||||
// this actually looks a busy status flag
|
||||
m_prot_a = !m_prot_a;
|
||||
@ -7039,7 +7039,7 @@ void model2_state::model2_0229_mem(address_map &map)
|
||||
|
||||
void model2_state::init_doa()
|
||||
{
|
||||
uint32_t *ROM = (uint32_t *)memregion("maincpu")->base();
|
||||
u32 *ROM = (u32 *)memregion("maincpu")->base();
|
||||
ROM[0x630 / 4] = 0x08000004;
|
||||
ROM[0x808 / 4] = 0x08000004;
|
||||
|
||||
|
@ -899,7 +899,7 @@ void model3_state::pci_device_set_reg(uint32_t value)
|
||||
}
|
||||
}
|
||||
|
||||
READ64_MEMBER(model3_state::mpc105_addr_r)
|
||||
uint64_t model3_state::mpc105_addr_r(offs_t offset, uint64_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_32_63)
|
||||
{
|
||||
@ -908,7 +908,7 @@ READ64_MEMBER(model3_state::mpc105_addr_r)
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE64_MEMBER(model3_state::mpc105_addr_w)
|
||||
void model3_state::mpc105_addr_w(offs_t offset, uint64_t data, uint64_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_32_63)
|
||||
{
|
||||
@ -922,7 +922,7 @@ WRITE64_MEMBER(model3_state::mpc105_addr_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ64_MEMBER(model3_state::mpc105_data_r)
|
||||
uint64_t model3_state::mpc105_data_r()
|
||||
{
|
||||
if(m_pci_device == 0) {
|
||||
return ((uint64_t)(swapendian_int32(m_mpc105_regs[(m_pci_reg/2)+1])) << 32) |
|
||||
@ -931,7 +931,7 @@ READ64_MEMBER(model3_state::mpc105_data_r)
|
||||
return swapendian_int32(pci_device_get_reg());
|
||||
}
|
||||
|
||||
WRITE64_MEMBER(model3_state::mpc105_data_w)
|
||||
void model3_state::mpc105_data_w(offs_t offset, uint64_t data, uint64_t mem_mask)
|
||||
{
|
||||
if(m_pci_device == 0) {
|
||||
m_mpc105_regs[(m_pci_reg/2)+1] = swapendian_int32((uint32_t)(data >> 32));
|
||||
@ -944,13 +944,13 @@ WRITE64_MEMBER(model3_state::mpc105_data_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ64_MEMBER(model3_state::mpc105_reg_r)
|
||||
uint64_t model3_state::mpc105_reg_r(offs_t offset)
|
||||
{
|
||||
return ((uint64_t)(m_mpc105_regs[(offset*2)+0]) << 32) |
|
||||
(uint64_t)(m_mpc105_regs[(offset*2)+1]);
|
||||
}
|
||||
|
||||
WRITE64_MEMBER(model3_state::mpc105_reg_w)
|
||||
void model3_state::mpc105_reg_w(offs_t offset, uint64_t data)
|
||||
{
|
||||
m_mpc105_regs[(offset*2)+0] = (uint32_t)(data >> 32);
|
||||
m_mpc105_regs[(offset*2)+1] = (uint32_t)data;
|
||||
@ -975,7 +975,7 @@ void model3_state::mpc105_init()
|
||||
/* Motorola MPC106 PCI Bridge/Memory Controller */
|
||||
|
||||
|
||||
READ64_MEMBER(model3_state::mpc106_addr_r)
|
||||
uint64_t model3_state::mpc106_addr_r(offs_t offset, uint64_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_32_63)
|
||||
{
|
||||
@ -984,7 +984,7 @@ READ64_MEMBER(model3_state::mpc106_addr_r)
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE64_MEMBER(model3_state::mpc106_addr_w)
|
||||
void model3_state::mpc106_addr_w(offs_t offset, uint64_t data, uint64_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_32_63)
|
||||
{
|
||||
@ -1006,7 +1006,7 @@ WRITE64_MEMBER(model3_state::mpc106_addr_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ64_MEMBER(model3_state::mpc106_data_r)
|
||||
uint64_t model3_state::mpc106_data_r(offs_t offset, uint64_t mem_mask)
|
||||
{
|
||||
if(m_pci_device == 0) {
|
||||
return ((uint64_t)(swapendian_int32(m_mpc106_regs[(m_pci_reg/2)+1])) << 32) |
|
||||
@ -1022,7 +1022,7 @@ READ64_MEMBER(model3_state::mpc106_data_r)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE64_MEMBER(model3_state::mpc106_data_w)
|
||||
void model3_state::mpc106_data_w(offs_t offset, uint64_t data, uint64_t mem_mask)
|
||||
{
|
||||
if(m_pci_device == 0) {
|
||||
m_mpc106_regs[(m_pci_reg/2)+1] = swapendian_int32((uint32_t)(data >> 32));
|
||||
@ -1035,13 +1035,13 @@ WRITE64_MEMBER(model3_state::mpc106_data_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ64_MEMBER(model3_state::mpc106_reg_r)
|
||||
uint64_t model3_state::mpc106_reg_r(offs_t offset)
|
||||
{
|
||||
return ((uint64_t)(m_mpc106_regs[(offset*2)+0]) << 32) |
|
||||
(uint64_t)(m_mpc106_regs[(offset*2)+1]);
|
||||
}
|
||||
|
||||
WRITE64_MEMBER(model3_state::mpc106_reg_w)
|
||||
void model3_state::mpc106_reg_w(offs_t offset, uint64_t data)
|
||||
{
|
||||
m_mpc106_regs[(offset*2)+0] = (uint32_t)(data >> 32);
|
||||
m_mpc106_regs[(offset*2)+1] = (uint32_t)data;
|
||||
@ -1069,7 +1069,7 @@ void model3_state::mpc106_init()
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
READ64_MEMBER(model3_state::scsi_r)
|
||||
uint64_t model3_state::scsi_r(offs_t offset, uint64_t mem_mask)
|
||||
{
|
||||
int reg = offset*8;
|
||||
uint64_t r = 0;
|
||||
@ -1101,7 +1101,7 @@ READ64_MEMBER(model3_state::scsi_r)
|
||||
return r;
|
||||
}
|
||||
|
||||
WRITE64_MEMBER(model3_state::scsi_w)
|
||||
void model3_state::scsi_w(offs_t offset, uint64_t data, uint64_t mem_mask)
|
||||
{
|
||||
int reg = offset*8;
|
||||
if (ACCESSING_BITS_56_63) {
|
||||
@ -1146,7 +1146,7 @@ void model3_state::scsi_irq_callback(int state)
|
||||
/* Real3D DMA */
|
||||
|
||||
|
||||
READ64_MEMBER(model3_state::real3d_dma_r)
|
||||
uint64_t model3_state::real3d_dma_r(offs_t offset, uint64_t mem_mask)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
@ -1162,7 +1162,7 @@ READ64_MEMBER(model3_state::real3d_dma_r)
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE64_MEMBER(model3_state::real3d_dma_w)
|
||||
void model3_state::real3d_dma_w(offs_t offset, uint64_t data, uint64_t mem_mask)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
@ -1475,7 +1475,7 @@ void model3_state::lostwsga_ser2_w(uint8_t data)
|
||||
m_serial_fifo2 = data;
|
||||
}
|
||||
|
||||
READ64_MEMBER(model3_state::model3_sys_r)
|
||||
uint64_t model3_state::model3_sys_r(offs_t offset, uint64_t mem_mask)
|
||||
{
|
||||
// printf("%s model3_sys_r: mask %llx @ %x\n", machine().describe_context().c_str(), mem_mask, offset);
|
||||
|
||||
@ -1510,7 +1510,7 @@ READ64_MEMBER(model3_state::model3_sys_r)
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE64_MEMBER(model3_state::model3_sys_w)
|
||||
void model3_state::model3_sys_w(offs_t offset, uint64_t data, uint64_t mem_mask)
|
||||
{
|
||||
// printf("model3_sys_w: %llx to %x mask %llx\n", data, offset, mem_mask);
|
||||
|
||||
@ -1580,29 +1580,29 @@ WRITE64_MEMBER(model3_state::model3_sys_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ64_MEMBER(model3_state::model3_rtc_r)
|
||||
uint64_t model3_state::model3_rtc_r(offs_t offset, uint64_t mem_mask)
|
||||
{
|
||||
uint64_t r = 0;
|
||||
if(ACCESSING_BITS_56_63) {
|
||||
r |= (uint64_t)rtc72421_r(space, (offset*2)+0, (uint32_t)(mem_mask >> 32)) << 32;
|
||||
r |= (uint64_t)rtc72421_r((offset*2)+0) << 32;
|
||||
}
|
||||
if(ACCESSING_BITS_24_31) {
|
||||
r |= (uint64_t)rtc72421_r(space, (offset*2)+1, (uint32_t)(mem_mask));
|
||||
r |= (uint64_t)rtc72421_r((offset*2)+1);
|
||||
}
|
||||
return r;
|
||||
}
|
||||
|
||||
WRITE64_MEMBER(model3_state::model3_rtc_w)
|
||||
void model3_state::model3_rtc_w(offs_t offset, uint64_t data, uint64_t mem_mask)
|
||||
{
|
||||
if(ACCESSING_BITS_56_63) {
|
||||
rtc72421_w(space, (offset*2)+0, (uint32_t)(data >> 32), (uint32_t)(mem_mask >> 32));
|
||||
rtc72421_w((offset*2)+0, (uint32_t)(data >> 32));
|
||||
}
|
||||
if(ACCESSING_BITS_24_31) {
|
||||
rtc72421_w(space, (offset*2)+1, (uint32_t)(data), (uint32_t)(mem_mask));
|
||||
rtc72421_w((offset*2)+1, (uint32_t)(data));
|
||||
}
|
||||
}
|
||||
|
||||
READ64_MEMBER(model3_state::real3d_status_r)
|
||||
uint64_t model3_state::real3d_status_r(offs_t offset)
|
||||
{
|
||||
m_real3d_status ^= 0xffffffffffffffffU;
|
||||
if (offset == 0)
|
||||
@ -1682,7 +1682,7 @@ WRITE8_MEMBER(model3_state::model3_sound_w)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE64_MEMBER(model3_state::daytona2_rombank_w)
|
||||
void model3_state::daytona2_rombank_w(offs_t offset, uint64_t data, uint64_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_56_63)
|
||||
{
|
||||
@ -5840,7 +5840,7 @@ ROM_END
|
||||
|
||||
/* Model 3 sound board emulation */
|
||||
|
||||
WRITE16_MEMBER(model3_state::model3snd_ctrl)
|
||||
void model3_state::model3snd_ctrl(uint16_t data)
|
||||
{
|
||||
// handle sample banking
|
||||
if (memregion("samples")->bytes() > 0x800000)
|
||||
@ -6115,13 +6115,14 @@ void model3_state::init_model3_10()
|
||||
{
|
||||
interleave_vroms();
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xc0000000, 0xc00000ff, read64_delegate(*this, FUNC(model3_state::scsi_r)), write64_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xc0000000, 0xc00000ff, read64s_delegate(*this, FUNC(model3_state::scsi_r)), write64s_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_read_bank(0xff000000, 0xff7fffff, "bank1" );
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0800cf8, 0xf0800cff, read64_delegate(*this, FUNC(model3_state::mpc105_addr_r)), write64_delegate(*this, FUNC(model3_state::mpc105_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0c00cf8, 0xf0c00cff, read64_delegate(*this, FUNC(model3_state::mpc105_data_r)), write64_delegate(*this, FUNC(model3_state::mpc105_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf8fff000, 0xf8fff0ff, read64_delegate(*this, FUNC(model3_state::mpc105_reg_r)), write64_delegate(*this, FUNC(model3_state::mpc105_reg_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0800cf8, 0xf0800cff, read64s_delegate(*this, FUNC(model3_state::mpc105_addr_r)), write64s_delegate(*this, FUNC(model3_state::mpc105_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0xf0c00cf8, 0xf0c00cff, read64smo_delegate(*this, FUNC(model3_state::mpc105_data_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xf0c00cf8, 0xf0c00cff, write64s_delegate(*this, FUNC(model3_state::mpc105_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf8fff000, 0xf8fff0ff, read64sm_delegate(*this, FUNC(model3_state::mpc105_reg_r)), write64sm_delegate(*this, FUNC(model3_state::mpc105_reg_w)));
|
||||
}
|
||||
|
||||
void model3_state::init_model3_15()
|
||||
@ -6129,9 +6130,10 @@ void model3_state::init_model3_15()
|
||||
interleave_vroms();
|
||||
m_maincpu->space(AS_PROGRAM).install_read_bank(0xff000000, 0xff7fffff, "bank1");
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0800cf8, 0xf0800cff, read64_delegate(*this, FUNC(model3_state::mpc105_addr_r)), write64_delegate(*this, FUNC(model3_state::mpc105_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0c00cf8, 0xf0c00cff, read64_delegate(*this, FUNC(model3_state::mpc105_data_r)), write64_delegate(*this, FUNC(model3_state::mpc105_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf8fff000, 0xf8fff0ff, read64_delegate(*this, FUNC(model3_state::mpc105_reg_r)), write64_delegate(*this, FUNC(model3_state::mpc105_reg_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0800cf8, 0xf0800cff, read64s_delegate(*this, FUNC(model3_state::mpc105_addr_r)), write64s_delegate(*this, FUNC(model3_state::mpc105_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0xf0c00cf8, 0xf0c00cff, read64smo_delegate(*this, FUNC(model3_state::mpc105_data_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xf0c00cf8, 0xf0c00cff, write64s_delegate(*this, FUNC(model3_state::mpc105_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf8fff000, 0xf8fff0ff, read64sm_delegate(*this, FUNC(model3_state::mpc105_reg_r)), write64sm_delegate(*this, FUNC(model3_state::mpc105_reg_w)));
|
||||
}
|
||||
|
||||
void model3_state::init_model3_20()
|
||||
@ -6139,11 +6141,11 @@ void model3_state::init_model3_20()
|
||||
interleave_vroms();
|
||||
m_maincpu->space(AS_PROGRAM).install_read_bank(0xff000000, 0xff7fffff, "bank1" );
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xc2000000, 0xc20000ff, read64_delegate(*this, FUNC(model3_state::real3d_dma_r)), write64_delegate(*this, FUNC(model3_state::real3d_dma_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xc2000000, 0xc20000ff, read64s_delegate(*this, FUNC(model3_state::real3d_dma_r)), write64s_delegate(*this, FUNC(model3_state::real3d_dma_w)));
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfec00000, 0xfedfffff, read64_delegate(*this, FUNC(model3_state::mpc106_addr_r)), write64_delegate(*this, FUNC(model3_state::mpc106_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfee00000, 0xfeffffff, read64_delegate(*this, FUNC(model3_state::mpc106_data_r)), write64_delegate(*this, FUNC(model3_state::mpc106_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf8fff000, 0xf8fff0ff, read64_delegate(*this, FUNC(model3_state::mpc106_reg_r)), write64_delegate(*this, FUNC(model3_state::mpc106_reg_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfec00000, 0xfedfffff, read64s_delegate(*this, FUNC(model3_state::mpc106_addr_r)), write64s_delegate(*this, FUNC(model3_state::mpc106_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfee00000, 0xfeffffff, read64s_delegate(*this, FUNC(model3_state::mpc106_data_r)), write64s_delegate(*this, FUNC(model3_state::mpc106_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf8fff000, 0xf8fff0ff, read64sm_delegate(*this, FUNC(model3_state::mpc106_reg_r)), write64sm_delegate(*this, FUNC(model3_state::mpc106_reg_w)));
|
||||
}
|
||||
|
||||
void model3_state::init_lostwsga()
|
||||
@ -6151,7 +6153,7 @@ void model3_state::init_lostwsga()
|
||||
uint32_t *rom = (uint32_t*)memregion("user1")->base();
|
||||
|
||||
init_model3_15();
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xc1000000, 0xc10000ff, read64_delegate(*this, FUNC(model3_state::scsi_r)), write64_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xc1000000, 0xc10000ff, read64s_delegate(*this, FUNC(model3_state::scsi_r)), write64s_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
|
||||
rom[0x7374f0/4] = 0x38840004; /* This seems to be an actual bug in the original code */
|
||||
}
|
||||
@ -6160,7 +6162,7 @@ void model3_state::init_scud()
|
||||
{
|
||||
init_model3_15();
|
||||
/* TODO: network device at 0xC0000000 - FF */
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf9000000, 0xf90000ff, read64_delegate(*this, FUNC(model3_state::scsi_r)), write64_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf9000000, 0xf90000ff, read64s_delegate(*this, FUNC(model3_state::scsi_r)), write64s_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
|
||||
// uint32_t *rom = (uint32_t*)memregion("user1")->base();
|
||||
// rom[(0x799de8^4)/4] = 0x00050208; // secret debug menu
|
||||
@ -6169,20 +6171,20 @@ void model3_state::init_scud()
|
||||
void model3_state::init_scudplus()
|
||||
{
|
||||
init_model3_15();
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xc1000000, 0xc10000ff, read64_delegate(*this, FUNC(model3_state::scsi_r)), write64_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xc1000000, 0xc10000ff, read64s_delegate(*this, FUNC(model3_state::scsi_r)), write64s_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
}
|
||||
|
||||
void model3_state::init_scudplusa()
|
||||
{
|
||||
init_model3_15();
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xc1000000, 0xc10000ff, read64_delegate(*this, FUNC(model3_state::scsi_r)), write64_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xc1000000, 0xc10000ff, read64s_delegate(*this, FUNC(model3_state::scsi_r)), write64s_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
}
|
||||
|
||||
void model3_state::init_lemans24()
|
||||
{
|
||||
init_model3_15();
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xc1000000, 0xc10000ff, read64_delegate(*this, FUNC(model3_state::scsi_r)), write64_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xc1000000, 0xc10000ff, read64s_delegate(*this, FUNC(model3_state::scsi_r)), write64s_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
|
||||
// rom[(0x73fe38^4)/4] = 0x38840004; /* This seems to be an actual bug in the original code */
|
||||
}
|
||||
@ -6208,13 +6210,13 @@ void model3_state::init_vs215()
|
||||
interleave_vroms();
|
||||
m_maincpu->space(AS_PROGRAM).install_read_bank(0xff000000, 0xff7fffff, "bank1" );
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf9000000, 0xf90000ff, read64_delegate(*this, FUNC(model3_state::scsi_r)), write64_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf9000000, 0xf90000ff, read64s_delegate(*this, FUNC(model3_state::scsi_r)), write64s_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0800cf8, 0xf0800cff, read64_delegate(*this, FUNC(model3_state::mpc106_addr_r)), write64_delegate(*this, FUNC(model3_state::mpc106_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfec00000, 0xfedfffff, read64_delegate(*this, FUNC(model3_state::mpc106_addr_r)), write64_delegate(*this, FUNC(model3_state::mpc106_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0c00cf8, 0xf0c00cff, read64_delegate(*this, FUNC(model3_state::mpc106_data_r)), write64_delegate(*this, FUNC(model3_state::mpc106_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfee00000, 0xfeffffff, read64_delegate(*this, FUNC(model3_state::mpc106_data_r)), write64_delegate(*this, FUNC(model3_state::mpc106_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf8fff000, 0xf8fff0ff, read64_delegate(*this, FUNC(model3_state::mpc106_reg_r)), write64_delegate(*this, FUNC(model3_state::mpc106_reg_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0800cf8, 0xf0800cff, read64s_delegate(*this, FUNC(model3_state::mpc106_addr_r)), write64s_delegate(*this, FUNC(model3_state::mpc106_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfec00000, 0xfedfffff, read64s_delegate(*this, FUNC(model3_state::mpc106_addr_r)), write64s_delegate(*this, FUNC(model3_state::mpc106_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0c00cf8, 0xf0c00cff, read64s_delegate(*this, FUNC(model3_state::mpc106_data_r)), write64s_delegate(*this, FUNC(model3_state::mpc106_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfee00000, 0xfeffffff, read64s_delegate(*this, FUNC(model3_state::mpc106_data_r)), write64s_delegate(*this, FUNC(model3_state::mpc106_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf8fff000, 0xf8fff0ff, read64sm_delegate(*this, FUNC(model3_state::mpc106_reg_r)), write64sm_delegate(*this, FUNC(model3_state::mpc106_reg_w)));
|
||||
}
|
||||
|
||||
void model3_state::init_vs29815()
|
||||
@ -6229,13 +6231,13 @@ void model3_state::init_vs29815()
|
||||
interleave_vroms();
|
||||
m_maincpu->space(AS_PROGRAM).install_read_bank(0xff000000, 0xff7fffff, "bank1" );
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf9000000, 0xf90000ff, read64_delegate(*this, FUNC(model3_state::scsi_r)), write64_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf9000000, 0xf90000ff, read64s_delegate(*this, FUNC(model3_state::scsi_r)), write64s_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0800cf8, 0xf0800cff, read64_delegate(*this, FUNC(model3_state::mpc106_addr_r)), write64_delegate(*this, FUNC(model3_state::mpc106_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfec00000, 0xfedfffff, read64_delegate(*this, FUNC(model3_state::mpc106_addr_r)), write64_delegate(*this, FUNC(model3_state::mpc106_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0c00cf8, 0xf0c00cff, read64_delegate(*this, FUNC(model3_state::mpc106_data_r)), write64_delegate(*this, FUNC(model3_state::mpc106_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfee00000, 0xfeffffff, read64_delegate(*this, FUNC(model3_state::mpc106_data_r)), write64_delegate(*this, FUNC(model3_state::mpc106_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf8fff000, 0xf8fff0ff, read64_delegate(*this, FUNC(model3_state::mpc106_reg_r)), write64_delegate(*this, FUNC(model3_state::mpc106_reg_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0800cf8, 0xf0800cff, read64s_delegate(*this, FUNC(model3_state::mpc106_addr_r)), write64s_delegate(*this, FUNC(model3_state::mpc106_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfec00000, 0xfedfffff, read64s_delegate(*this, FUNC(model3_state::mpc106_addr_r)), write64s_delegate(*this, FUNC(model3_state::mpc106_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0c00cf8, 0xf0c00cff, read64s_delegate(*this, FUNC(model3_state::mpc106_data_r)), write64s_delegate(*this, FUNC(model3_state::mpc106_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfee00000, 0xfeffffff, read64s_delegate(*this, FUNC(model3_state::mpc106_data_r)), write64s_delegate(*this, FUNC(model3_state::mpc106_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf8fff000, 0xf8fff0ff, read64sm_delegate(*this, FUNC(model3_state::mpc106_reg_r)), write64sm_delegate(*this, FUNC(model3_state::mpc106_reg_w)));
|
||||
}
|
||||
|
||||
void model3_state::init_bass()
|
||||
@ -6245,13 +6247,13 @@ void model3_state::init_bass()
|
||||
interleave_vroms();
|
||||
m_maincpu->space(AS_PROGRAM).install_read_bank(0xff000000, 0xff7fffff, "bank1" );
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf9000000, 0xf90000ff, read64_delegate(*this, FUNC(model3_state::scsi_r)), write64_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf9000000, 0xf90000ff, read64s_delegate(*this, FUNC(model3_state::scsi_r)), write64s_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0800cf8, 0xf0800cff, read64_delegate(*this, FUNC(model3_state::mpc106_addr_r)), write64_delegate(*this, FUNC(model3_state::mpc106_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfec00000, 0xfedfffff, read64_delegate(*this, FUNC(model3_state::mpc106_addr_r)), write64_delegate(*this, FUNC(model3_state::mpc106_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0c00cf8, 0xf0c00cff, read64_delegate(*this, FUNC(model3_state::mpc106_data_r)), write64_delegate(*this, FUNC(model3_state::mpc106_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfee00000, 0xfeffffff, read64_delegate(*this, FUNC(model3_state::mpc106_data_r)), write64_delegate(*this, FUNC(model3_state::mpc106_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf8fff000, 0xf8fff0ff, read64_delegate(*this, FUNC(model3_state::mpc106_reg_r)), write64_delegate(*this, FUNC(model3_state::mpc106_reg_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0800cf8, 0xf0800cff, read64s_delegate(*this, FUNC(model3_state::mpc106_addr_r)), write64s_delegate(*this, FUNC(model3_state::mpc106_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfec00000, 0xfedfffff, read64s_delegate(*this, FUNC(model3_state::mpc106_addr_r)), write64s_delegate(*this, FUNC(model3_state::mpc106_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0c00cf8, 0xf0c00cff, read64s_delegate(*this, FUNC(model3_state::mpc106_data_r)), write64s_delegate(*this, FUNC(model3_state::mpc106_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xfee00000, 0xfeffffff, read64s_delegate(*this, FUNC(model3_state::mpc106_data_r)), write64s_delegate(*this, FUNC(model3_state::mpc106_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf8fff000, 0xf8fff0ff, read64sm_delegate(*this, FUNC(model3_state::mpc106_reg_r)), write64sm_delegate(*this, FUNC(model3_state::mpc106_reg_w)));
|
||||
}
|
||||
|
||||
void model3_state::init_getbass()
|
||||
@ -6259,11 +6261,12 @@ void model3_state::init_getbass()
|
||||
interleave_vroms();
|
||||
m_maincpu->space(AS_PROGRAM).install_read_bank(0xff000000, 0xff7fffff, "bank1" );
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf9000000, 0xf90000ff, read64_delegate(*this, FUNC(model3_state::scsi_r)), write64_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf9000000, 0xf90000ff, read64s_delegate(*this, FUNC(model3_state::scsi_r)), write64s_delegate(*this, FUNC(model3_state::scsi_w)));
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0800cf8, 0xf0800cff, read64_delegate(*this, FUNC(model3_state::mpc105_addr_r)), write64_delegate(*this, FUNC(model3_state::mpc105_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0c00cf8, 0xf0c00cff, read64_delegate(*this, FUNC(model3_state::mpc105_data_r)), write64_delegate(*this, FUNC(model3_state::mpc105_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf8fff000, 0xf8fff0ff, read64_delegate(*this, FUNC(model3_state::mpc105_reg_r)), write64_delegate(*this, FUNC(model3_state::mpc105_reg_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf0800cf8, 0xf0800cff, read64s_delegate(*this, FUNC(model3_state::mpc105_addr_r)), write64s_delegate(*this, FUNC(model3_state::mpc105_addr_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0xf0c00cf8, 0xf0c00cff, read64smo_delegate(*this, FUNC(model3_state::mpc105_data_r)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xf0c00cf8, 0xf0c00cff, write64s_delegate(*this, FUNC(model3_state::mpc105_data_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xf8fff000, 0xf8fff0ff, read64sm_delegate(*this, FUNC(model3_state::mpc105_reg_r)), write64sm_delegate(*this, FUNC(model3_state::mpc105_reg_w)));
|
||||
}
|
||||
|
||||
void model3_state::init_vs2()
|
||||
@ -6354,7 +6357,7 @@ void model3_state::init_daytona2()
|
||||
// uint32_t *rom = (uint32_t*)memregion("user1")->base();
|
||||
init_model3_20();
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xc3800000, 0xc3800007, write64_delegate(*this, FUNC(model3_state::daytona2_rombank_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xc3800000, 0xc3800007, write64s_delegate(*this, FUNC(model3_state::daytona2_rombank_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_bank(0xc3000000, 0xc37fffff, "bank2");
|
||||
|
||||
//rom[(0x68468c^4)/4] = 0x60000000;
|
||||
@ -6368,7 +6371,7 @@ void model3_state::init_dayto2pe()
|
||||
// uint32_t *rom = (uint32_t*)memregion("user1")->base();
|
||||
init_model3_20();
|
||||
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xc3800000, 0xc3800007, write64_delegate(*this, FUNC(model3_state::daytona2_rombank_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_write_handler(0xc3800000, 0xc3800007, write64s_delegate(*this, FUNC(model3_state::daytona2_rombank_w)));
|
||||
m_maincpu->space(AS_PROGRAM).install_read_bank(0xc3000000, 0xc37fffff, "bank2");
|
||||
|
||||
// rom[(0x606784^4)/4] = 0x60000000;
|
||||
|
@ -130,12 +130,12 @@ Bucky:
|
||||
#define MOO_DMADELAY (100)
|
||||
|
||||
|
||||
READ16_MEMBER(moo_state::control2_r)
|
||||
uint16_t moo_state::control2_r()
|
||||
{
|
||||
return m_cur_control2;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(moo_state::control2_w)
|
||||
void moo_state::control2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
/* bit 0 is data */
|
||||
/* bit 1 is cs (active low) */
|
||||
@ -221,7 +221,7 @@ INTERRUPT_GEN_MEMBER(moo_state::moobl_interrupt)
|
||||
device.execute().set_input_line(5, HOLD_LINE);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(moo_state::sound_irq_w)
|
||||
void moo_state::sound_irq_w(uint16_t data)
|
||||
{
|
||||
m_soundcpu->set_input_line(0, HOLD_LINE);
|
||||
}
|
||||
@ -236,7 +236,7 @@ WRITE8_MEMBER(moo_state::sound_bankswitch_w)
|
||||
|
||||
/* the interface with the 053247 is weird. The chip can address only 0x1000 bytes */
|
||||
/* of RAM, but they put 0x10000 there. The CPU can access them all. */
|
||||
READ16_MEMBER(moo_state::k053247_scattered_word_r)
|
||||
uint16_t moo_state::k053247_scattered_word_r(offs_t offset, uint16_t mem_mask)
|
||||
{
|
||||
if (offset & 0x0078)
|
||||
return m_spriteram[offset];
|
||||
@ -247,7 +247,7 @@ READ16_MEMBER(moo_state::k053247_scattered_word_r)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(moo_state::k053247_scattered_word_w)
|
||||
void moo_state::k053247_scattered_word_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
if (offset & 0x0078)
|
||||
COMBINE_DATA(m_spriteram + offset);
|
||||
@ -262,7 +262,7 @@ WRITE16_MEMBER(moo_state::k053247_scattered_word_w)
|
||||
#endif
|
||||
|
||||
|
||||
WRITE16_MEMBER(moo_state::moo_prot_w)
|
||||
void moo_state::moo_prot_w(address_space &space, offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
uint32_t src1, src2, dst, length, a, b, res;
|
||||
|
||||
@ -292,7 +292,7 @@ WRITE16_MEMBER(moo_state::moo_prot_w)
|
||||
}
|
||||
|
||||
|
||||
WRITE16_MEMBER(moo_state::moobl_oki_bank_w)
|
||||
void moo_state::moobl_oki_bank_w(uint16_t data)
|
||||
{
|
||||
logerror("%x to OKI bank\n", data);
|
||||
|
||||
|
@ -144,7 +144,7 @@ Switches Aux-RS232 Aux Port Alpha Vend-Bus
|
||||
#include "mpu5.lh"
|
||||
|
||||
|
||||
READ8_MEMBER(mpu5_state::asic_r8)
|
||||
uint8_t mpu5_state::asic_r8(offs_t offset)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
@ -173,17 +173,17 @@ READ8_MEMBER(mpu5_state::asic_r8)
|
||||
}
|
||||
|
||||
|
||||
READ32_MEMBER(mpu5_state::asic_r32)
|
||||
uint32_t mpu5_state::asic_r32(offs_t offset, uint32_t mem_mask)
|
||||
{
|
||||
uint32_t retdata = 0;
|
||||
if (ACCESSING_BITS_24_31) retdata |= asic_r8(space,(offset*4)+0) <<24;
|
||||
if (ACCESSING_BITS_16_23) retdata |= asic_r8(space,(offset*4)+1) <<16;
|
||||
if (ACCESSING_BITS_8_15) retdata |= asic_r8(space,(offset*4)+2) <<8;
|
||||
if (ACCESSING_BITS_0_7) retdata |= asic_r8(space,(offset*4)+3) <<0;
|
||||
if (ACCESSING_BITS_24_31) retdata |= asic_r8((offset*4)+0) <<24;
|
||||
if (ACCESSING_BITS_16_23) retdata |= asic_r8((offset*4)+1) <<16;
|
||||
if (ACCESSING_BITS_8_15) retdata |= asic_r8((offset*4)+2) <<8;
|
||||
if (ACCESSING_BITS_0_7) retdata |= asic_r8((offset*4)+3) <<0;
|
||||
return retdata;
|
||||
}
|
||||
|
||||
READ32_MEMBER(mpu5_state::mpu5_mem_r)
|
||||
uint32_t mpu5_state::mpu5_mem_r(offs_t offset, uint32_t mem_mask)
|
||||
{
|
||||
int pc = m_maincpu->pc();
|
||||
int addr = offset *4;
|
||||
@ -208,7 +208,7 @@ READ32_MEMBER(mpu5_state::mpu5_mem_r)
|
||||
|
||||
case 0xf0:
|
||||
{
|
||||
return asic_r32(space, offset&3,mem_mask);
|
||||
return asic_r32(offset&3,mem_mask);
|
||||
}
|
||||
|
||||
default:
|
||||
@ -236,7 +236,7 @@ READ32_MEMBER(mpu5_state::mpu5_mem_r)
|
||||
}
|
||||
|
||||
// Each board is fitted with an ASIC that does most of the heavy lifting, including sound playback.
|
||||
WRITE8_MEMBER(mpu5_state::asic_w8)
|
||||
void mpu5_state::asic_w8(offs_t offset, uint8_t data)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
@ -308,23 +308,23 @@ WRITE8_MEMBER(mpu5_state::asic_w8)
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(mpu5_state::asic_w32)
|
||||
void mpu5_state::asic_w32(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_24_31) asic_w8(space,(offset*4)+0, (data>>24)&0xff);
|
||||
if (ACCESSING_BITS_16_23) asic_w8(space,(offset*4)+1, (data>>16)&0xff);
|
||||
if (ACCESSING_BITS_8_15) asic_w8(space,(offset*4)+2, (data>>8) &0xff);
|
||||
if (ACCESSING_BITS_0_7) asic_w8(space,(offset*4)+3, (data>>0) &0xff);
|
||||
if (ACCESSING_BITS_24_31) asic_w8((offset*4)+0, (data>>24)&0xff);
|
||||
if (ACCESSING_BITS_16_23) asic_w8((offset*4)+1, (data>>16)&0xff);
|
||||
if (ACCESSING_BITS_8_15) asic_w8((offset*4)+2, (data>>8) &0xff);
|
||||
if (ACCESSING_BITS_0_7) asic_w8((offset*4)+3, (data>>0) &0xff);
|
||||
}
|
||||
|
||||
|
||||
READ32_MEMBER(mpu5_state::pic_r)
|
||||
uint32_t mpu5_state::pic_r(offs_t offset)
|
||||
{
|
||||
int pc = m_maincpu->pc();
|
||||
logerror("%08x maincpu read from PIC - offset %01x\n", pc, offset);
|
||||
return m_pic_output_bit;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(mpu5_state::pic_w)
|
||||
void mpu5_state::pic_w(offs_t offset, uint32_t data)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
@ -379,7 +379,7 @@ WRITE32_MEMBER(mpu5_state::pic_w)
|
||||
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(mpu5_state::mpu5_mem_w)
|
||||
void mpu5_state::mpu5_mem_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
int pc = m_maincpu->pc();
|
||||
int addr = offset *4;
|
||||
@ -393,7 +393,7 @@ WRITE32_MEMBER(mpu5_state::mpu5_mem_w)
|
||||
{
|
||||
case 0xd0:
|
||||
{
|
||||
pic_w(space, (addr& 0x0f),data,mem_mask);
|
||||
pic_w((addr& 0x0f),data);
|
||||
break;
|
||||
}
|
||||
case 0xe0:
|
||||
@ -404,7 +404,7 @@ WRITE32_MEMBER(mpu5_state::mpu5_mem_w)
|
||||
|
||||
case 0xf0:
|
||||
{
|
||||
asic_w32(space, offset&3,data,mem_mask);
|
||||
asic_w32(offset&3,data,mem_mask);
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -510,7 +510,7 @@ CUSTOM_INPUT_MEMBER(ms32_state::mahjong_ctrl_r)
|
||||
}
|
||||
|
||||
|
||||
READ32_MEMBER(ms32_state::ms32_read_inputs3)
|
||||
u32 ms32_state::ms32_read_inputs3()
|
||||
{
|
||||
int a,b,c,d;
|
||||
a = ioport("AN2?")->read(); // unused?
|
||||
@ -521,7 +521,7 @@ READ32_MEMBER(ms32_state::ms32_read_inputs3)
|
||||
}
|
||||
|
||||
|
||||
WRITE32_MEMBER(ms32_state::ms32_sound_w)
|
||||
void ms32_state::ms32_sound_w(u32 data)
|
||||
{
|
||||
m_soundlatch->write(data & 0xff);
|
||||
|
||||
@ -529,12 +529,12 @@ WRITE32_MEMBER(ms32_state::ms32_sound_w)
|
||||
m_maincpu->spin_until_time(attotime::from_usec(40));
|
||||
}
|
||||
|
||||
READ32_MEMBER(ms32_state::ms32_sound_r)
|
||||
u32 ms32_state::ms32_sound_r()
|
||||
{
|
||||
return m_to_main^0xff;
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(ms32_state::reset_sub_w)
|
||||
void ms32_state::reset_sub_w(u32 data)
|
||||
{
|
||||
if(data) m_audiocpu->pulse_input_line(INPUT_LINE_RESET, attotime::zero); // 0 too ?
|
||||
}
|
||||
@ -565,71 +565,71 @@ WRITE8_MEMBER(ms32_state::ms32_priram_w8)
|
||||
m_priram[offset] = data;
|
||||
}
|
||||
|
||||
READ16_MEMBER(ms32_state::ms32_palram_r16)
|
||||
u16 ms32_state::ms32_palram_r16(offs_t offset)
|
||||
{
|
||||
return m_palram[offset];
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(ms32_state::ms32_palram_w16)
|
||||
void ms32_state::ms32_palram_w16(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_palram[offset]);
|
||||
}
|
||||
|
||||
READ16_MEMBER(ms32_state::ms32_rozram_r16)
|
||||
u16 ms32_state::ms32_rozram_r16(offs_t offset)
|
||||
{
|
||||
return m_rozram[offset];
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(ms32_state::ms32_rozram_w16)
|
||||
void ms32_state::ms32_rozram_w16(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_rozram[offset]);
|
||||
m_roz_tilemap->mark_tile_dirty(offset/2);
|
||||
}
|
||||
|
||||
READ16_MEMBER(ms32_state::ms32_lineram_r16)
|
||||
u16 ms32_state::ms32_lineram_r16(offs_t offset)
|
||||
{
|
||||
return m_lineram[offset];
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(ms32_state::ms32_lineram_w16)
|
||||
void ms32_state::ms32_lineram_w16(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_lineram[offset]);
|
||||
}
|
||||
|
||||
READ16_MEMBER(ms32_state::ms32_sprram_r16)
|
||||
u16 ms32_state::ms32_sprram_r16(offs_t offset)
|
||||
{
|
||||
return m_sprram[offset];
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(ms32_state::ms32_sprram_w16)
|
||||
void ms32_state::ms32_sprram_w16(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_sprram[offset]);
|
||||
}
|
||||
|
||||
READ16_MEMBER(ms32_state::ms32_txram_r16)
|
||||
u16 ms32_state::ms32_txram_r16(offs_t offset)
|
||||
{
|
||||
return m_txram[offset];
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(ms32_state::ms32_txram_w16)
|
||||
void ms32_state::ms32_txram_w16(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_txram[offset]);
|
||||
m_tx_tilemap->mark_tile_dirty(offset/2);
|
||||
}
|
||||
|
||||
READ16_MEMBER(ms32_state::ms32_bgram_r16)
|
||||
u16 ms32_state::ms32_bgram_r16(offs_t offset)
|
||||
{
|
||||
return m_bgram[offset];
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(ms32_state::ms32_bgram_w16)
|
||||
void ms32_state::ms32_bgram_w16(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_bgram[offset]);
|
||||
m_bg_tilemap->mark_tile_dirty(offset/2);
|
||||
m_bg_tilemap_alt->mark_tile_dirty(offset/2);
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(ms32_state::pip_w)
|
||||
void ms32_state::pip_w(u32 data)
|
||||
{
|
||||
m_tilemaplayoutcontrol = data;
|
||||
|
||||
@ -637,7 +637,7 @@ WRITE32_MEMBER(ms32_state::pip_w)
|
||||
popmessage("fce00a7c = %02x",data);
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(ms32_state::coin_counter_w)
|
||||
void ms32_state::coin_counter_w(u32 data)
|
||||
{
|
||||
// desertwr/p47aces sets 4 here
|
||||
// f1superb sets 2
|
||||
@ -690,23 +690,23 @@ void ms32_state::ms32_map(address_map &map)
|
||||
/* F1 Super Battle has an extra linemap for the road, and am unknown maths chip (mcu?) handling perspective calculations for the road / corners etc. */
|
||||
/* it should use its own memory map */
|
||||
|
||||
WRITE16_MEMBER(ms32_state::ms32_extra_w16)
|
||||
void ms32_state::ms32_extra_w16(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_f1superb_extraram[offset]);
|
||||
m_extra_tilemap->mark_tile_dirty(offset/2);
|
||||
}
|
||||
|
||||
READ16_MEMBER(ms32_state::ms32_extra_r16)
|
||||
u16 ms32_state::ms32_extra_r16(offs_t offset)
|
||||
{
|
||||
return m_f1superb_extraram[offset];
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(ms32_state::ms32_irq2_guess_w)
|
||||
void ms32_state::ms32_irq2_guess_w(u32 data)
|
||||
{
|
||||
irq_raise(2);
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(ms32_state::ms32_irq5_guess_w)
|
||||
void ms32_state::ms32_irq5_guess_w(u32 data)
|
||||
{
|
||||
irq_raise(5);
|
||||
}
|
||||
|
@ -52,7 +52,7 @@ behavior we use .
|
||||
#include "speaker.h"
|
||||
|
||||
|
||||
WRITE16_MEMBER(mugsmash_state::mugsmash_reg2_w)
|
||||
void mugsmash_state::mugsmash_reg2_w(offs_t offset, uint16_t data)
|
||||
{
|
||||
m_regs2[offset] = data;
|
||||
//popmessage ("Regs2 %04x, %04x, %04x, %04x", m_regs2[0], m_regs2[1], m_regs2[2], m_regs2[3]);
|
||||
@ -151,7 +151,7 @@ WRITE16_MEMBER(mugsmash_state::mugsmash_reg2_w)
|
||||
#define USE_FAKE_INPUT_PORTS 0
|
||||
|
||||
#if USE_FAKE_INPUT_PORTS
|
||||
READ16_MEMBER(mugsmash_state::mugsmash_input_ports_r)
|
||||
uint16_t mugsmash_state::mugsmash_input_ports_r(offs_t offset)
|
||||
{
|
||||
uint16_t data = 0xffff;
|
||||
|
||||
|
@ -146,7 +146,7 @@ we have no way of knowing which is the later/corrected version.
|
||||
|
||||
|
||||
|
||||
READ16_MEMBER(mystwarr_state::eeprom_r)
|
||||
uint16_t mystwarr_state::eeprom_r(offs_t offset, uint16_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_0_7)
|
||||
{
|
||||
@ -158,7 +158,7 @@ READ16_MEMBER(mystwarr_state::eeprom_r)
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(mystwarr_state::mweeprom_w)
|
||||
void mystwarr_state::mweeprom_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_8_15)
|
||||
{
|
||||
@ -169,7 +169,7 @@ WRITE16_MEMBER(mystwarr_state::mweeprom_w)
|
||||
|
||||
}
|
||||
|
||||
READ16_MEMBER(mystwarr_state::dddeeprom_r)
|
||||
uint16_t mystwarr_state::dddeeprom_r(offs_t offset, uint16_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_8_15)
|
||||
{
|
||||
@ -179,7 +179,7 @@ READ16_MEMBER(mystwarr_state::dddeeprom_r)
|
||||
return ioport("P2")->read();
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(mystwarr_state::mmeeprom_w)
|
||||
void mystwarr_state::mmeeprom_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_0_7)
|
||||
{
|
||||
@ -244,12 +244,12 @@ INTERRUPT_GEN_MEMBER(mystwarr_state::ddd_interrupt)
|
||||
|
||||
/**********************************************************************************/
|
||||
|
||||
WRITE16_MEMBER(mystwarr_state::sound_irq_w)
|
||||
void mystwarr_state::sound_irq_w(uint16_t data)
|
||||
{
|
||||
m_soundcpu->set_input_line(0, HOLD_LINE);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(mystwarr_state::irq_ack_w)
|
||||
void mystwarr_state::irq_ack_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
m_k056832->b_word_w(offset, data, mem_mask);
|
||||
|
||||
@ -264,7 +264,7 @@ WRITE16_MEMBER(mystwarr_state::irq_ack_w)
|
||||
|
||||
/* the interface with the 053247 is weird. The chip can address only 0x1000 bytes */
|
||||
/* of RAM, but they put 0x10000 there. The CPU can access them all. */
|
||||
READ16_MEMBER(mystwarr_state::k053247_scattered_word_r)
|
||||
uint16_t mystwarr_state::k053247_scattered_word_r(offs_t offset)
|
||||
{
|
||||
if (offset & 0x0078)
|
||||
return m_spriteram[offset];
|
||||
@ -275,7 +275,7 @@ READ16_MEMBER(mystwarr_state::k053247_scattered_word_r)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(mystwarr_state::k053247_scattered_word_w)
|
||||
void mystwarr_state::k053247_scattered_word_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
if (offset & 0x0078)
|
||||
{
|
||||
@ -385,7 +385,7 @@ void mystwarr_state::viostorm_map(address_map &map)
|
||||
}
|
||||
|
||||
// Martial Champion specific interfaces
|
||||
READ16_MEMBER(mystwarr_state::k053247_martchmp_word_r)
|
||||
uint16_t mystwarr_state::k053247_martchmp_word_r(offs_t offset)
|
||||
{
|
||||
if (offset & 0x0018)
|
||||
return m_spriteram[offset];
|
||||
@ -396,7 +396,7 @@ READ16_MEMBER(mystwarr_state::k053247_martchmp_word_r)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(mystwarr_state::k053247_martchmp_word_w)
|
||||
void mystwarr_state::k053247_martchmp_word_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
if (offset & 0x0018)
|
||||
{
|
||||
@ -410,13 +410,13 @@ WRITE16_MEMBER(mystwarr_state::k053247_martchmp_word_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(mystwarr_state::mccontrol_r)
|
||||
uint16_t mystwarr_state::mccontrol_r()
|
||||
{
|
||||
// unknown, buggy watchdog reset code ?
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(mystwarr_state::mccontrol_w)
|
||||
void mystwarr_state::mccontrol_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_8_15)
|
||||
{
|
||||
@ -429,7 +429,7 @@ WRITE16_MEMBER(mystwarr_state::mccontrol_w)
|
||||
// else logerror("write %x to LSB of mccontrol\n", data);
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(mystwarr_state::mceeprom_w)
|
||||
void mystwarr_state::mceeprom_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_8_15)
|
||||
{
|
||||
|
@ -259,12 +259,12 @@ void md_boot_state::jzth_map(address_map &map)
|
||||
map(0x710000, 0x710001).rw(FUNC(md_boot_state::bl_710000_r), FUNC(md_boot_state::bl_710000_w)); // protection, will erase the VDP address causing writes to 0 unless this returns 0xe
|
||||
}
|
||||
|
||||
READ16_MEMBER(md_boot_state::puckpkmna_70001c_r)
|
||||
uint16_t md_boot_state::puckpkmna_70001c_r()
|
||||
{
|
||||
return 0x0e;
|
||||
}
|
||||
|
||||
READ16_MEMBER(md_boot_state::puckpkmna_4b2476_r)
|
||||
uint16_t md_boot_state::puckpkmna_4b2476_r()
|
||||
{
|
||||
if (!strcmp(machine().system().name, "puckpkmnb")) return 0x3100;
|
||||
|
||||
|
@ -2,7 +2,7 @@
|
||||
// copyright-holders:David Caldwell
|
||||
/***************************************************************************
|
||||
|
||||
jrcrypt.c
|
||||
jrcrypt.cpp
|
||||
|
||||
This file is not part of MAME. It is here to provide detailed
|
||||
documentation of the encryption used by Jr. Pac Man ROMs.
|
||||
@ -400,7 +400,7 @@ void write_rom_section(char *prefix,char *suffix,int start,int end)
|
||||
}
|
||||
#endif
|
||||
|
||||
WRITE8_HANDLER( jrpacman_interrupt_mask_w )
|
||||
void jrpacman_interrupt_mask_w(uint8_t data)
|
||||
{
|
||||
irq_mask = data;
|
||||
}
|
||||
|
@ -70,12 +70,12 @@ private:
|
||||
|
||||
IRQ_CALLBACK_MEMBER(jack_sh_irq_ack);
|
||||
void joinem_control_w(uint8_t data);
|
||||
DECLARE_WRITE8_MEMBER(joinem_scroll_w);
|
||||
DECLARE_READ8_MEMBER(striv_question_r);
|
||||
DECLARE_WRITE8_MEMBER(jack_videoram_w);
|
||||
DECLARE_WRITE8_MEMBER(jack_colorram_w);
|
||||
DECLARE_READ8_MEMBER(jack_flipscreen_r);
|
||||
DECLARE_WRITE8_MEMBER(jack_flipscreen_w);
|
||||
void joinem_scroll_w(offs_t offset, uint8_t data);
|
||||
uint8_t striv_question_r(offs_t offset);
|
||||
void jack_videoram_w(offs_t offset, uint8_t data);
|
||||
void jack_colorram_w(offs_t offset, uint8_t data);
|
||||
uint8_t jack_flipscreen_r(offs_t offset);
|
||||
void jack_flipscreen_w(offs_t offset, uint8_t data);
|
||||
uint8_t timer_r();
|
||||
|
||||
TILE_GET_INFO_MEMBER(get_bg_tile_info);
|
||||
|
@ -49,15 +49,15 @@ private:
|
||||
required_device<gfxdecode_device> m_gfxdecode;
|
||||
required_device<palette_device> m_palette;
|
||||
|
||||
DECLARE_READ8_MEMBER(jackalr_rotary_r);
|
||||
DECLARE_WRITE8_MEMBER(jackal_flipscreen_w);
|
||||
DECLARE_READ8_MEMBER(jackal_zram_r);
|
||||
DECLARE_READ8_MEMBER(jackal_voram_r);
|
||||
DECLARE_READ8_MEMBER(jackal_spriteram_r);
|
||||
DECLARE_WRITE8_MEMBER(jackal_rambank_w);
|
||||
DECLARE_WRITE8_MEMBER(jackal_zram_w);
|
||||
DECLARE_WRITE8_MEMBER(jackal_voram_w);
|
||||
DECLARE_WRITE8_MEMBER(jackal_spriteram_w);
|
||||
uint8_t jackalr_rotary_r(offs_t offset);
|
||||
void jackal_flipscreen_w(uint8_t data);
|
||||
uint8_t jackal_zram_r(offs_t offset);
|
||||
uint8_t jackal_voram_r(offs_t offset);
|
||||
uint8_t jackal_spriteram_r(offs_t offset);
|
||||
void jackal_rambank_w(uint8_t data);
|
||||
void jackal_zram_w(offs_t offset, uint8_t data);
|
||||
void jackal_voram_w(offs_t offset, uint8_t data);
|
||||
void jackal_spriteram_w(offs_t offset, uint8_t data);
|
||||
TILE_GET_INFO_MEMBER(get_bg_tile_info);
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
|
@ -192,73 +192,73 @@ private:
|
||||
static void (jaguar_state::*const bitmap16[8])(uint16_t *, int32_t, int32_t, uint32_t *, int32_t);
|
||||
static void (jaguar_state::*const bitmap32[8])(uint16_t *, int32_t, int32_t, uint32_t *, int32_t);
|
||||
|
||||
DECLARE_WRITE32_MEMBER(eeprom_w);
|
||||
DECLARE_READ32_MEMBER(eeprom_clk);
|
||||
DECLARE_READ32_MEMBER(eeprom_cs);
|
||||
DECLARE_READ32_MEMBER(misc_control_r);
|
||||
DECLARE_WRITE32_MEMBER(misc_control_w);
|
||||
DECLARE_READ32_MEMBER(gpuctrl_r);
|
||||
DECLARE_WRITE32_MEMBER(gpuctrl_w);
|
||||
DECLARE_READ32_MEMBER(dspctrl_r);
|
||||
DECLARE_WRITE32_MEMBER(dspctrl_w);
|
||||
DECLARE_READ32_MEMBER(joystick_r);
|
||||
DECLARE_WRITE32_MEMBER(joystick_w);
|
||||
DECLARE_WRITE32_MEMBER(latch_w);
|
||||
DECLARE_READ32_MEMBER(eeprom_data_r);
|
||||
DECLARE_WRITE32_MEMBER(eeprom_enable_w);
|
||||
DECLARE_WRITE32_MEMBER(eeprom_data_w);
|
||||
DECLARE_WRITE32_MEMBER(gpu_jump_w);
|
||||
DECLARE_READ32_MEMBER(gpu_jump_r);
|
||||
DECLARE_READ32_MEMBER(cojagr3k_main_speedup_r);
|
||||
DECLARE_READ32_MEMBER(main_gpu_wait_r);
|
||||
DECLARE_WRITE32_MEMBER(area51_main_speedup_w);
|
||||
DECLARE_WRITE32_MEMBER(area51mx_main_speedup_w);
|
||||
DECLARE_READ16_MEMBER(gpuctrl_r16);
|
||||
DECLARE_WRITE16_MEMBER(gpuctrl_w16);
|
||||
DECLARE_READ16_MEMBER(blitter_r16);
|
||||
DECLARE_WRITE16_MEMBER(blitter_w16);
|
||||
DECLARE_READ16_MEMBER(serial_r16);
|
||||
DECLARE_WRITE16_MEMBER(serial_w16);
|
||||
DECLARE_READ16_MEMBER(dspctrl_r16);
|
||||
DECLARE_WRITE16_MEMBER(dspctrl_w16);
|
||||
DECLARE_READ16_MEMBER(eeprom_cs16);
|
||||
DECLARE_READ16_MEMBER(eeprom_clk16);
|
||||
DECLARE_WRITE16_MEMBER(eeprom_w16);
|
||||
DECLARE_READ16_MEMBER(joystick_r16);
|
||||
DECLARE_WRITE16_MEMBER(joystick_w16);
|
||||
DECLARE_READ32_MEMBER(shared_ram_r);
|
||||
DECLARE_WRITE32_MEMBER(shared_ram_w);
|
||||
DECLARE_READ32_MEMBER(rom_base_r);
|
||||
DECLARE_READ32_MEMBER(wave_rom_r);
|
||||
DECLARE_READ32_MEMBER(dsp_ram_r);
|
||||
DECLARE_WRITE32_MEMBER(dsp_ram_w);
|
||||
DECLARE_READ32_MEMBER(gpu_clut_r);
|
||||
DECLARE_WRITE32_MEMBER(gpu_clut_w);
|
||||
DECLARE_READ32_MEMBER(gpu_ram_r);
|
||||
DECLARE_WRITE32_MEMBER(gpu_ram_w);
|
||||
DECLARE_READ16_MEMBER(shared_ram_r16);
|
||||
DECLARE_WRITE16_MEMBER(shared_ram_w16);
|
||||
DECLARE_READ16_MEMBER(cart_base_r16);
|
||||
DECLARE_READ16_MEMBER(dsp_ram_r16);
|
||||
DECLARE_WRITE16_MEMBER(dsp_ram_w16);
|
||||
DECLARE_READ16_MEMBER(gpu_clut_r16);
|
||||
DECLARE_WRITE16_MEMBER(gpu_clut_w16);
|
||||
DECLARE_READ16_MEMBER(gpu_ram_r16);
|
||||
DECLARE_WRITE16_MEMBER(gpu_ram_w16);
|
||||
void eeprom_w(uint32_t data);
|
||||
uint32_t eeprom_clk();
|
||||
uint32_t eeprom_cs();
|
||||
uint32_t misc_control_r();
|
||||
void misc_control_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint32_t gpuctrl_r(offs_t offset, uint32_t mem_mask = ~0);
|
||||
void gpuctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint32_t dspctrl_r(offs_t offset, uint32_t mem_mask = ~0);
|
||||
void dspctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint32_t joystick_r();
|
||||
void joystick_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
void latch_w(uint32_t data);
|
||||
uint32_t eeprom_data_r(offs_t offset);
|
||||
void eeprom_enable_w(uint32_t data);
|
||||
void eeprom_data_w(offs_t offset, uint32_t data);
|
||||
void gpu_jump_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint32_t gpu_jump_r();
|
||||
uint32_t cojagr3k_main_speedup_r();
|
||||
uint32_t main_gpu_wait_r();
|
||||
void area51_main_speedup_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
void area51mx_main_speedup_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint16_t gpuctrl_r16(offs_t offset, uint16_t mem_mask = ~0);
|
||||
void gpuctrl_w16(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint16_t blitter_r16(offs_t offset, uint16_t mem_mask = ~0);
|
||||
void blitter_w16(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint16_t serial_r16(offs_t offset);
|
||||
void serial_w16(offs_t offset, uint16_t data);
|
||||
uint16_t dspctrl_r16(offs_t offset, uint16_t mem_mask = ~0);
|
||||
void dspctrl_w16(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint16_t eeprom_cs16(offs_t offset);
|
||||
uint16_t eeprom_clk16(offs_t offset);
|
||||
void eeprom_w16(offs_t offset, uint16_t data);
|
||||
uint16_t joystick_r16(offs_t offset);
|
||||
void joystick_w16(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint32_t shared_ram_r(offs_t offset);
|
||||
void shared_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint32_t rom_base_r(offs_t offset);
|
||||
uint32_t wave_rom_r(offs_t offset);
|
||||
uint32_t dsp_ram_r(offs_t offset);
|
||||
void dsp_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint32_t gpu_clut_r(offs_t offset);
|
||||
void gpu_clut_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint32_t gpu_ram_r(offs_t offset);
|
||||
void gpu_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint16_t shared_ram_r16(offs_t offset);
|
||||
void shared_ram_w16(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint16_t cart_base_r16(offs_t offset);
|
||||
uint16_t dsp_ram_r16(offs_t offset);
|
||||
void dsp_ram_w16(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint16_t gpu_clut_r16(offs_t offset);
|
||||
void gpu_clut_w16(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint16_t gpu_ram_r16(offs_t offset);
|
||||
void gpu_ram_w16(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
|
||||
// from audio/jaguar.cpp
|
||||
DECLARE_READ16_MEMBER( jerry_regs_r );
|
||||
DECLARE_WRITE16_MEMBER( jerry_regs_w );
|
||||
DECLARE_READ32_MEMBER( serial_r );
|
||||
DECLARE_WRITE32_MEMBER( serial_w );
|
||||
uint16_t jerry_regs_r(offs_t offset);
|
||||
void jerry_regs_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint32_t serial_r(offs_t offset);
|
||||
void serial_w(offs_t offset, uint32_t data);
|
||||
void serial_update();
|
||||
|
||||
// from video/jaguar.cpp
|
||||
DECLARE_READ32_MEMBER( blitter_r );
|
||||
DECLARE_WRITE32_MEMBER( blitter_w );
|
||||
DECLARE_READ16_MEMBER( tom_regs_r );
|
||||
DECLARE_WRITE16_MEMBER( tom_regs_w );
|
||||
DECLARE_READ32_MEMBER( cojag_gun_input_r );
|
||||
uint32_t blitter_r(offs_t offset, uint32_t mem_mask = ~0);
|
||||
void blitter_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint16_t tom_regs_r(offs_t offset);
|
||||
void tom_regs_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint32_t cojag_gun_input_r(offs_t offset);
|
||||
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
|
||||
void jagpal_ycc(palette_device &palette) const;
|
||||
|
||||
@ -298,11 +298,11 @@ private:
|
||||
void cojag_common_init(uint16_t gpu_jump_offs, uint16_t spin_pc);
|
||||
void init_freeze_common(offs_t main_speedup_addr);
|
||||
|
||||
// from audio/jaguar.c
|
||||
// from audio/jaguar.cpp
|
||||
void update_gpu_irq();
|
||||
DECLARE_WRITE32_MEMBER( dsp_flags_w );
|
||||
void dsp_flags_w(address_space &space, offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
|
||||
// from video/jaguar.c
|
||||
// from video/jaguar.cpp
|
||||
void get_crosshair_xy(int player, int &x, int &y);
|
||||
int effective_hvalue(int value);
|
||||
bool adjust_object_timer(int vc);
|
||||
@ -313,7 +313,7 @@ private:
|
||||
void scanline_update(int param);
|
||||
void set_palette(uint16_t vmode);
|
||||
|
||||
/* from jagobj.c */
|
||||
/* from jagobj.cpp */
|
||||
void jagobj_init();
|
||||
uint32_t *process_bitmap(uint16_t *scanline, uint32_t *objdata, int vc, bool logit);
|
||||
uint32_t *process_scaled_bitmap(uint16_t *scanline, uint32_t *objdata, int vc, bool logit);
|
||||
@ -356,7 +356,7 @@ private:
|
||||
void bitmap_32_6(uint16_t *scanline, int32_t firstpix, int32_t iwidth, uint32_t *src, int32_t xpos);
|
||||
void bitmap_32_7(uint16_t *scanline, int32_t firstpix, int32_t iwidth, uint32_t *src, int32_t xpos);
|
||||
|
||||
/* from jagblit.c */
|
||||
/* from jagblit.cpp */
|
||||
void generic_blitter(uint32_t command, uint32_t a1flags, uint32_t a2flags);
|
||||
void blitter_09800001_010020_010020(uint32_t command, uint32_t a1flags, uint32_t a2flags);
|
||||
void blitter_09800009_000020_000020(uint32_t command, uint32_t a1flags, uint32_t a2flags);
|
||||
@ -391,12 +391,12 @@ protected:
|
||||
virtual void machine_reset() override;
|
||||
|
||||
private:
|
||||
DECLARE_READ16_MEMBER(butch_regs_r16);
|
||||
DECLARE_WRITE16_MEMBER(butch_regs_w16);
|
||||
DECLARE_READ32_MEMBER(butch_regs_r);
|
||||
DECLARE_WRITE32_MEMBER(butch_regs_w);
|
||||
uint16_t butch_regs_r16(offs_t offset);
|
||||
void butch_regs_w16(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint32_t butch_regs_r(offs_t offset);
|
||||
void butch_regs_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
|
||||
DECLARE_READ32_MEMBER(cd_bios_r);
|
||||
uint32_t cd_bios_r(offs_t offset);
|
||||
|
||||
void jaguarcd_map(address_map &map);
|
||||
void jagcd_gpu_dsp_map(address_map &map);
|
||||
|
@ -55,12 +55,12 @@ private:
|
||||
/* misc */
|
||||
uint8_t m_irq_enable;
|
||||
uint8_t m_nmi_enable;
|
||||
DECLARE_WRITE8_MEMBER(ctrl_w);
|
||||
DECLARE_WRITE8_MEMBER(coin_w);
|
||||
DECLARE_WRITE8_MEMBER(videoram_w);
|
||||
DECLARE_WRITE8_MEMBER(colorram_w);
|
||||
DECLARE_READ8_MEMBER(speech_r);
|
||||
DECLARE_WRITE8_MEMBER(speech_w);
|
||||
void ctrl_w(uint8_t data);
|
||||
void coin_w(uint8_t data);
|
||||
void videoram_w(offs_t offset, uint8_t data);
|
||||
void colorram_w(offs_t offset, uint8_t data);
|
||||
uint8_t speech_r();
|
||||
void speech_w(uint8_t data);
|
||||
TILE_GET_INFO_MEMBER(get_bg_tile_info);
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
|
@ -67,8 +67,8 @@ private:
|
||||
void rom_banksel_w(u8 data);
|
||||
DECLARE_WRITE_LINE_MEMBER(coin_counter_left_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(coin_counter_right_w);
|
||||
DECLARE_READ8_MEMBER(novram_data_r);
|
||||
DECLARE_WRITE8_MEMBER(novram_data_w);
|
||||
u8 novram_data_r(address_space &space, offs_t offset);
|
||||
void novram_data_w(offs_t offset, u8 data);
|
||||
void novram_recall_w(offs_t offset, u8 data);
|
||||
void novram_store_w(u8 data);
|
||||
void vscroll_w(offs_t offset, u8 data);
|
||||
|
@ -81,26 +81,26 @@ public:
|
||||
|
||||
private:
|
||||
template <unsigned N> DECLARE_WRITE_LINE_MEMBER(reel_optic_cb) { if (state) m_optic_pattern |= (1 << N); else m_optic_pattern &= ~(1 << N); }
|
||||
DECLARE_READ16_MEMBER(duart_1_r);
|
||||
DECLARE_WRITE16_MEMBER(duart_1_w);
|
||||
DECLARE_READ16_MEMBER(duart_2_r);
|
||||
DECLARE_WRITE16_MEMBER(duart_2_w);
|
||||
DECLARE_READ16_MEMBER(inputs1_r);
|
||||
DECLARE_READ16_MEMBER(unk_r);
|
||||
DECLARE_WRITE16_MEMBER(unk_w);
|
||||
DECLARE_READ16_MEMBER(jpmio_r);
|
||||
DECLARE_WRITE16_MEMBER(jpmio_w);
|
||||
DECLARE_READ16_MEMBER(inputs1awp_r);
|
||||
DECLARE_READ16_MEMBER(optos_r);
|
||||
DECLARE_READ16_MEMBER(prot_1_r);
|
||||
DECLARE_READ16_MEMBER(prot_0_r);
|
||||
DECLARE_WRITE16_MEMBER(jpmioawp_w);
|
||||
DECLARE_READ16_MEMBER(ump_r);
|
||||
DECLARE_WRITE16_MEMBER(jpmimpct_bt477_w);
|
||||
DECLARE_READ16_MEMBER(jpmimpct_bt477_r);
|
||||
DECLARE_WRITE16_MEMBER(volume_w);
|
||||
DECLARE_WRITE16_MEMBER(upd7759_w);
|
||||
DECLARE_READ16_MEMBER(upd7759_r);
|
||||
uint16_t duart_1_r(offs_t offset);
|
||||
void duart_1_w(offs_t offset, uint16_t data);
|
||||
uint16_t duart_2_r(offs_t offset);
|
||||
void duart_2_w(uint16_t data);
|
||||
uint16_t inputs1_r(offs_t offset);
|
||||
uint16_t unk_r();
|
||||
void unk_w(uint16_t data);
|
||||
uint16_t jpmio_r();
|
||||
void jpmio_w(offs_t offset, uint16_t data);
|
||||
uint16_t inputs1awp_r(offs_t offset);
|
||||
uint16_t optos_r();
|
||||
uint16_t prot_1_r();
|
||||
uint16_t prot_0_r();
|
||||
void jpmioawp_w(offs_t offset, uint16_t data);
|
||||
uint16_t ump_r();
|
||||
void jpmimpct_bt477_w(offs_t offset, uint16_t data);
|
||||
uint16_t jpmimpct_bt477_r(offs_t offset);
|
||||
void volume_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void upd7759_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint16_t upd7759_r(offs_t offset, uint16_t mem_mask = ~0);
|
||||
uint8_t hopper_b_r();
|
||||
uint8_t hopper_c_r();
|
||||
void payen_a_w(uint8_t data);
|
||||
|
@ -53,8 +53,8 @@ protected:
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
|
||||
DECLARE_WRITE16_MEMBER(jpm_upd7759_w);
|
||||
DECLARE_READ16_MEMBER(jpm_upd7759_r);
|
||||
void jpm_upd7759_w(offs_t offset, uint16_t data);
|
||||
uint16_t jpm_upd7759_r();
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device_array<acia6850_device, 3> m_acia6850;
|
||||
@ -64,14 +64,14 @@ protected:
|
||||
void jpm_sys5_common_map(address_map &map);
|
||||
|
||||
private:
|
||||
DECLARE_READ16_MEMBER(coins_r);
|
||||
DECLARE_WRITE16_MEMBER(coins_w);
|
||||
DECLARE_READ16_MEMBER(unk_r);
|
||||
DECLARE_WRITE16_MEMBER(mux_w);
|
||||
DECLARE_READ16_MEMBER(mux_r);
|
||||
uint16_t coins_r(offs_t offset);
|
||||
void coins_w(uint16_t data);
|
||||
uint16_t unk_r();
|
||||
void mux_w(offs_t offset, uint16_t data);
|
||||
uint16_t mux_r(offs_t offset);
|
||||
|
||||
DECLARE_READ16_MEMBER(mux_awp_r);
|
||||
DECLARE_READ16_MEMBER(coins_awp_r);
|
||||
uint16_t mux_awp_r(offs_t offset);
|
||||
uint16_t coins_awp_r(offs_t offset);
|
||||
void sys5_draw_lamps();
|
||||
|
||||
void m68000_awp_map(address_map &map);
|
||||
@ -113,10 +113,10 @@ private:
|
||||
virtual void machine_reset() override;
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(generate_tms34061_interrupt);
|
||||
DECLARE_WRITE16_MEMBER(sys5_tms34061_w);
|
||||
DECLARE_READ16_MEMBER(sys5_tms34061_r);
|
||||
DECLARE_WRITE16_MEMBER(ramdac_w);
|
||||
DECLARE_WRITE16_MEMBER(rombank_w);
|
||||
void sys5_tms34061_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint16_t sys5_tms34061_r(offs_t offset, uint16_t mem_mask = ~0);
|
||||
void ramdac_w(offs_t offset, uint16_t data);
|
||||
void rombank_w(uint16_t data);
|
||||
uint32_t screen_update_jpmsys5v(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
|
||||
TIMER_CALLBACK_MEMBER(touch_cb);
|
||||
|
||||
|
@ -26,12 +26,12 @@ public:
|
||||
std::unique_ptr<uint32_t[]> m_videoram;
|
||||
|
||||
/* misc */
|
||||
uint8_t m_mcu_clock;
|
||||
DECLARE_READ8_MEMBER(mcu_sim_r);
|
||||
DECLARE_WRITE8_MEMBER(mcu_sim_w);
|
||||
DECLARE_WRITE8_MEMBER(kangaroo_coin_counter_w);
|
||||
DECLARE_WRITE8_MEMBER(kangaroo_videoram_w);
|
||||
DECLARE_WRITE8_MEMBER(kangaroo_video_control_w);
|
||||
uint8_t m_mcu_clock;
|
||||
uint8_t mcu_sim_r();
|
||||
void mcu_sim_w(uint8_t data);
|
||||
void kangaroo_coin_counter_w(uint8_t data);
|
||||
void kangaroo_videoram_w(offs_t offset, uint8_t data);
|
||||
void kangaroo_video_control_w(offs_t offset, uint8_t data);
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
virtual void video_start() override;
|
||||
|
@ -64,11 +64,11 @@ public:
|
||||
|
||||
u16 mcusim_r();
|
||||
void mcusim_w(u16 data);
|
||||
DECLARE_WRITE16_MEMBER(mcusim_ack_w);
|
||||
DECLARE_WRITE16_MEMBER(mcusim_reset_w);
|
||||
DECLARE_WRITE16_MEMBER(vint_ack_w);
|
||||
DECLARE_WRITE16_MEMBER(videoram_w);
|
||||
void playfield_w(offs_t offset, u16 data, u16 mem_mask);
|
||||
void mcusim_ack_w(u16 data);
|
||||
void mcusim_reset_w(u16 data);
|
||||
void vint_ack_w(u16 data);
|
||||
void videoram_w(offs_t offset, u16 data, u16 mem_mask = ~0);
|
||||
void playfield_w(offs_t offset, u16 data, u16 mem_mask = ~0);
|
||||
void init_wndrplnt();
|
||||
void init_karnov();
|
||||
void init_karnovj();
|
||||
|
@ -42,21 +42,21 @@ public:
|
||||
{}
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(write_centronics_busy);
|
||||
DECLARE_READ8_MEMBER(kaypro484_87_r);
|
||||
DECLARE_READ8_MEMBER(kaypro484_system_port_r);
|
||||
DECLARE_READ8_MEMBER(kaypro484_status_r);
|
||||
DECLARE_READ8_MEMBER(kaypro484_videoram_r);
|
||||
DECLARE_WRITE8_MEMBER(kaypro484_system_port_w);
|
||||
DECLARE_WRITE8_MEMBER(kaypro484_index_w);
|
||||
DECLARE_WRITE8_MEMBER(kaypro484_register_w);
|
||||
DECLARE_WRITE8_MEMBER(kaypro484_videoram_w);
|
||||
uint8_t kaypro484_87_r();
|
||||
uint8_t kaypro484_system_port_r();
|
||||
uint8_t kaypro484_status_r();
|
||||
uint8_t kaypro484_videoram_r();
|
||||
void kaypro484_system_port_w(uint8_t data);
|
||||
void kaypro484_index_w(uint8_t data);
|
||||
void kaypro484_register_w(uint8_t data);
|
||||
void kaypro484_videoram_w(uint8_t data);
|
||||
uint8_t pio_system_r();
|
||||
void kayproii_pio_system_w(uint8_t data);
|
||||
void kayproiv_pio_system_w(uint8_t data);
|
||||
DECLARE_WRITE_LINE_MEMBER(fdc_intrq_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(fdc_drq_w);
|
||||
DECLARE_READ8_MEMBER(kaypro_videoram_r);
|
||||
DECLARE_WRITE8_MEMBER(kaypro_videoram_w);
|
||||
uint8_t kaypro_videoram_r(offs_t offset);
|
||||
void kaypro_videoram_w(offs_t offset, uint8_t data);
|
||||
DECLARE_MACHINE_START(kayproii);
|
||||
DECLARE_MACHINE_RESET(kaypro);
|
||||
DECLARE_VIDEO_START(kaypro);
|
||||
|
@ -79,23 +79,23 @@ public:
|
||||
required_device<screen_device> m_screen;
|
||||
required_device_array<kcexp_slot_device, 3> m_expansions;
|
||||
|
||||
// defined in machine/kc.c
|
||||
// defined in machine/kc.cpp
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
|
||||
// modules read/write
|
||||
DECLARE_READ8_MEMBER ( expansion_read );
|
||||
DECLARE_WRITE8_MEMBER( expansion_write );
|
||||
DECLARE_READ8_MEMBER ( expansion_4000_r );
|
||||
DECLARE_WRITE8_MEMBER( expansion_4000_w );
|
||||
DECLARE_READ8_MEMBER ( expansion_8000_r );
|
||||
DECLARE_WRITE8_MEMBER( expansion_8000_w );
|
||||
DECLARE_READ8_MEMBER ( expansion_c000_r );
|
||||
DECLARE_WRITE8_MEMBER( expansion_c000_w );
|
||||
DECLARE_READ8_MEMBER ( expansion_e000_r );
|
||||
DECLARE_WRITE8_MEMBER( expansion_e000_w );
|
||||
DECLARE_READ8_MEMBER ( expansion_io_read );
|
||||
DECLARE_WRITE8_MEMBER( expansion_io_write );
|
||||
uint8_t expansion_read(offs_t offset);
|
||||
void expansion_write(offs_t offset, uint8_t data);
|
||||
uint8_t expansion_4000_r(offs_t offset);
|
||||
void expansion_4000_w(offs_t offset, uint8_t data);
|
||||
uint8_t expansion_8000_r(offs_t offset);
|
||||
void expansion_8000_w(offs_t offset, uint8_t data);
|
||||
uint8_t expansion_c000_r(offs_t offset);
|
||||
void expansion_c000_w(offs_t offset, uint8_t data);
|
||||
uint8_t expansion_e000_r(offs_t offset);
|
||||
void expansion_e000_w(offs_t offset, uint8_t data);
|
||||
uint8_t expansion_io_read(offs_t offset);
|
||||
void expansion_io_write(offs_t offset, uint8_t data);
|
||||
|
||||
// bankswitch
|
||||
virtual void update_0x00000();
|
||||
@ -126,7 +126,7 @@ public:
|
||||
// speaker
|
||||
void speaker_update();
|
||||
|
||||
// defined in video/kc.c
|
||||
// defined in video/kc.cpp
|
||||
virtual void video_start() override;
|
||||
virtual uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
DECLARE_WRITE_LINE_MEMBER( video_toggle_blink_state );
|
||||
@ -171,19 +171,19 @@ public:
|
||||
: kc_state(mconfig, type, tag)
|
||||
{ }
|
||||
|
||||
// defined in machine/kc.c
|
||||
// defined in machine/kc.cpp
|
||||
virtual void machine_reset() override;
|
||||
|
||||
virtual void update_0x04000() override;
|
||||
virtual void update_0x08000() override;
|
||||
virtual void update_0x0c000() override;
|
||||
|
||||
DECLARE_READ8_MEMBER( kc85_4_86_r );
|
||||
DECLARE_READ8_MEMBER( kc85_4_84_r );
|
||||
DECLARE_WRITE8_MEMBER( kc85_4_86_w );
|
||||
DECLARE_WRITE8_MEMBER( kc85_4_84_w );
|
||||
uint8_t kc85_4_86_r();
|
||||
uint8_t kc85_4_84_r();
|
||||
void kc85_4_86_w(uint8_t data);
|
||||
void kc85_4_84_w(uint8_t data);
|
||||
|
||||
// defined in video/kc.c
|
||||
// defined in video/kc.cpp
|
||||
virtual void video_start() override;
|
||||
virtual uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect) override;
|
||||
void video_control_w(int data);
|
||||
|
@ -73,11 +73,10 @@ private:
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(nmi_enable_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(sound_reset_w);
|
||||
DECLARE_WRITE8_MEMBER(sound_msm_w);
|
||||
DECLARE_READ8_MEMBER(sound_reset_r);
|
||||
DECLARE_WRITE8_MEMBER(kc_sound_control_w);
|
||||
DECLARE_WRITE8_MEMBER(kchamp_videoram_w);
|
||||
DECLARE_WRITE8_MEMBER(kchamp_colorram_w);
|
||||
uint8_t sound_reset_r();
|
||||
void kc_sound_control_w(offs_t offset, uint8_t data);
|
||||
void kchamp_videoram_w(offs_t offset, uint8_t data);
|
||||
void kchamp_colorram_w(offs_t offset, uint8_t data);
|
||||
DECLARE_WRITE_LINE_MEMBER(flipscreen_w);
|
||||
void sound_control_w(u8 data);
|
||||
TILE_GET_INFO_MEMBER(get_bg_tile_info);
|
||||
|
@ -48,17 +48,17 @@ protected:
|
||||
virtual void machine_reset() override;
|
||||
|
||||
private:
|
||||
DECLARE_WRITE16_MEMBER(fgram_w);
|
||||
DECLARE_WRITE16_MEMBER(bgram_w);
|
||||
DECLARE_WRITE16_MEMBER(bg2ram_w);
|
||||
DECLARE_WRITE16_MEMBER(actionhw_snd_w);
|
||||
void fgram_w(offs_t offset, u16 data, u16 mem_mask = ~0);
|
||||
void bgram_w(offs_t offset, u16 data, u16 mem_mask = ~0);
|
||||
void bg2ram_w(offs_t offset, u16 data, u16 mem_mask = ~0);
|
||||
void actionhw_snd_w(offs_t offset, u16 data, u16 mem_mask = ~0);
|
||||
|
||||
void soundio_port_a_w(uint8_t data);
|
||||
uint8_t soundio_port_b_r();
|
||||
void soundio_port_b_w(uint8_t data);
|
||||
uint8_t soundio_port_c_r();
|
||||
void soundio_port_c_w(uint8_t data);
|
||||
DECLARE_WRITE16_MEMBER(to_pic_w);
|
||||
void soundio_port_a_w(u8 data);
|
||||
u8 soundio_port_b_r();
|
||||
void soundio_port_b_w(u8 data);
|
||||
u8 soundio_port_c_r();
|
||||
void soundio_port_c_w(u8 data);
|
||||
void to_pic_w(u16 data);
|
||||
|
||||
TILE_GET_INFO_MEMBER(get_kickgoal_fg_tile_info);
|
||||
TILE_GET_INFO_MEMBER(get_bg_tile_info);
|
||||
|
@ -59,11 +59,11 @@ private:
|
||||
//u8 m_queue[64];
|
||||
//int m_qfront;
|
||||
//int m_qstate;
|
||||
DECLARE_WRITE8_MEMBER(kicknrun_sub_output_w);
|
||||
virtual DECLARE_WRITE8_MEMBER(main_f008_w);
|
||||
void kicknrun_sub_output_w(uint8_t data);
|
||||
virtual void main_f008_w(uint8_t data);
|
||||
|
||||
DECLARE_WRITE8_MEMBER(main_bankswitch_w);
|
||||
DECLARE_READ8_MEMBER(kiki_ym2203_r);
|
||||
void main_bankswitch_w(uint8_t data);
|
||||
uint8_t kiki_ym2203_r(offs_t offset);
|
||||
|
||||
virtual INTERRUPT_GEN_MEMBER(kikikai_interrupt);
|
||||
|
||||
@ -86,22 +86,22 @@ private:
|
||||
uint8_t m_port3_out;
|
||||
uint8_t m_port4_out;
|
||||
|
||||
DECLARE_READ8_MEMBER(kikikai_mcu_ddr1_r);
|
||||
DECLARE_WRITE8_MEMBER(kikikai_mcu_ddr1_w);
|
||||
DECLARE_READ8_MEMBER(kikikai_mcu_ddr2_r);
|
||||
DECLARE_WRITE8_MEMBER(kikikai_mcu_ddr2_w);
|
||||
DECLARE_READ8_MEMBER(kikikai_mcu_ddr3_r);
|
||||
DECLARE_WRITE8_MEMBER(kikikai_mcu_ddr3_w);
|
||||
DECLARE_READ8_MEMBER(kikikai_mcu_ddr4_r);
|
||||
DECLARE_WRITE8_MEMBER(kikikai_mcu_ddr4_w);
|
||||
DECLARE_READ8_MEMBER(kikikai_mcu_port1_r);
|
||||
DECLARE_WRITE8_MEMBER(kikikai_mcu_port1_w);
|
||||
DECLARE_READ8_MEMBER(kikikai_mcu_port2_r);
|
||||
DECLARE_WRITE8_MEMBER(kikikai_mcu_port2_w);
|
||||
DECLARE_READ8_MEMBER(kikikai_mcu_port3_r);
|
||||
DECLARE_WRITE8_MEMBER(kikikai_mcu_port3_w);
|
||||
DECLARE_READ8_MEMBER(kikikai_mcu_port4_r);
|
||||
DECLARE_WRITE8_MEMBER(kikikai_mcu_port4_w);
|
||||
uint8_t kikikai_mcu_ddr1_r();
|
||||
void kikikai_mcu_ddr1_w(uint8_t data);
|
||||
uint8_t kikikai_mcu_ddr2_r();
|
||||
void kikikai_mcu_ddr2_w(uint8_t data);
|
||||
uint8_t kikikai_mcu_ddr3_r();
|
||||
void kikikai_mcu_ddr3_w(uint8_t data);
|
||||
uint8_t kikikai_mcu_ddr4_r();
|
||||
void kikikai_mcu_ddr4_w(uint8_t data);
|
||||
uint8_t kikikai_mcu_port1_r();
|
||||
void kikikai_mcu_port1_w(uint8_t data);
|
||||
uint8_t kikikai_mcu_port2_r();
|
||||
void kikikai_mcu_port2_w(uint8_t data);
|
||||
uint8_t kikikai_mcu_port3_r();
|
||||
void kikikai_mcu_port3_w(uint8_t data);
|
||||
uint8_t kikikai_mcu_port4_r();
|
||||
void kikikai_mcu_port4_w(uint8_t data);
|
||||
};
|
||||
|
||||
class mexico86_state : public kikikai_state
|
||||
@ -121,7 +121,7 @@ protected:
|
||||
virtual void machine_reset() override;
|
||||
|
||||
private:
|
||||
virtual DECLARE_WRITE8_MEMBER(main_f008_w) override;
|
||||
virtual void main_f008_w(uint8_t data) override;
|
||||
|
||||
INTERRUPT_GEN_MEMBER(mexico86_m68705_interrupt);
|
||||
void mexico86_68705_port_a_w(u8 data);
|
||||
@ -153,7 +153,7 @@ protected:
|
||||
virtual void machine_reset() override;
|
||||
|
||||
private:
|
||||
virtual DECLARE_WRITE8_MEMBER(main_f008_w) override;
|
||||
virtual void main_f008_w(uint8_t data) override;
|
||||
|
||||
virtual INTERRUPT_GEN_MEMBER(kikikai_interrupt) override;
|
||||
|
||||
|
@ -62,9 +62,9 @@ private:
|
||||
|
||||
void sound_cmd_w(uint8_t data);
|
||||
void sound_irq_ack_w(uint8_t data);
|
||||
DECLARE_WRITE8_MEMBER(kncljoe_videoram_w);
|
||||
DECLARE_WRITE8_MEMBER(kncljoe_control_w);
|
||||
DECLARE_WRITE8_MEMBER(kncljoe_scroll_w);
|
||||
void kncljoe_videoram_w(offs_t offset, uint8_t data);
|
||||
void kncljoe_control_w(uint8_t data);
|
||||
void kncljoe_scroll_w(offs_t offset, uint8_t data);
|
||||
void m6803_port1_w(uint8_t data);
|
||||
void m6803_port2_w(uint8_t data);
|
||||
uint8_t m6803_port1_r();
|
||||
|
@ -61,26 +61,26 @@ public:
|
||||
, m_lamp(*this, "lamp0")
|
||||
{ }
|
||||
|
||||
DECLARE_WRITE32_MEMBER(esc_w);
|
||||
DECLARE_WRITE32_MEMBER(eeprom_w);
|
||||
DECLARE_WRITE32_MEMBER(control_w);
|
||||
DECLARE_READ32_MEMBER(le2_gun_H_r);
|
||||
DECLARE_READ32_MEMBER(le2_gun_V_r);
|
||||
DECLARE_READ32_MEMBER(type1_roz_r1);
|
||||
DECLARE_READ32_MEMBER(type1_roz_r2);
|
||||
DECLARE_READ32_MEMBER(type3_sync_r);
|
||||
DECLARE_WRITE32_MEMBER(type4_prot_w);
|
||||
DECLARE_WRITE32_MEMBER(type1_cablamps_w);
|
||||
DECLARE_READ16_MEMBER(tms57002_status_word_r);
|
||||
DECLARE_WRITE16_MEMBER(tms57002_control_word_w);
|
||||
DECLARE_READ16_MEMBER(K055550_word_r);
|
||||
DECLARE_WRITE16_MEMBER(K055550_word_w);
|
||||
DECLARE_WRITE16_MEMBER(K053990_martchmp_word_w);
|
||||
DECLARE_WRITE32_MEMBER(fantjour_dma_w);
|
||||
DECLARE_WRITE8_MEMBER(type3_bank_w);
|
||||
DECLARE_WRITE32_MEMBER(konamigx_tilebank_w);
|
||||
DECLARE_WRITE32_MEMBER(konamigx_t1_psacmap_w);
|
||||
DECLARE_WRITE32_MEMBER(konamigx_t4_psacmap_w);
|
||||
void esc_w(address_space &space, uint32_t data);
|
||||
void eeprom_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
void control_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint32_t le2_gun_H_r();
|
||||
uint32_t le2_gun_V_r();
|
||||
uint32_t type1_roz_r1(offs_t offset);
|
||||
uint32_t type1_roz_r2(offs_t offset);
|
||||
uint32_t type3_sync_r();
|
||||
void type4_prot_w(address_space &space, offs_t offset, uint32_t data);
|
||||
void type1_cablamps_w(uint32_t data);
|
||||
uint16_t tms57002_status_word_r();
|
||||
void tms57002_control_word_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint16_t K055550_word_r(offs_t offset);
|
||||
void K055550_word_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void K053990_martchmp_word_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void fantjour_dma_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
void type3_bank_w(offs_t offset, uint8_t data);
|
||||
void konamigx_tilebank_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
void konamigx_t1_psacmap_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
void konamigx_t4_psacmap_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
DECLARE_WRITE_LINE_MEMBER(vblank_irq_ack_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(hblank_irq_ack_w);
|
||||
DECLARE_CUSTOM_INPUT_MEMBER(gx_rdport1_3_r);
|
||||
@ -120,7 +120,7 @@ public:
|
||||
K055673_CB_MEMBER(le2_sprite_callback);
|
||||
|
||||
void common_init();
|
||||
DECLARE_READ32_MEMBER( k_6bpp_rom_long_r );
|
||||
uint32_t k_6bpp_rom_long_r(offs_t offset, uint32_t mem_mask = ~0);
|
||||
void konamigx_mixer (screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect,tilemap_t *sub1, int sub1flags,tilemap_t *sub2, int sub2flags,int mixerflags, bitmap_ind16 *extra_bitmap, int rushingheroes_hack);
|
||||
void konamigx_mixer_draw(screen_device &Screen, bitmap_rgb32 &bitmap, const rectangle &cliprect,
|
||||
tilemap_t *sub1, int sub1flags,
|
||||
|
@ -35,8 +35,8 @@ private:
|
||||
uint8_t sensors2_r();
|
||||
void lamp_w(uint8_t data);
|
||||
void coin_w(uint8_t data);
|
||||
DECLARE_WRITE8_MEMBER(vram_fg_w);
|
||||
DECLARE_WRITE8_MEMBER(vram_bg_w);
|
||||
void vram_fg_w(offs_t offset, uint8_t data);
|
||||
void vram_bg_w(offs_t offset, uint8_t data);
|
||||
void scroll_x_w(uint8_t data);
|
||||
void scroll_y_w(uint8_t data);
|
||||
void gfxbank_w(uint8_t data);
|
||||
|
@ -48,13 +48,13 @@ private:
|
||||
|
||||
/* misc */
|
||||
int m_sound_status;
|
||||
DECLARE_WRITE8_MEMBER(bank_select_w);
|
||||
DECLARE_WRITE8_MEMBER(latch_w);
|
||||
DECLARE_READ8_MEMBER(sound_status_r);
|
||||
DECLARE_WRITE8_MEMBER(tomaincpu_w);
|
||||
DECLARE_READ8_MEMBER(int_ack_r);
|
||||
DECLARE_WRITE8_MEMBER(ksayakyu_videoram_w);
|
||||
DECLARE_WRITE8_MEMBER(ksayakyu_videoctrl_w);
|
||||
void bank_select_w(uint8_t data);
|
||||
void latch_w(uint8_t data);
|
||||
uint8_t sound_status_r();
|
||||
void tomaincpu_w(uint8_t data);
|
||||
uint8_t int_ack_r();
|
||||
void ksayakyu_videoram_w(offs_t offset, uint8_t data);
|
||||
void ksayakyu_videoctrl_w(uint8_t data);
|
||||
void dummy1_w(uint8_t data);
|
||||
void dummy2_w(uint8_t data);
|
||||
void dummy3_w(uint8_t data);
|
||||
|
@ -55,9 +55,9 @@ private:
|
||||
rectangle m_clip0;
|
||||
rectangle m_clip1;
|
||||
|
||||
DECLARE_WRITE8_MEMBER(labyrunr_bankswitch_w);
|
||||
DECLARE_WRITE8_MEMBER(labyrunr_vram1_w);
|
||||
DECLARE_WRITE8_MEMBER(labyrunr_vram2_w);
|
||||
void labyrunr_bankswitch_w(uint8_t data);
|
||||
void labyrunr_vram1_w(offs_t offset, uint8_t data);
|
||||
void labyrunr_vram2_w(offs_t offset, uint8_t data);
|
||||
TILE_GET_INFO_MEMBER(get_tile_info0);
|
||||
TILE_GET_INFO_MEMBER(get_tile_info1);
|
||||
virtual void machine_start() override;
|
||||
|
@ -101,9 +101,9 @@ public:
|
||||
void sraider(machine_config &config);
|
||||
|
||||
protected:
|
||||
DECLARE_READ8_MEMBER(sraider_8005_r);
|
||||
DECLARE_WRITE8_MEMBER(sraider_misc_w);
|
||||
DECLARE_WRITE8_MEMBER(sraider_io_w);
|
||||
uint8_t sraider_8005_r();
|
||||
void sraider_misc_w(offs_t offset, uint8_t data);
|
||||
void sraider_io_w(uint8_t data);
|
||||
void sraider_palette(palette_device &palette) const;
|
||||
DECLARE_WRITE_LINE_MEMBER(screen_vblank_sraider);
|
||||
TILE_GET_INFO_MEMBER(get_grid_tile_info);
|
||||
|
@ -66,23 +66,23 @@ private:
|
||||
required_device<palette_device> m_palette;
|
||||
required_device<generic_latch_8_device> m_soundlatch;
|
||||
|
||||
DECLARE_READ8_MEMBER(from_snd_r);
|
||||
DECLARE_WRITE8_MEMBER(to_main_w);
|
||||
DECLARE_WRITE8_MEMBER(sound_cpu_reset_w);
|
||||
DECLARE_WRITE8_MEMBER(sound_command_w);
|
||||
DECLARE_WRITE8_MEMBER(nmi_disable_w);
|
||||
DECLARE_WRITE8_MEMBER(nmi_enable_w);
|
||||
DECLARE_READ8_MEMBER(snd_flag_r);
|
||||
DECLARE_WRITE8_MEMBER(ladyfrog_spriteram_w);
|
||||
DECLARE_READ8_MEMBER(ladyfrog_spriteram_r);
|
||||
DECLARE_WRITE8_MEMBER(ladyfrog_videoram_w);
|
||||
DECLARE_READ8_MEMBER(ladyfrog_videoram_r);
|
||||
DECLARE_WRITE8_MEMBER(ladyfrog_palette_w);
|
||||
DECLARE_READ8_MEMBER(ladyfrog_palette_r);
|
||||
DECLARE_WRITE8_MEMBER(ladyfrog_gfxctrl_w);
|
||||
DECLARE_WRITE8_MEMBER(ladyfrog_gfxctrl2_w);
|
||||
DECLARE_READ8_MEMBER(ladyfrog_scrlram_r);
|
||||
DECLARE_WRITE8_MEMBER(ladyfrog_scrlram_w);
|
||||
uint8_t from_snd_r();
|
||||
void to_main_w(uint8_t data);
|
||||
void sound_cpu_reset_w(uint8_t data);
|
||||
void sound_command_w(uint8_t data);
|
||||
void nmi_disable_w(uint8_t data);
|
||||
void nmi_enable_w(uint8_t data);
|
||||
uint8_t snd_flag_r();
|
||||
void ladyfrog_spriteram_w(offs_t offset, uint8_t data);
|
||||
uint8_t ladyfrog_spriteram_r(offs_t offset);
|
||||
void ladyfrog_videoram_w(offs_t offset, uint8_t data);
|
||||
uint8_t ladyfrog_videoram_r(offs_t offset);
|
||||
void ladyfrog_palette_w(offs_t offset, uint8_t data);
|
||||
uint8_t ladyfrog_palette_r(offs_t offset);
|
||||
void ladyfrog_gfxctrl_w(uint8_t data);
|
||||
void ladyfrog_gfxctrl2_w(uint8_t data);
|
||||
uint8_t ladyfrog_scrlram_r(offs_t offset);
|
||||
void ladyfrog_scrlram_w(offs_t offset, uint8_t data);
|
||||
void unk_w(uint8_t data);
|
||||
TILE_GET_INFO_MEMBER(get_tile_info);
|
||||
DECLARE_VIDEO_START(toucheme);
|
||||
|
@ -74,23 +74,23 @@ protected:
|
||||
enum { TIMER_SCANLINE };
|
||||
|
||||
// control ports
|
||||
DECLARE_WRITE8_MEMBER(ct_io_w);
|
||||
DECLARE_READ8_MEMBER(rrowx_r);
|
||||
void ct_io_w(uint8_t data);
|
||||
uint8_t rrowx_r();
|
||||
|
||||
INTERRUPT_GEN_MEMBER(laserbat_interrupt);
|
||||
|
||||
// video memory and control ports
|
||||
DECLARE_WRITE8_MEMBER(videoram_w);
|
||||
DECLARE_WRITE8_MEMBER(wcoh_w);
|
||||
DECLARE_WRITE8_MEMBER(wcov_w);
|
||||
DECLARE_WRITE8_MEMBER(cnt_eff_w);
|
||||
DECLARE_WRITE8_MEMBER(cnt_nav_w);
|
||||
void videoram_w(offs_t offset, uint8_t data);
|
||||
void wcoh_w(uint8_t data);
|
||||
void wcov_w(uint8_t data);
|
||||
void cnt_eff_w(uint8_t data);
|
||||
void cnt_nav_w(uint8_t data);
|
||||
|
||||
// sound control ports
|
||||
virtual DECLARE_READ8_MEMBER(rhsc_r);
|
||||
virtual DECLARE_WRITE8_MEMBER(whsc_w);
|
||||
virtual DECLARE_WRITE8_MEMBER(csound1_w);
|
||||
virtual DECLARE_WRITE8_MEMBER(csound2_w);
|
||||
virtual uint8_t rhsc_r();
|
||||
virtual void whsc_w(uint8_t data);
|
||||
virtual void csound1_w(uint8_t data);
|
||||
virtual void csound2_w(uint8_t data);
|
||||
|
||||
// running the video
|
||||
virtual void video_start() override;
|
||||
@ -176,7 +176,7 @@ protected:
|
||||
void laserbat_palette(palette_device &palette) const;
|
||||
|
||||
// sound control ports
|
||||
virtual DECLARE_WRITE8_MEMBER(csound2_w) override;
|
||||
virtual void csound2_w(uint8_t data) override;
|
||||
|
||||
// sound board devices
|
||||
required_device<sn76477_device> m_csg;
|
||||
@ -205,8 +205,8 @@ protected:
|
||||
void catnmous_palette(palette_device &palette) const;
|
||||
|
||||
// sound control ports
|
||||
virtual DECLARE_WRITE8_MEMBER(csound1_w) override;
|
||||
virtual DECLARE_WRITE8_MEMBER(csound2_w) override;
|
||||
virtual void csound1_w(uint8_t data) override;
|
||||
virtual void csound2_w(uint8_t data) override;
|
||||
|
||||
required_device<zac1b11107_audio_device> m_audiopcb;
|
||||
};
|
||||
|
@ -76,15 +76,15 @@ private:
|
||||
required_device<palette_device> m_palette;
|
||||
required_device<generic_latch_8_device> m_soundlatch;
|
||||
|
||||
DECLARE_WRITE8_MEMBER(sound_command_w);
|
||||
DECLARE_READ8_MEMBER(sound_status_r);
|
||||
DECLARE_WRITE8_MEMBER(sound_select_w);
|
||||
DECLARE_WRITE8_MEMBER(lasso_videoram_w);
|
||||
DECLARE_WRITE8_MEMBER(lasso_colorram_w);
|
||||
DECLARE_WRITE8_MEMBER(lasso_flip_screen_w);
|
||||
DECLARE_WRITE8_MEMBER(lasso_video_control_w);
|
||||
DECLARE_WRITE8_MEMBER(wwjgtin_video_control_w);
|
||||
DECLARE_WRITE8_MEMBER(pinbo_video_control_w);
|
||||
void sound_command_w(uint8_t data);
|
||||
uint8_t sound_status_r();
|
||||
void sound_select_w(uint8_t data);
|
||||
void lasso_videoram_w(offs_t offset, uint8_t data);
|
||||
void lasso_colorram_w(offs_t offset, uint8_t data);
|
||||
void lasso_flip_screen_w(uint8_t data);
|
||||
void lasso_video_control_w(uint8_t data);
|
||||
void wwjgtin_video_control_w(uint8_t data);
|
||||
void pinbo_video_control_w(uint8_t data);
|
||||
TILE_GET_INFO_MEMBER(lasso_get_bg_tile_info);
|
||||
TILE_GET_INFO_MEMBER(wwjgtin_get_track_tile_info);
|
||||
TILE_GET_INFO_MEMBER(pinbo_get_bg_tile_info);
|
||||
|
@ -58,12 +58,12 @@ private:
|
||||
int m_sprite_pri_mask;
|
||||
int m_tilemap_priority;
|
||||
|
||||
DECLARE_WRITE8_MEMBER(mg_bankswitch_w);
|
||||
DECLARE_WRITE8_MEMBER(flip_w);
|
||||
DECLARE_WRITE16_MEMBER(vctrl_w);
|
||||
template<int Layer> DECLARE_WRITE16_MEMBER(lastduel_vram_w);
|
||||
DECLARE_WRITE16_MEMBER(txram_w);
|
||||
template<int Layer> DECLARE_WRITE16_MEMBER(madgear_vram_w);
|
||||
void mg_bankswitch_w(uint8_t data);
|
||||
void flip_w(uint8_t data);
|
||||
void vctrl_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
template<int Layer> void lastduel_vram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void txram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
template<int Layer> void madgear_vram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
static rgb_t lastduel_RRRRGGGGBBBBIIII(uint32_t raw);
|
||||
TILE_GET_INFO_MEMBER(ld_get_bg_tile_info);
|
||||
TILE_GET_INFO_MEMBER(ld_get_fg_tile_info);
|
||||
|
@ -72,14 +72,14 @@ private:
|
||||
uint8_t m_sense_state;
|
||||
uint8_t m_attract;
|
||||
|
||||
DECLARE_WRITE8_MEMBER(lazercmd_ctrl_port_w);
|
||||
DECLARE_READ8_MEMBER(lazercmd_ctrl_port_r);
|
||||
DECLARE_WRITE8_MEMBER(lazercmd_data_port_w);
|
||||
DECLARE_READ8_MEMBER(lazercmd_data_port_r);
|
||||
DECLARE_WRITE8_MEMBER(lazercmd_hardware_w);
|
||||
DECLARE_WRITE8_MEMBER(medlanes_hardware_w);
|
||||
DECLARE_WRITE8_MEMBER(bbonk_hardware_w);
|
||||
DECLARE_READ8_MEMBER(lazercmd_hardware_r);
|
||||
void lazercmd_ctrl_port_w(uint8_t data);
|
||||
uint8_t lazercmd_ctrl_port_r();
|
||||
void lazercmd_data_port_w(uint8_t data);
|
||||
uint8_t lazercmd_data_port_r();
|
||||
void lazercmd_hardware_w(offs_t offset, uint8_t data);
|
||||
void medlanes_hardware_w(offs_t offset, uint8_t data);
|
||||
void bbonk_hardware_w(offs_t offset, uint8_t data);
|
||||
uint8_t lazercmd_hardware_r(offs_t offset);
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
void lazercmd_palette(palette_device &palette) const;
|
||||
|
@ -54,11 +54,11 @@ private:
|
||||
|
||||
required_ioport_array<4> m_trackball_io;
|
||||
|
||||
DECLARE_WRITE16_MEMBER(lemmings_control_w);
|
||||
DECLARE_READ16_MEMBER(lemmings_trackball_r);
|
||||
DECLARE_WRITE16_MEMBER(lemmings_pixel_0_w);
|
||||
DECLARE_WRITE16_MEMBER(lemmings_pixel_1_w);
|
||||
DECLARE_WRITE16_MEMBER(lemmings_vram_w);
|
||||
void lemmings_control_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint16_t lemmings_trackball_r(offs_t offset);
|
||||
void lemmings_pixel_0_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void lemmings_pixel_1_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void lemmings_vram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
TILE_GET_INFO_MEMBER(get_tile_info);
|
||||
virtual void machine_start() override;
|
||||
virtual void video_start() override;
|
||||
@ -66,8 +66,8 @@ private:
|
||||
DECLARE_WRITE_LINE_MEMBER(screen_vblank_lemmings);
|
||||
void lemmings_copy_bitmap(bitmap_rgb32& bitmap, int* xscroll, int* yscroll, const rectangle& cliprect);
|
||||
|
||||
DECLARE_READ16_MEMBER( lem_protection_region_0_146_r );
|
||||
DECLARE_WRITE16_MEMBER( lem_protection_region_0_146_w );
|
||||
uint16_t lem_protection_region_0_146_r(offs_t offset);
|
||||
void lem_protection_region_0_146_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void lemmings_map(address_map &map);
|
||||
void sound_map(address_map &map);
|
||||
};
|
||||
|
@ -54,13 +54,13 @@ private:
|
||||
required_device<k054321_device> m_k054321;
|
||||
required_device<palette_device> m_palette;
|
||||
|
||||
DECLARE_WRITE8_MEMBER(control2_w);
|
||||
DECLARE_READ8_MEMBER(sound_irq_r);
|
||||
DECLARE_WRITE8_MEMBER(sound_irq_w);
|
||||
DECLARE_WRITE8_MEMBER(le_bankswitch_w);
|
||||
DECLARE_READ8_MEMBER(guns_r);
|
||||
DECLARE_READ8_MEMBER(gunsaux_r);
|
||||
DECLARE_WRITE8_MEMBER(lethalen_palette_control);
|
||||
void control2_w(uint8_t data);
|
||||
uint8_t sound_irq_r();
|
||||
void sound_irq_w(uint8_t data);
|
||||
void le_bankswitch_w(uint8_t data);
|
||||
uint8_t guns_r(offs_t offset);
|
||||
uint8_t gunsaux_r();
|
||||
void lethalen_palette_control(offs_t offset, uint8_t data);
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
virtual void video_start() override;
|
||||
|
@ -47,11 +47,11 @@ public:
|
||||
DECLARE_CUSTOM_INPUT_MEMBER(cclownz_paddle);
|
||||
|
||||
private:
|
||||
DECLARE_WRITE16_MEMBER(ripribit_control_w);
|
||||
DECLARE_WRITE16_MEMBER(cfarm_control_w);
|
||||
DECLARE_WRITE16_MEMBER(cclownz_control_w);
|
||||
DECLARE_READ16_MEMBER(lethalj_gun_r);
|
||||
DECLARE_WRITE16_MEMBER(blitter_w);
|
||||
void ripribit_control_w(uint16_t data);
|
||||
void cfarm_control_w(uint16_t data);
|
||||
void cclownz_control_w(uint16_t data);
|
||||
uint16_t lethalj_gun_r(offs_t offset);
|
||||
void blitter_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
void do_blit();
|
||||
inline void get_crosshair_xy(int player, int *x, int *y);
|
||||
TMS340X0_SCANLINE_IND16_CB_MEMBER(scanline_update);
|
||||
|
@ -65,22 +65,22 @@ private:
|
||||
required_device<palette_device> m_palette;
|
||||
required_device<generic_latch_8_device> m_soundlatch;
|
||||
|
||||
DECLARE_READ8_MEMBER(deco16_bank_r);
|
||||
DECLARE_READ8_MEMBER(deco16_io_r);
|
||||
DECLARE_WRITE8_MEMBER(deco16_bank_w);
|
||||
DECLARE_READ8_MEMBER(prosoccr_bank_r);
|
||||
DECLARE_READ8_MEMBER(prosoccr_charram_r);
|
||||
DECLARE_WRITE8_MEMBER(prosoccr_charram_w);
|
||||
DECLARE_WRITE8_MEMBER(prosoccr_char_bank_w);
|
||||
DECLARE_WRITE8_MEMBER(prosoccr_io_bank_w);
|
||||
DECLARE_READ8_MEMBER(prosport_charram_r);
|
||||
DECLARE_WRITE8_MEMBER(prosport_charram_w);
|
||||
DECLARE_WRITE8_MEMBER(deco16_io_w);
|
||||
DECLARE_WRITE8_MEMBER(prosoccr_io_w);
|
||||
DECLARE_WRITE8_MEMBER(prosport_io_w);
|
||||
DECLARE_WRITE8_MEMBER(liberate_videoram_w);
|
||||
DECLARE_WRITE8_MEMBER(liberate_colorram_w);
|
||||
DECLARE_WRITE8_MEMBER(prosport_bg_vram_w);
|
||||
uint8_t deco16_bank_r(offs_t offset);
|
||||
uint8_t deco16_io_r(offs_t offset);
|
||||
void deco16_bank_w(uint8_t data);
|
||||
uint8_t prosoccr_bank_r(offs_t offset);
|
||||
uint8_t prosoccr_charram_r(offs_t offset);
|
||||
void prosoccr_charram_w(offs_t offset, uint8_t data);
|
||||
void prosoccr_char_bank_w(uint8_t data);
|
||||
void prosoccr_io_bank_w(uint8_t data);
|
||||
uint8_t prosport_charram_r(offs_t offset);
|
||||
void prosport_charram_w(offs_t offset, uint8_t data);
|
||||
void deco16_io_w(offs_t offset, uint8_t data);
|
||||
void prosoccr_io_w(offs_t offset, uint8_t data);
|
||||
void prosport_io_w(offs_t offset, uint8_t data);
|
||||
void liberate_videoram_w(offs_t offset, uint8_t data);
|
||||
void liberate_colorram_w(offs_t offset, uint8_t data);
|
||||
void prosport_bg_vram_w(offs_t offset, uint8_t data);
|
||||
TILEMAP_MAPPER_MEMBER(back_scan);
|
||||
TILEMAP_MAPPER_MEMBER(fix_scan);
|
||||
TILE_GET_INFO_MEMBER(get_back_tile_info);
|
||||
|
@ -43,23 +43,23 @@ private:
|
||||
virtual void machine_reset() override;
|
||||
virtual void video_start() override;
|
||||
|
||||
DECLARE_WRITE8_MEMBER(output_latch_w);
|
||||
void output_latch_w(offs_t offset, uint8_t data);
|
||||
DECLARE_WRITE_LINE_MEMBER(coin_counter_left_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(coin_counter_right_w);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(trackball_reset_w);
|
||||
DECLARE_READ8_MEMBER(port0_r);
|
||||
uint8_t port0_r();
|
||||
|
||||
DECLARE_WRITE8_MEMBER( bitmap_w );
|
||||
DECLARE_READ8_MEMBER( bitmap_xy_r );
|
||||
DECLARE_WRITE8_MEMBER( bitmap_xy_w );
|
||||
void bitmap_w(offs_t offset, uint8_t data);
|
||||
uint8_t bitmap_xy_r();
|
||||
void bitmap_xy_w(uint8_t data);
|
||||
|
||||
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
|
||||
|
||||
// early raster EAROM interface
|
||||
DECLARE_READ8_MEMBER( earom_r );
|
||||
DECLARE_WRITE8_MEMBER( earom_w );
|
||||
DECLARE_WRITE8_MEMBER( earom_control_w );
|
||||
uint8_t earom_r();
|
||||
void earom_w(offs_t offset, uint8_t data);
|
||||
void earom_control_w(uint8_t data);
|
||||
|
||||
void liberat2_map(address_map &map);
|
||||
void liberatr_map(address_map &map);
|
||||
|
@ -206,12 +206,12 @@ private:
|
||||
int m_last_my;
|
||||
int m_frame_count;
|
||||
int m_videoROM_address;
|
||||
DECLARE_READ8_MEMBER(lisa_fdc_io_r);
|
||||
DECLARE_WRITE8_MEMBER(lisa_fdc_io_w);
|
||||
DECLARE_READ16_MEMBER(lisa_r);
|
||||
DECLARE_WRITE16_MEMBER(lisa_w);
|
||||
DECLARE_READ16_MEMBER(lisa_IO_r);
|
||||
DECLARE_WRITE16_MEMBER(lisa_IO_w);
|
||||
uint8_t lisa_fdc_io_r(offs_t offset);
|
||||
void lisa_fdc_io_w(offs_t offset, uint8_t data);
|
||||
uint16_t lisa_r(offs_t offset, uint16_t mem_mask = ~0);
|
||||
void lisa_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
uint16_t lisa_IO_r(offs_t offset, uint16_t mem_mask = ~0);
|
||||
void lisa_IO_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
|
||||
DECLARE_WRITE_LINE_MEMBER(diag1_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(diag2_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(seg1_w);
|
||||
|
@ -69,16 +69,16 @@ private:
|
||||
required_device<generic_latch_8_device> m_soundlatch;
|
||||
required_device<input_merger_device> m_soundnmi;
|
||||
|
||||
DECLARE_WRITE8_MEMBER(lkage_sh_nmi_disable_w);
|
||||
DECLARE_WRITE8_MEMBER(lkage_sh_nmi_enable_w);
|
||||
DECLARE_READ8_MEMBER(sound_status_r);
|
||||
DECLARE_READ8_MEMBER(port_fetch_r);
|
||||
DECLARE_READ8_MEMBER(mcu_status_r);
|
||||
DECLARE_READ8_MEMBER(fake_mcu_r);
|
||||
DECLARE_WRITE8_MEMBER(fake_mcu_w);
|
||||
DECLARE_READ8_MEMBER(fake_status_r);
|
||||
void lkage_sh_nmi_disable_w(uint8_t data);
|
||||
void lkage_sh_nmi_enable_w(uint8_t data);
|
||||
uint8_t sound_status_r();
|
||||
uint8_t port_fetch_r(offs_t offset);
|
||||
uint8_t mcu_status_r();
|
||||
uint8_t fake_mcu_r();
|
||||
void fake_mcu_w(uint8_t data);
|
||||
uint8_t fake_status_r();
|
||||
|
||||
DECLARE_WRITE8_MEMBER(lkage_videoram_w);
|
||||
void lkage_videoram_w(offs_t offset, uint8_t data);
|
||||
TILE_GET_INFO_MEMBER(get_bg_tile_info);
|
||||
TILE_GET_INFO_MEMBER(get_fg_tile_info);
|
||||
TILE_GET_INFO_MEMBER(get_tx_tile_info);
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user