Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-07-05 01:48:29 +03:00
Code Issues Actions 36 Packages Projects Releases Wiki Activity

Fix c

Browse Source
This commit is contained in:
Olivier Galibert 2020-11-06 17:56:45 +01:00
parent 63a7300ef4
commit 14a076eb86
4 changed files with 11 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mame/drivers/cischeat.cpp
View File

@ -893,7 +893,7 @@ void captflag_state::oki2_map(address_map &map)
void cischeat_state::bigrun_map2(address_map &map) void cischeat_state::bigrun_map2(address_map &map)
{ {
map(0x000000, 0x03ffff).rom(); // ROM map(0x000000, 0x03ffff).rom(); // ROM
map(0x040000, 0x047fff).ram().share("share1"); // Shared RAM (with Main CPU) map(0x040000, 0x043fff).ram().share("share1"); // Shared RAM (with Main CPU)
map(0x080000, 0x0807ff).ram().share("roadram.0"); // Road RAM map(0x080000, 0x0807ff).ram().share("roadram.0"); // Road RAM
map(0x0c0000, 0x0c3fff).ram(); // RAM map(0x0c0000, 0x0c3fff).ram(); // RAM
} }
@ -901,7 +901,7 @@ void cischeat_state::bigrun_map2(address_map &map)
void cischeat_state::bigrun_map3(address_map &map) void cischeat_state::bigrun_map3(address_map &map)
{ {
map(0x000000, 0x03ffff).rom(); // ROM map(0x000000, 0x03ffff).rom(); // ROM
map(0x040000, 0x047fff).ram().share("share2"); // Shared RAM (with Main CPU) map(0x040000, 0x043fff).ram().share("share2"); // Shared RAM (with Main CPU)
map(0x080000, 0x0807ff).ram().share("roadram.1"); // Road RAM map(0x080000, 0x0807ff).ram().share("roadram.1"); // Road RAM
map(0x0c0000, 0x0c3fff).ram(); // RAM map(0x0c0000, 0x0c3fff).ram(); // RAM
} }
@ -940,7 +940,7 @@ void cischeat_state::cischeat_map3(address_map &map)
void cischeat_state::f1gpstar_map2(address_map &map) void cischeat_state::f1gpstar_map2(address_map &map)
{ {
map(0x000000, 0x03ffff).rom(); // ROM map(0x000000, 0x03ffff).rom(); // ROM
map(0x080000, 0x0807ff).ram().share("share1"); // Shared RAM (with Main CPU) map(0x080000, 0x087fff).ram().share("share1"); // Shared RAM (with Main CPU)
map(0x100000, 0x1007ff).ram().share("roadram.0"); // Road RAM map(0x100000, 0x1007ff).ram().share("roadram.0"); // Road RAM
map(0x180000, 0x183fff).ram(); // RAM map(0x180000, 0x183fff).ram(); // RAM
map(0x200000, 0x200001).nopw(); // watchdog map(0x200000, 0x200001).nopw(); // watchdog
@ -949,7 +949,7 @@ void cischeat_state::f1gpstar_map2(address_map &map)
void cischeat_state::f1gpstar_map3(address_map &map) void cischeat_state::f1gpstar_map3(address_map &map)
{ {
map(0x000000, 0x03ffff).rom(); // ROM map(0x000000, 0x03ffff).rom(); // ROM
map(0x080000, 0x0807ff).ram().share("share2"); // Shared RAM (with Main CPU) map(0x080000, 0x087fff).ram().share("share2"); // Shared RAM (with Main CPU)
map(0x100000, 0x1007ff).ram().share("roadram.1"); // Road RAM map(0x100000, 0x1007ff).ram().share("roadram.1"); // Road RAM
map(0x180000, 0x183fff).ram(); // RAM map(0x180000, 0x183fff).ram(); // RAM
map(0x200000, 0x200001).nopw(); // watchdog map(0x200000, 0x200001).nopw(); // watchdog

2
src/mame/drivers/cps3.cpp
View File

@ -2139,7 +2139,7 @@ void cps3_state::cps3_map(address_map &map)
map(0x03000000, 0x030003ff).ram(); // 'FRAM' (sfiii and warzard memory test mode ONLY, and only odd bytes) map(0x03000000, 0x030003ff).ram(); // 'FRAM' (sfiii and warzard memory test mode ONLY, and only odd bytes)
map(0x04000000, 0x0407ffff).ram().share("spriteram"); // Sprite RAM map(0x04000000, 0x0407ffff).ram().share("spriteram"); // Sprite RAM
map(0x04080000, 0x040bffff).rw(FUNC(cps3_state::colourram_r), FUNC(cps3_state::colourram_w)).share("colourram"); // Colour RAM 0x20000 colours map(0x04080000, 0x040bffff).rw(FUNC(cps3_state::colourram_r), FUNC(cps3_state::colourram_w)); // Colour RAM 0x20000 colours
// PPU registers // PPU registers
map(0x040c0000, 0x040c0007).nopr(); // ?? warzard reads this but not use values, dev/debug leftovers ? map(0x040c0000, 0x040c0007).nopr(); // ?? warzard reads this but not use values, dev/debug leftovers ?
map(0x040c000c, 0x040c000d).r(FUNC(cps3_state::dma_status_r)); map(0x040c000c, 0x040c000d).r(FUNC(cps3_state::dma_status_r));

8
src/mame/drivers/crvision.cpp
View File

@ -164,8 +164,8 @@ void crvision_state::crvision_map(address_map &map)
map(0x1000, 0x1003).mirror(0x0ffc).rw(m_pia, FUNC(pia6821_device::read), FUNC(pia6821_device::write)); map(0x1000, 0x1003).mirror(0x0ffc).rw(m_pia, FUNC(pia6821_device::read), FUNC(pia6821_device::write));
map(0x2000, 0x2001).mirror(0x0ffe).r(TMS9929_TAG, FUNC(tms9928a_device::read)); map(0x2000, 0x2001).mirror(0x0ffe).r(TMS9929_TAG, FUNC(tms9928a_device::read));
map(0x3000, 0x3001).mirror(0x0ffe).w(TMS9929_TAG, FUNC(tms9928a_device::write)); map(0x3000, 0x3001).mirror(0x0ffe).w(TMS9929_TAG, FUNC(tms9928a_device::write));
map(0x4000, 0x7fff).bankr(BANK_ROM2); map(0x4000, 0x7fff).rom().share(BANK_ROM2);
map(0x8000, 0xbfff).bankr(BANK_ROM1); map(0x8000, 0xbfff).rom().share(BANK_ROM1);
// map(0xc000, 0xe7ff).bankrw(3); // map(0xc000, 0xe7ff).bankrw(3);
map(0xe800, 0xe800).w(m_cent_data_out, FUNC(output_latch_device::write)); map(0xe800, 0xe800).w(m_cent_data_out, FUNC(output_latch_device::write));
map(0xe801, 0xe801).r("cent_status_in", FUNC(input_buffer_device::read)); map(0xe801, 0xe801).r("cent_status_in", FUNC(input_buffer_device::read));
@ -184,8 +184,8 @@ void laser2001_state::lasr2001_map(address_map &map)
map(0x1000, 0x1003).mirror(0x0ffc).rw(m_pia, FUNC(pia6821_device::read), FUNC(pia6821_device::write)); map(0x1000, 0x1003).mirror(0x0ffc).rw(m_pia, FUNC(pia6821_device::read), FUNC(pia6821_device::write));
map(0x2000, 0x2001).mirror(0x0ffe).r(TMS9929_TAG, FUNC(tms9928a_device::read)); map(0x2000, 0x2001).mirror(0x0ffe).r(TMS9929_TAG, FUNC(tms9928a_device::read));
map(0x3000, 0x3001).mirror(0x0ffe).w(TMS9929_TAG, FUNC(tms9928a_device::write)); map(0x3000, 0x3001).mirror(0x0ffe).w(TMS9929_TAG, FUNC(tms9928a_device::write));
map(0x4000, 0x7fff).bankrw(BANK_ROM2); map(0x4000, 0x7fff).ram().share(BANK_ROM2);
map(0x8000, 0xbfff).bankrw(BANK_ROM1); map(0x8000, 0xbfff).ram().share(BANK_ROM1);
map(0xc000, 0xffff).rom().region(M6502_TAG, 0); map(0xc000, 0xffff).rom().region(M6502_TAG, 0);
} }

4
src/mame/includes/cps3.h
View File

@ -38,7 +38,7 @@ public:
{*this, "simm7.%u", 0U}} {*this, "simm7.%u", 0U}}
, m_mainram(*this, "mainram") , m_mainram(*this, "mainram")
, m_spriteram(*this, "spriteram") , m_spriteram(*this, "spriteram")
, m_colourram(*this, "colourram") , m_colourram(*this, "colourram", 0x40000, ENDIANNESS_BIG)
, m_ppu_gscroll(*this, "ppu_gscroll_regs") , m_ppu_gscroll(*this, "ppu_gscroll_regs")
, m_tilemap_regs(*this, "ppu_tmap_regs") , m_tilemap_regs(*this, "ppu_tmap_regs")
, m_ppu_crtc_zoom(*this, "ppu_crtc_zoom") , m_ppu_crtc_zoom(*this, "ppu_crtc_zoom")
@ -92,7 +92,7 @@ protected:
required_shared_ptr<u32> m_mainram; required_shared_ptr<u32> m_mainram;
required_shared_ptr<u32> m_spriteram; required_shared_ptr<u32> m_spriteram;
required_shared_ptr<u16> m_colourram; memory_share_creator<u16> m_colourram;
required_shared_ptr<u32> m_ppu_gscroll; required_shared_ptr<u32> m_ppu_gscroll;
required_shared_ptr<u32> m_tilemap_regs; required_shared_ptr<u32> m_tilemap_regs;
required_shared_ptr<u32> m_ppu_crtc_zoom; required_shared_ptr<u32> m_ppu_crtc_zoom;