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Changed DSP56k macros to avoid collision with OS X 10.6+ system headers

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This commit is contained in:
R. Belmont 2010-01-17 02:58:59 +00:00
parent 51d5cf69e3
commit 14e2b9acf3
2 changed files with 125 additions and 125 deletions
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32
src/emu/cpu/dsp56k/dsp56def.h
View File

@ -107,29 +107,29 @@ static void S_bits_set(dsp56k_core* cpustate, UINT8 value);
static void I_bits_set(dsp56k_core* cpustate, UINT8 value);
/* CCR setters - with macros for easy access */
#define S_SET() (S_bit_set(cpustate, 1))
#define S_CLEAR() (S_bit_set(cpustate, 0))
#define DSP56K_S_SET() (S_bit_set(cpustate, 1))
#define DSP56K_S_CLEAR() (S_bit_set(cpustate, 0))
static void S_bit_set(dsp56k_core* cpustate, UINT8 value);
#define L_SET() (L_bit_set(cpustate, 1))
#define L_CLEAR() (L_bit_set(cpustate, 0))
#define DSP56K_L_SET() (L_bit_set(cpustate, 1))
#define DSP56K_L_CLEAR() (L_bit_set(cpustate, 0))
static void L_bit_set(dsp56k_core* cpustate, UINT8 value);
#define E_SET() (E_bit_set(cpustate, 1))
#define E_CLEAR() (E_bit_set(cpustate, 0))
#define DSP56K_E_SET() (E_bit_set(cpustate, 1))
#define DSP56K_E_CLEAR() (E_bit_set(cpustate, 0))
static void E_bit_set(dsp56k_core* cpustate, UINT8 value);
#define U_SET() (U_bit_set(cpustate, 1))
#define U_CLEAR() (U_bit_set(cpustate, 0))
#define DSP56K_U_SET() (U_bit_set(cpustate, 1))
#define DSP56K_U_CLEAR() (U_bit_set(cpustate, 0))
static void U_bit_set(dsp56k_core* cpustate, UINT8 value);
#define N_SET() (N_bit_set(cpustate, 1))
#define N_CLEAR() (N_bit_set(cpustate, 0))
#define DSP56K_N_SET() (N_bit_set(cpustate, 1))
#define DSP56K_N_CLEAR() (N_bit_set(cpustate, 0))
static void N_bit_set(dsp56k_core* cpustate, UINT8 value);
#define Z_SET() (Z_bit_set(cpustate, 1))
#define Z_CLEAR() (Z_bit_set(cpustate, 0))
#define DSP56K_Z_SET() (Z_bit_set(cpustate, 1))
#define DSP56K_Z_CLEAR() (Z_bit_set(cpustate, 0))
static void Z_bit_set(dsp56k_core* cpustate, UINT8 value);
#define V_SET() (V_bit_set(cpustate, 1))
#define V_CLEAR() (V_bit_set(cpustate, 0))
#define DSP56K_V_SET() (V_bit_set(cpustate, 1))
#define DSP56K_V_CLEAR() (V_bit_set(cpustate, 0))
static void V_bit_set(dsp56k_core* cpustate, UINT8 value);
#define C_SET() (C_bit_set(cpustate, 1))
#define C_CLEAR() (C_bit_set(cpustate, 0))
#define DSP56K_C_SET() (C_bit_set(cpustate, 1))
#define DSP56K_C_CLEAR() (C_bit_set(cpustate, 0))
static void C_bit_set(dsp56k_core* cpustate, UINT8 value);
// TODO: Maybe some functions for Interrupt Mask and Scaling Mode go here?

218
src/emu/cpu/dsp56k/dsp56ops.c
View File

@ -1156,8 +1156,8 @@ static size_t dsp56k_op_addsub_2(dsp56k_core* cpustate, const UINT16 op_byte, ty
/* S L E U N Z V C */
/* * * * * * * * * */
/* TODO S, L, E, U, V, C */
if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if (*((UINT64*)D.addr) == 0) Z_SET(); else Z_CLEAR();
if (*((UINT64*)D.addr) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if (*((UINT64*)D.addr) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
cycles += 2; /* TODO: + mv oscillator cycles */
return 1;
@ -1207,8 +1207,8 @@ static size_t dsp56k_op_mac_1(dsp56k_core* cpustate, const UINT16 op_byte, typed
/* S L E U N Z V C */
/* * * * * * * * - */
/* TODO: S, L, E, V */
if ( *((UINT64*)D) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_SET(); else Z_CLEAR();
if ( *((UINT64*)D) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
cycles += 2; /* TODO: +mv oscillator cycles */
return 1;
@ -1261,8 +1261,8 @@ static size_t dsp56k_op_mpy_1(dsp56k_core* cpustate, const UINT16 op_byte, typed
/* S L E U N Z V C */
/* * * * * * * * - */
/* TODO: S, L, E, V */
if ( *((UINT64*)D) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_SET(); else Z_CLEAR();
if ( *((UINT64*)D) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
cycles += 2; /* TODO: +mv oscillator cycles */
return 1;
@ -1321,11 +1321,11 @@ static size_t dsp56k_op_clr(dsp56k_core* cpustate, const UINT16 op_byte, typed_p
/* S L E U N Z V C */
/* * * * * * * 0 - */
/* TODO - S, L */
E_CLEAR();
U_SET();
N_CLEAR();
Z_SET();
V_CLEAR();
DSP56K_E_CLEAR();
DSP56K_U_SET();
DSP56K_N_CLEAR();
DSP56K_Z_SET();
DSP56K_V_CLEAR();
cycles += 2; /* TODO: + mv oscillator clock cycles */
return 1;
@ -1362,8 +1362,8 @@ static size_t dsp56k_op_add(dsp56k_core* cpustate, const UINT16 op_byte, typed_p
/* S L E U N Z V C */
/* * * * * * * * * */
/* TODO S, L, E, U, V, C */
if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if (*((UINT64*)D.addr) == 0) Z_SET(); else Z_CLEAR();
if (*((UINT64*)D.addr) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if (*((UINT64*)D.addr) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
cycles += 2; /* TODO: + mv oscillator cycles */
return 1;
@ -1428,8 +1428,8 @@ static size_t dsp56k_op_rnd(dsp56k_core* cpustate, const UINT16 op_byte, typed_p
/* S L E U N Z V C */
/* * * * * * * * - */
/* TODO: S, L, E, U, V */
if ((*((UINT64*)D.addr)) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D.addr)) == 0) Z_SET(); else Z_CLEAR();
if ((*((UINT64*)D.addr)) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D.addr)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
cycles += 2; /* TODO: + mv oscillator clock cycles */
return 1;
@ -1450,10 +1450,10 @@ static size_t dsp56k_op_tst(dsp56k_core* cpustate, const UINT16 op_byte, typed_p
/* S L E U N Z V C */
/* 0 * * * * * 0 0 */
/* TODO: S, L, E, U */
if ((*((UINT64*)D.addr)) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D.addr)) == 0) Z_SET(); else Z_CLEAR();
V_CLEAR();
C_CLEAR();
if ((*((UINT64*)D.addr)) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D.addr)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
DSP56K_V_CLEAR();
DSP56K_C_CLEAR();
cycles += 2; /* TODO: + mv oscillator clock cycles */
return 1;
@ -1480,10 +1480,10 @@ static size_t dsp56k_op_inc(dsp56k_core* cpustate, const UINT16 op_byte, typed_p
/* S L E U N Z V C */
/* * * * * * * * * */
/* TODO: S, L, E, U */
if ( *((UINT64*)D.addr) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D.addr) & U64(0x000000ffffff0000)) == 0) Z_SET(); else Z_CLEAR();
if ((*((UINT64*)D.addr) & U64(0xffffff0000000000)) != 0) V_SET(); else V_CLEAR();
if ((*((UINT64*)D.addr) & U64(0xffffff0000000000)) != 0) C_SET(); else C_CLEAR();
if ( *((UINT64*)D.addr) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D.addr) & U64(0x000000ffffff0000)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
if ((*((UINT64*)D.addr) & U64(0xffffff0000000000)) != 0) DSP56K_V_SET(); else DSP56K_V_CLEAR();
if ((*((UINT64*)D.addr) & U64(0xffffff0000000000)) != 0) DSP56K_C_SET(); else DSP56K_C_CLEAR();
cycles += 2; /* TODO: +mv oscillator cycles */
return 1;
@ -1515,10 +1515,10 @@ static size_t dsp56k_op_inc24(dsp56k_core* cpustate, const UINT16 op_byte, typed
/* S L E U N Z V C */
/* * * * * * ? * * */
/* TODO: S, L, E, U */
if ( *((UINT64*)D.addr) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D.addr) & U64(0x000000ffffff0000)) == 0) Z_SET(); else Z_CLEAR();
if ((workBits24 & 0xff000000) != 0) V_SET(); else V_CLEAR();
if ((workBits24 & 0xff000000) != 0) C_SET(); else C_CLEAR();
if ( *((UINT64*)D.addr) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D.addr) & U64(0x000000ffffff0000)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
if ((workBits24 & 0xff000000) != 0) DSP56K_V_SET(); else DSP56K_V_CLEAR();
if ((workBits24 & 0xff000000) != 0) DSP56K_C_SET(); else DSP56K_C_CLEAR();
cycles += 2; /* TODO: + mv oscillator clock cycles */
return 1;
@ -1544,9 +1544,9 @@ static size_t dsp56k_op_or(dsp56k_core* cpustate, const UINT16 op_byte, typed_po
/* S L E U N Z V C */
/* * * - - ? ? 0 - */
/* TODO: S, L */
if ( *((UINT64*)D.addr) & U64(0x0000000080000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D.addr) & U64(0x00000000ffff0000)) == 0) Z_SET(); else Z_CLEAR();
V_CLEAR();
if ( *((UINT64*)D.addr) & U64(0x0000000080000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D.addr) & U64(0x00000000ffff0000)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
DSP56K_V_CLEAR();
cycles += 2; /* TODO: + mv oscillator cycles */
return 1;
@ -1575,10 +1575,10 @@ static size_t dsp56k_op_asr(dsp56k_core* cpustate, const UINT16 op_byte, typed_p
/* S L E U N Z V C */
/* * * * * * * 0 ? */
/* TODO: S, L, E, U */
if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if (*((UINT64*)D.addr) == 0) Z_SET(); else Z_CLEAR();
V_CLEAR();
if (*p_accum & U64(0x0000000000000001)) C_SET(); else C_CLEAR();
if (*((UINT64*)D.addr) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if (*((UINT64*)D.addr) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
DSP56K_V_CLEAR();
if (*p_accum & U64(0x0000000000000001)) DSP56K_C_SET(); else DSP56K_C_CLEAR();
cycles += 2; /* TODO: + mv oscillator cycles */
return 1;
@ -1615,10 +1615,10 @@ static size_t dsp56k_op_lsr(dsp56k_core* cpustate, const UINT16 op_byte, typed_p
/* S L E U N Z V C */
/* * * - - ? ? 0 ? */
/* TODO: S, L */
N_CLEAR();
if (((PAIR64*)D.addr)->w.h == 0) Z_SET(); else Z_CLEAR();
V_CLEAR();
if (*p_accum & U64(0x0000000000010000)) C_SET(); else C_CLEAR();
DSP56K_N_CLEAR();
if (((PAIR64*)D.addr)->w.h == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
DSP56K_V_CLEAR();
if (*p_accum & U64(0x0000000000010000)) DSP56K_C_SET(); else DSP56K_C_CLEAR();
cycles += 2; /* TODO: + mv oscillator cycles */
return 1;
@ -1689,10 +1689,10 @@ static size_t dsp56k_op_sub(dsp56k_core* cpustate, const UINT16 op_byte, typed_p
/* S L E U N Z V C */
/* * * * * * * * * */
/* TODO S, L, E, U */
if ( *((UINT64*)D.addr) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if ( *((UINT64*)D.addr) == 0) Z_SET(); else Z_CLEAR();
if ((*((UINT64*)D.addr) & U64(0xffffff0000000000)) != 0) V_SET(); else V_CLEAR();
if ((*((UINT64*)D.addr) & U64(0xffffff0000000000)) != 0) C_SET(); else C_CLEAR();
if ( *((UINT64*)D.addr) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ( *((UINT64*)D.addr) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
if ((*((UINT64*)D.addr) & U64(0xffffff0000000000)) != 0) DSP56K_V_SET(); else DSP56K_V_CLEAR();
if ((*((UINT64*)D.addr) & U64(0xffffff0000000000)) != 0) DSP56K_C_SET(); else DSP56K_C_CLEAR();
cycles += 2; /* TODO: + mv oscillator cycles */
return 1;
@ -1752,10 +1752,10 @@ static size_t dsp56k_op_cmp(dsp56k_core* cpustate, const UINT16 op_byte, typed_p
/* S L E U N Z V C */
/* * * * * * * * * */
/* TODO: S, L, E, U */
if ( result & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if ( result == 0) Z_SET(); else Z_CLEAR();
if ((result & U64(0xffffff0000000000)) != 0) V_SET(); else V_CLEAR();
if ((result & U64(0xffffff0000000000)) != 0) C_SET(); else C_CLEAR();
if ( result & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ( result == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
if ((result & U64(0xffffff0000000000)) != 0) DSP56K_V_SET(); else DSP56K_V_CLEAR();
if ((result & U64(0xffffff0000000000)) != 0) DSP56K_C_SET(); else DSP56K_C_CLEAR();
cycles += 2; /* TODO: + mv oscillator clock cycles */
@ -1787,9 +1787,9 @@ static size_t dsp56k_op_not(dsp56k_core* cpustate, const UINT16 op_byte, typed_p
/* S L E U N Z V C */
/* * * - - ? ? 0 - */
/* TODO: S?, L */
if ( *((UINT64*)D.addr) & U64(0x0000000080000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D.addr) & U64(0x00000000ffff0000)) == 0) Z_SET(); else Z_CLEAR();
V_CLEAR();
if ( *((UINT64*)D.addr) & U64(0x0000000080000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D.addr) & U64(0x00000000ffff0000)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
DSP56K_V_CLEAR();
cycles += 2; /* TODO: + mv oscillator cycles */
return 1;
@ -1829,8 +1829,8 @@ static size_t dsp56k_op_dec24(dsp56k_core* cpustate, const UINT16 op_byte, typed
/* S L E U N Z V C */
/* * * * * * ? * * */
/* TODO: S, L, E, U, V, C */
if ( *((UINT64*)D.addr) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D.addr) & U64(0x000000ffffff0000)) == 0) Z_SET(); else Z_CLEAR();
if ( *((UINT64*)D.addr) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D.addr) & U64(0x000000ffffff0000)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
cycles += 2; /* TODO: + mv oscillator clock cycles */
return 1;
@ -1856,9 +1856,9 @@ static size_t dsp56k_op_and(dsp56k_core* cpustate, const UINT16 op_byte, typed_p
/* S L E U N Z V C */
/* * * - - ? ? 0 - */
/* TODO: S, L */
if ( *((UINT64*)D.addr) & U64(0x0000000080000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D.addr) & U64(0x00000000ffff0000)) == 0) Z_SET(); else Z_CLEAR();
V_CLEAR();
if ( *((UINT64*)D.addr) & U64(0x0000000080000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D.addr) & U64(0x00000000ffff0000)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
DSP56K_V_CLEAR();
cycles += 2; /* TODO: + mv oscillator cycles */
return 1;
@ -1895,9 +1895,9 @@ static size_t dsp56k_op_abs(dsp56k_core* cpustate, const UINT16 op_byte, typed_p
/* S L E U N Z V C */
/* * * * * * * * - */
/* TODO: S, L, E, U */
if ( *((UINT64*)D.addr) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D.addr) & U64(0x000000ffffffffff)) == 0) Z_SET(); else Z_CLEAR();
if ((*p_accum) == U64(0x0000008000000000)) V_SET(); else V_CLEAR();
if ( *((UINT64*)D.addr) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D.addr) & U64(0x000000ffffffffff)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
if ((*p_accum) == U64(0x0000008000000000)) DSP56K_V_SET(); else DSP56K_V_CLEAR();
cycles += 2; /* TODO: + mv oscillator clock cycles */
return 1;
@ -1978,10 +1978,10 @@ static size_t dsp56k_op_cmpm(dsp56k_core* cpustate, const UINT16 op_byte, typed_
/* S L E U N Z V C */
/* * * * * * * * * */
/* TODO: S, L, E, U */
if ( (absResult) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if (((absResult) & U64(0x000000ffffffffff)) == 0) Z_SET(); else Z_CLEAR();
if ( (absResult & U64(0xffffff0000000000)) != 0) V_SET(); else V_CLEAR();
if ( (absResult & U64(0xffffff0000000000)) != 0) C_SET(); else C_CLEAR();
if ( (absResult) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if (((absResult) & U64(0x000000ffffffffff)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
if ( (absResult & U64(0xffffff0000000000)) != 0) DSP56K_V_SET(); else DSP56K_V_CLEAR();
if ( (absResult & U64(0xffffff0000000000)) != 0) DSP56K_C_SET(); else DSP56K_C_CLEAR();
cycles += 2; /* TODO: +mv oscillator cycles */
return 1;
@ -2020,8 +2020,8 @@ static size_t dsp56k_op_mpy(dsp56k_core* cpustate, const UINT16 op_byte, typed_p
/* S L E U N Z V C */
/* * * * * * * * - */
/* TODO: S, L, E, V */
if ( *((UINT64*)D) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_SET(); else Z_CLEAR();
if ( *((UINT64*)D) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
cycles += 2; /* TODO: +mv oscillator cycles */
return 1;
@ -2086,8 +2086,8 @@ static size_t dsp56k_op_mac(dsp56k_core* cpustate, const UINT16 op_byte, typed_p
/* S L E U N Z V C */
/* * * * * * * * - */
/* TODO: S, L, E, V */
if ( *((UINT64*)D) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_SET(); else Z_CLEAR();
if ( *((UINT64*)D) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
cycles += 2; /* TODO: +mv oscillator cycles */
return 1;
@ -2152,8 +2152,8 @@ static size_t dsp56k_op_macr(dsp56k_core* cpustate, const UINT16 op_byte, typed_
/* S L E U N Z V C */
/* * * * * * * * - */
/* TODO: S, L, E, V */
if ( *((UINT64*)D) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_SET(); else Z_CLEAR();
if ( *((UINT64*)D) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
cycles += 2; /* TODO: +mv oscillator cycles */
return 1;
@ -2222,10 +2222,10 @@ static size_t dsp56k_op_asl4(dsp56k_core* cpustate, const UINT16 op, UINT8* cycl
/* V - Set if an arithmetic overflow occurs in the 40 bit result. Also set if bit 35 through 39 are
not the same. */
/* C - Set if bit 36 of source operand is set. Cleared otherwise. */
if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if (*((UINT64*)D.addr) == 0) Z_SET(); else Z_CLEAR();
if ( (*((UINT64*)D.addr) & U64(0x000000ff00000000)) != (p_accum & U64(0x000000ff00000000)) ) V_SET(); else V_CLEAR();
if (p_accum & U64(0x0000001000000000)) C_SET(); else C_CLEAR();
if (*((UINT64*)D.addr) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if (*((UINT64*)D.addr) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
if ( (*((UINT64*)D.addr) & U64(0x000000ff00000000)) != (p_accum & U64(0x000000ff00000000)) ) DSP56K_V_SET(); else DSP56K_V_CLEAR();
if (p_accum & U64(0x0000001000000000)) DSP56K_C_SET(); else DSP56K_C_CLEAR();
cycles += 2;
return 1;
@ -2253,10 +2253,10 @@ static size_t dsp56k_op_asr4(dsp56k_core* cpustate, const UINT16 op, UINT8* cycl
/* - * * * * * 0 ? */
/* TODO: E, U */
/* C - Set if bit 3 of source operand is set. Cleared otherwise. */
if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if (*((UINT64*)D.addr) == 0) Z_SET(); else Z_CLEAR();
V_CLEAR();
if (p_accum & U64(0x0000000000000008)) C_SET(); else C_CLEAR();
if (*((UINT64*)D.addr) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if (*((UINT64*)D.addr) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
DSP56K_V_CLEAR();
if (p_accum & U64(0x0000000000000008)) DSP56K_C_SET(); else DSP56K_C_CLEAR();
cycles += 2;
return 1;
@ -2282,10 +2282,10 @@ static size_t dsp56k_op_asr16(dsp56k_core* cpustate, const UINT16 op, UINT8* cyc
/* S L E U N Z V C */
/* - * * * * * 0 ? */
/* TODO: E, U */
if (*((UINT64*)D.addr) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if (*((UINT64*)D.addr) == 0) Z_SET(); else Z_CLEAR();
V_CLEAR();
if (backupVal & U64(0x0000000000008000)) C_SET(); else C_CLEAR();
if (*((UINT64*)D.addr) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if (*((UINT64*)D.addr) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
DSP56K_V_CLEAR();
if (backupVal & U64(0x0000000000008000)) DSP56K_C_SET(); else DSP56K_C_CLEAR();
cycles += 2;
return 1;
@ -2339,15 +2339,15 @@ static size_t dsp56k_op_bfop(dsp56k_core* cpustate, const UINT16 op, const UINT1
switch(BITS(op2, 0x1f00))
{
case 0x12: /* BFCHG */
if ((iVal & previousValue) == iVal) C_SET(); else C_CLEAR(); break;
if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
case 0x04: /* BFCLR */
if ((iVal & previousValue) == iVal) C_SET(); else C_CLEAR(); break;
if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
case 0x18: /* BFSET */
if ((iVal & previousValue) == iVal) C_SET(); else C_CLEAR(); break;
if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
case 0x10: /* BFTSTH */
if ((iVal & previousValue) == iVal) C_SET(); else C_CLEAR(); break;
if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
case 0x00: /* BFTSTL */
if ((iVal & previousValue) == 0x0000) C_SET(); else C_CLEAR(); break;
if ((iVal & previousValue) == 0x0000) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
}
cycles += 4; /* TODO: + mvb oscillator clock cycles */
@ -2405,15 +2405,15 @@ static size_t dsp56k_op_bfop_1(dsp56k_core* cpustate, const UINT16 op, const UIN
switch(BITS(op2, 0x1f00))
{
case 0x12: /* BFCHG */
if ((iVal & previousValue) == iVal) C_SET(); else C_CLEAR(); break;
if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
case 0x04: /* BFCLR */
if ((iVal & previousValue) == iVal) C_SET(); else C_CLEAR(); break;
if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
case 0x18: /* BFSET */
if ((iVal & previousValue) == iVal) C_SET(); else C_CLEAR(); break;
if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
case 0x10: /* BFTSTH */
if ((iVal & previousValue) == iVal) C_SET(); else C_CLEAR(); break;
if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
case 0x00: /* BFTSTL */
if ((iVal & previousValue) == 0x0000) C_SET(); else C_CLEAR(); break;
if ((iVal & previousValue) == 0x0000) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
}
cycles += 4; /* TODO: + mvb oscillator clock cycles */
@ -2475,15 +2475,15 @@ static size_t dsp56k_op_bfop_2(dsp56k_core* cpustate, const UINT16 op, const UIN
switch(BITS(op2, 0x1f00))
{
case 0x12: /* BFCHG */
if ((iVal & previousValue) == iVal) C_SET(); else C_CLEAR(); break;
if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
case 0x04: /* BFCLR */
if ((iVal & previousValue) == iVal) C_SET(); else C_CLEAR(); break;
if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
case 0x18: /* BFSET */
if ((iVal & previousValue) == iVal) C_SET(); else C_CLEAR(); break;
if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
case 0x10: /* BFTSTH */
if ((iVal & previousValue) == iVal) C_SET(); else C_CLEAR(); break;
if ((iVal & previousValue) == iVal) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
case 0x00: /* BFTSTL */
if ((iVal & previousValue) == 0x0000) C_SET(); else C_CLEAR(); break;
if ((iVal & previousValue) == 0x0000) DSP56K_C_SET(); else DSP56K_C_CLEAR(); break;
}
cycles += 4; /* TODO: + mvb oscillator clock cycles */
@ -2783,8 +2783,8 @@ static size_t dsp56k_op_dmac(dsp56k_core* cpustate, const UINT16 op, UINT8* cycl
/* S L E U N Z V C */
/* - * * * * * * - */
/* TODO: L, E, U, V */
if ( *((UINT64*)D) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_SET(); else Z_CLEAR();
if ( *((UINT64*)D) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
cycles += 2;
return 1;
@ -3010,9 +3010,9 @@ static size_t dsp56k_op_imac(dsp56k_core* cpustate, const UINT16 op, UINT8* cycl
/* - * ? ? * ? ? - */
/* TODO: L */
/* U,E - Will not be set correctly by this instruction*/
if ( *((UINT64*)D) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffff0000)) == 0) Z_SET(); else Z_CLEAR();
V_CLEAR();
if ( *((UINT64*)D) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffff0000)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
DSP56K_V_CLEAR();
cycles += 2;
return 1;
@ -3252,8 +3252,8 @@ static size_t dsp56k_op_macsuuu(dsp56k_core* cpustate, const UINT16 op, UINT8* c
/* S L E U N Z V C */
/* - * * * * * * - */
/* TODO: L, E, U, V */
if ( *((UINT64*)D) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_SET(); else Z_CLEAR();
if ( *((UINT64*)D) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
cycles += 2;
return 1;
@ -3723,8 +3723,8 @@ static size_t dsp56k_op_mpysuuu(dsp56k_core* cpustate, const UINT16 op, UINT8* c
/* S L E U N Z V C */
/* - * * * * * * - */
/* TODO: L, E, U, V */
if ( *((UINT64*)D) & U64(0x0000008000000000)) N_SET(); else N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) Z_SET(); else Z_CLEAR();
if ( *((UINT64*)D) & U64(0x0000008000000000)) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT64*)D) & U64(0x000000ffffffffff)) == 0) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
cycles += 2;
return 1;
@ -3977,13 +3977,13 @@ static size_t dsp56k_op_tst2(dsp56k_core* cpustate, const UINT16 op, UINT8* cycl
/* S L E U N Z V C */
/* - * * * * * 0 0 */
/* (L,E,U should be set to 0) */
L_CLEAR();
E_CLEAR();
DSP56K_L_CLEAR();
DSP56K_E_CLEAR();
/* U_CLEAR(); */ /* TODO: Conflicting opinions? "Set if unnormalized." Documentation is weird (A&B?) */
if ((*((UINT16*)D.addr)) & 0x8000) N_SET(); else N_CLEAR();
if ((*((UINT16*)D.addr)) == 0x0000) Z_SET(); else Z_CLEAR();
/* V_CLEAR(); */ /* Unaffected */
C_CLEAR();
if ((*((UINT16*)D.addr)) & 0x8000) DSP56K_N_SET(); else DSP56K_N_CLEAR();
if ((*((UINT16*)D.addr)) == 0x0000) DSP56K_Z_SET(); else DSP56K_Z_CLEAR();
/* DSP56K_V_CLEAR(); */ /* Unaffected */
DSP56K_C_CLEAR();
cycles += 2;
return 1;