Merge pull request #446 from Happy-yappH/master

n64: Simulation of cpu cycles from the skipped RDRAM initialization.  This allows later SI initialization to see something closer to an expected value for the system uptime.
This commit is contained in:
Vas Crabb 2015-10-31 20:01:00 +11:00
commit 157cfffcc8
3 changed files with 22 additions and 1 deletions

View File

@ -2701,6 +2701,11 @@ void mips3_device::handle_special(UINT32 op)
}
}
void mips3_device::burn_cycles(INT32 cycles)
{
execute_burn(cycles);
}
void mips3_device::execute_run()
{
if (m_isdrc)

View File

@ -300,7 +300,8 @@ public:
void clear_fastram(UINT32 select_start);
void mips3drc_set_options(UINT32 options);
void mips3drc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles);
void burn_cycles(INT32 cycles);
protected:
// device-level overrides
virtual void device_start();
@ -313,6 +314,7 @@ protected:
virtual UINT32 execute_input_lines() const { return 6; }
virtual void execute_run();
virtual void execute_set_input(int inputnum, int state);
virtual void execute_burn(INT32 cycles) { m_totalcycles += cycles; }
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }

View File

@ -1667,6 +1667,20 @@ WRITE32_MEMBER( n64_periphs::pi_reg_w )
READ32_MEMBER( n64_periphs::ri_reg_r )
{
if(offset == 0x0C/4) // RI_SELECT
{
/* This is to 'simulate' the time that RDRAM initialization
would take if the RI registers were not set to skip the RDRAM
testing during device reset. Proper simulation would require
emulating the RDRAM modules and bus stalls for the mips cpu.
The cycle amount chosen represents 1/2 second, which is not
necessarily the time for RDRAM initialization, but rather the
time recommended for letting the SI devices settle after startup.
This allows the initialization routines for the SI to see that a
proper amount of time has passed since system startup. */
machine().device<mips3_device>("maincpu")->burn_cycles(93750000/2);
}
if(offset > 0x1c/4)
{
logerror("ri_reg_r: %08X, %08X at %08X\n", offset, mem_mask, maincpu->safe_pc());