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Merge pull request #446 from Happy-yappH/master
n64: Simulation of cpu cycles from the skipped RDRAM initialization. This allows later SI initialization to see something closer to an expected value for the system uptime.
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commit
157cfffcc8
@ -2701,6 +2701,11 @@ void mips3_device::handle_special(UINT32 op)
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}
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}
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void mips3_device::burn_cycles(INT32 cycles)
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{
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execute_burn(cycles);
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}
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void mips3_device::execute_run()
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{
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if (m_isdrc)
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@ -300,7 +300,8 @@ public:
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void clear_fastram(UINT32 select_start);
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void mips3drc_set_options(UINT32 options);
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void mips3drc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles);
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void burn_cycles(INT32 cycles);
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protected:
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// device-level overrides
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virtual void device_start();
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@ -313,6 +314,7 @@ protected:
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virtual UINT32 execute_input_lines() const { return 6; }
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virtual void execute_run();
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virtual void execute_set_input(int inputnum, int state);
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virtual void execute_burn(INT32 cycles) { m_totalcycles += cycles; }
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// device_memory_interface overrides
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
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@ -1667,6 +1667,20 @@ WRITE32_MEMBER( n64_periphs::pi_reg_w )
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READ32_MEMBER( n64_periphs::ri_reg_r )
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{
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if(offset == 0x0C/4) // RI_SELECT
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{
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/* This is to 'simulate' the time that RDRAM initialization
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would take if the RI registers were not set to skip the RDRAM
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testing during device reset. Proper simulation would require
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emulating the RDRAM modules and bus stalls for the mips cpu.
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The cycle amount chosen represents 1/2 second, which is not
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necessarily the time for RDRAM initialization, but rather the
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time recommended for letting the SI devices settle after startup.
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This allows the initialization routines for the SI to see that a
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proper amount of time has passed since system startup. */
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machine().device<mips3_device>("maincpu")->burn_cycles(93750000/2);
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}
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if(offset > 0x1c/4)
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{
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logerror("ri_reg_r: %08X, %08X at %08X\n", offset, mem_mask, maincpu->safe_pc());
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