mirror of
https://github.com/holub/mame
synced 2025-05-14 09:58:14 +03:00
-newport: Various changes. [Ryan Holtz]
* Added support for endian swapping on host data port writes. * Added double-buffer shift support for non-RGB/CI planes. * Fixed Packed Color Fractions register handling.
This commit is contained in:
mooglyguy
MooglyGuy
parent
0936ebf6c3
commit
15baaacf9b
@ -12,18 +12,6 @@
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- XMAP9: Final display generator
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- CMAP: Palette mapper
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- VC2: Video timing controller / CRTC
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Taken from the Linux Newport driver, slave addresses for Newport devices are:
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VC2 0
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Both CMAPs 1
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CMAP 0 2
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CMAP 1 3
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Both XMAPs 4
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XMAP 0 5
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XMAP 1 6
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RAMDAC 7
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VIDEO (CC1) 8
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VIDEO (AB1) 9
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*/
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#include "emu.h"
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@ -36,11 +24,12 @@
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#define LOG_XMAP0 (1 << 4)
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#define LOG_XMAP1 (1 << 5)
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#define LOG_REX3 (1 << 6)
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#define LOG_COMMANDS (1 << 7)
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#define LOG_REJECTS (1 << 8)
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#define LOG_ALL (LOG_UNKNOWN | LOG_VC2 | LOG_CMAP0 | LOG_CMAP1 | LOG_XMAP0 | LOG_XMAP1 | LOG_REX3 | LOG_COMMANDS | LOG_REJECTS)
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#define LOG_RAMDAC (1 << 7)
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#define LOG_COMMANDS (1 << 8)
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#define LOG_REJECTS (1 << 9)
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#define LOG_ALL (LOG_UNKNOWN | LOG_VC2 | LOG_CMAP0 | LOG_CMAP1 | LOG_XMAP0 | LOG_XMAP1 | LOG_REX3 | LOG_RAMDAC | LOG_COMMANDS | LOG_REJECTS)
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#define VERBOSE (0)//(LOG_REX3 | LOG_COMMANDS)
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#define VERBOSE (0)//(LOG_REX3 | LOG_CMAP0 | LOG_CMAP1 | LOG_XMAP0 | LOG_XMAP1)
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#include "logmacro.h"
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DEFINE_DEVICE_TYPE(GIO64_XL8, gio64_xl8_device, "gio64_xl8", "SGI 8-bit XL board")
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@ -350,7 +339,7 @@ uint32_t newport_base_device::screen_update(screen_device &device, bitmap_rgb32
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//uint32_t *src = &m_vt_table[y * 2048];
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uint32_t *src_ci = &m_rgbci[1344 * y];
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uint32_t *src_pup = &m_pup[1344 * y];
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uint32_t *src_olay = &m_pup[1344 * y];
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uint32_t *src_olay = &m_olay[1344 * y];
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m_vc2.m_did_frame_ptr = m_vc2.m_did_entry + (uint16_t)y;
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m_vc2.m_did_line_ptr = m_vc2.m_ram[m_vc2.m_did_frame_ptr];
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@ -469,7 +458,7 @@ uint32_t newport_base_device::screen_update(screen_device &device, bitmap_rgb32
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break;
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case 2: // 8-Bit Overlay
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{
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const uint32_t pix_in = (*src_olay >> 8) & 0xff;
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const uint32_t pix_in = ((*src_olay >> 8) & 0xf) | ((*src_olay >> 12) & 0xf0);
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if (pix_in)
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{
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*dest++ = m_cmap0.m_palette[aux_msb | pix_in];
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@ -749,6 +738,7 @@ void newport_base_device::ramdac_write(uint32_t data)
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switch (m_rex3.m_dcb_reg_select)
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{
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case 0:
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LOGMASKED(LOG_RAMDAC, "RAMDAC LUT index write: %08x\n", data);
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m_ramdac_lut_index = (uint8_t)data;
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break;
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case 1:
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@ -756,6 +746,10 @@ void newport_base_device::ramdac_write(uint32_t data)
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m_ramdac_lut_g[m_ramdac_lut_index] = (uint8_t)(data >> 16) << 8;
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m_ramdac_lut_b[m_ramdac_lut_index] = (uint8_t)(data >> 24) << 0;
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m_ramdac_lut_index++;
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LOGMASKED(LOG_RAMDAC, "RAMDAC LUT entry write: %08x\n", data);
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break;
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default:
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LOGMASKED(LOG_RAMDAC | LOG_UNKNOWN, "Unknown RAMDAC register %02x write: %08x\n", m_rex3.m_dcb_reg_select, data);
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break;
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}
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}
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@ -799,6 +793,26 @@ uint32_t newport_base_device::cmap0_read()
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}
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}
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void newport_base_device::cmap1_write(uint32_t data)
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{
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switch (m_rex3.m_dcb_reg_select)
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{
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case 0x00:
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LOGMASKED(LOG_CMAP1, "CMAP1 Palette Index Write: %04x\n", data & 0xffff);
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m_cmap1.m_palette_idx = (uint16_t)data;
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break;
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case 0x02:
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m_cmap1.m_palette[m_cmap1.m_palette_idx] = data >> 8;
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//if (m_cmap1.m_palette_idx < 0x2000)
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//set_pen_color(m_cmap1.m_palette_idx, rgb_t((uint8_t)(data >> 24), (uint8_t)(data >> 16), (uint8_t)(data >> 8)));
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LOGMASKED(LOG_CMAP1, "CMAP1 Palette Entry %04x Write: %08x\n", m_cmap0.m_palette_idx, data >> 8);
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break;
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default:
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LOGMASKED(LOG_CMAP1 | LOG_UNKNOWN, "Unknown CMAP1 Register %d Write: %08x\n", m_rex3.m_dcb_reg_select, data);
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break;
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}
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}
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uint32_t newport_base_device::cmap1_read()
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{
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switch (m_rex3.m_dcb_reg_select)
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@ -1827,10 +1841,15 @@ READ64_MEMBER(newport_base_device::rex3_r)
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return ret;
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}
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uint32_t newport_base_device::do_endian_swap(uint32_t color)
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{
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return (color >> 24) | (color << 24) | ((color >> 8) & 0x0000ff00) | ((color << 8) & 0x00ff0000);
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}
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uint32_t newport_base_device::get_host_color()
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{
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static const uint32_t s_color_masks[4] = { 0xf, 0xff, 0xfff, 0xffffff };
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const uint32_t color = (uint32_t)(m_rex3.m_host_dataport >> m_rex3.m_host_shift) & s_color_masks[m_rex3.m_hostdepth];
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static const uint32_t s_color_masks[4] = { 0xf, 0xff, 0xfff, 0xffffffff };
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uint32_t color = (uint32_t)(m_rex3.m_host_dataport >> m_rex3.m_host_shift) & s_color_masks[m_rex3.m_hostdepth];
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if (m_rex3.m_rwpacked)
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{
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if ((m_rex3.m_rwdouble && m_rex3.m_host_shift > 0) || m_rex3.m_host_shift > 32)
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@ -1843,33 +1862,47 @@ uint32_t newport_base_device::get_host_color()
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{
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default:
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// No conversion needed
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return color;
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break;
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case 1: // 4bpp -> 8bpp
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return convert_4bpp_bgr_to_8bpp((uint8_t)color);
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color = convert_4bpp_bgr_to_8bpp((uint8_t)color);
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break;
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case 2: // 4bpp -> 12bpp
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return convert_4bpp_bgr_to_12bpp((uint8_t)color);
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color = convert_4bpp_bgr_to_12bpp((uint8_t)color);
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break;
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case 3: // 4bpp -> 24bpp
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return convert_4bpp_bgr_to_24bpp((uint8_t)color);
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color = convert_4bpp_bgr_to_24bpp((uint8_t)color);
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break;
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case 4: // 8bpp -> 4bpp
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return convert_8bpp_bgr_to_4bpp((uint8_t)color);
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color = convert_8bpp_bgr_to_4bpp((uint8_t)color);
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break;
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case 6: // 8bpp -> 12bpp
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return convert_8bpp_bgr_to_12bpp((uint8_t)color);
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color = convert_8bpp_bgr_to_12bpp((uint8_t)color);
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break;
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case 7: // 8bpp -> 24bpp
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return convert_8bpp_bgr_to_24bpp((uint8_t)color);
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color = convert_8bpp_bgr_to_24bpp((uint8_t)color);
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break;
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case 8: // 12bpp -> 4bpp
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return convert_12bpp_bgr_to_4bpp((uint16_t)color);
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color = convert_12bpp_bgr_to_4bpp((uint16_t)color);
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break;
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case 9: // 12bpp -> 8bpp
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return convert_12bpp_bgr_to_8bpp((uint16_t)color);
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color = convert_12bpp_bgr_to_8bpp((uint16_t)color);
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break;
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case 11: // 12bpp -> 24bpp
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return convert_12bpp_bgr_to_24bpp((uint16_t)color);
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color = convert_12bpp_bgr_to_24bpp((uint16_t)color);
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break;
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case 12: // 32bpp -> 4bpp
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return convert_24bpp_bgr_to_4bpp(color);
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color = convert_24bpp_bgr_to_4bpp(color);
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break;
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case 13: // 32bpp -> 8bpp
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return convert_24bpp_bgr_to_8bpp(color);
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color = convert_24bpp_bgr_to_8bpp(color);
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break;
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case 14: // 32bpp -> 12bpp
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return convert_24bpp_bgr_to_12bpp(color);
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color = convert_24bpp_bgr_to_12bpp(color);
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break;
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}
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return color;
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if (BIT(m_rex3.m_draw_mode1, 11))
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color = do_endian_swap(color);
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return color;
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}
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void newport_base_device::write_pixel(uint32_t color)
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@ -3486,7 +3519,49 @@ WRITE64_MEMBER(newport_base_device::rex3_w)
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}
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m_rex3.m_draw_mode1 = data32;
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static const uint32_t s_store_shift[4] = { 4, 0, 12, 0 };
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static const uint32_t s_store_shift[8][4][2] = {
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{ { 0, 0 }, // None, 4bpp, Buffer 0/1
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{ 0, 0 }, // None, 8bpp, Buffer 0/1
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{ 0, 0 }, // None, 12bpp, Buffer 0/1
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{ 0, 0 }, // None, 24bpp, Buffer 0/1 (not valid)
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},
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{ { 0, 0 }, // RGB/CI, 4bpp, Buffer 0/1
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{ 0, 8 }, // RGB/CI, 8bpp, Buffer 0/1
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{ 0, 12 }, // RGB/CI, 12bpp, Buffer 0/1
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{ 0, 0 }, // RGB/CI, 24bpp, Buffer 0/1 (not valid)
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},
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{ { 0, 0 }, // RGBA, 4bpp, Buffer 0/1
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{ 0, 8 }, // RGBA, 8bpp, Buffer 0/1
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{ 0, 12 }, // RGBA, 12bpp, Buffer 0/1
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{ 0, 0 }, // RGBA, 24bpp, Buffer 0/1 (not valid)
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},
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{ { 0, 0 }, // Invalid, 4bpp, Buffer 0/1
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{ 0, 0 }, // Invalid, 8bpp, Buffer 0/1
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{ 0, 0 }, // Invalid, 12bpp, Buffer 0/1
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{ 0, 0 }, // Invalid, 24bpp, Buffer 0/1 (not valid)
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},
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{ { 0, 8 }, // Overlay, 4bpp, Buffer 0/1
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{ 0, 8 }, // Overlay, 8bpp, Buffer 0/1
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{ 0, 8 }, // Overlay, 12bpp, Buffer 0/1
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{ 0, 8 }, // Overlay, 24bpp, Buffer 0/1 (not valid)
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},
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{ { 0, 0 }, // Popup, 4bpp, Buffer 0/1
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{ 0, 8 }, // Popup, 8bpp, Buffer 0/1
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{ 0, 12 }, // Popup, 12bpp, Buffer 0/1
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{ 0, 0 }, // Popup, 24bpp, Buffer 0/1 (not valid)
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},
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{ { 0, 0 }, // CID, 4bpp, Buffer 0/1
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{ 0, 8 }, // CID, 8bpp, Buffer 0/1
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{ 0, 12 }, // CID, 12bpp, Buffer 0/1
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{ 0, 0 }, // CID, 24bpp, Buffer 0/1 (not valid)
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},
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{ { 0, 0 }, // Invalid, 4bpp, Buffer 0/1
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{ 0, 0 }, // Invalid, 8bpp, Buffer 0/1
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{ 0, 0 }, // Invalid, 12bpp, Buffer 0/1
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{ 0, 0 }, // Invalid, 24bpp, Buffer 0/1 (not valid)
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},
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};
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m_rex3.m_plane_enable = m_rex3.m_draw_mode1 & 7;
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m_rex3.m_plane_depth = (m_rex3.m_draw_mode1 >> 3) & 3;
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m_rex3.m_rwpacked = BIT(m_rex3.m_draw_mode1, 7);
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@ -3496,8 +3571,7 @@ WRITE64_MEMBER(newport_base_device::rex3_w)
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m_rex3.m_dfactor = (m_rex3.m_draw_mode1 >> 22) & 7;
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m_rex3.m_logicop = (m_rex3.m_draw_mode1 >> 28) & 15;
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m_rex3.m_store_shift = BIT(m_rex3.m_draw_mode1, 5) ? s_store_shift[m_rex3.m_plane_depth] : 0;
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m_rex3.m_store_shift = s_store_shift[m_rex3.m_plane_enable][m_rex3.m_plane_depth][BIT(m_rex3.m_draw_mode1, 5)];
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m_rex3.m_host_shift = 64 - s_host_shifts[m_rex3.m_hostdepth];
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}
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if (ACCESSING_BITS_0_31)
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@ -3804,11 +3878,25 @@ WRITE64_MEMBER(newport_base_device::rex3_w)
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{
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LOGMASKED(LOG_REX3, "REX3 Red/CI Full State Write: %08x\n", (uint32_t)(data >> 32));
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m_rex3.m_color_red = (int32_t)((data >> 32) & 0xffffff);
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if (m_rex3.m_plane_depth == 2 && !BIT(m_rex3.m_draw_mode1, 15))
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m_rex3.m_curr_color_red = m_rex3.m_color_red;
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if (!BIT(m_rex3.m_draw_mode1, 15))
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{
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m_rex3.m_color_i = m_rex3.m_color_red >> 9;
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switch (m_rex3.m_plane_depth)
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{
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case 0: // 4bpp
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m_rex3.m_color_i = (uint32_t)((data >> 43) & 0xf);
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break;
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case 1: // 8bpp
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m_rex3.m_color_i = (uint32_t)((data >> 43) & 0xff);
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break;
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case 2: // 12bpp
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m_rex3.m_color_i = (uint32_t)((data >> 41) & 0xfff);
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break;
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case 3: // 32bpp
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// Invalid for CI mode
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break;
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}
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}
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m_rex3.m_curr_color_red = m_rex3.m_color_red;
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}
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if (ACCESSING_BITS_0_31)
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{
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@ -3914,8 +4002,18 @@ WRITE64_MEMBER(newport_base_device::rex3_w)
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}
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if (ACCESSING_BITS_0_31)
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{
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LOGMASKED(LOG_REX3, "REX3 Packed Color Fractions Write: %08x\n", (uint32_t)data);
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LOGMASKED(LOG_REX3, "REX3 Packed Color Write: %08x\n", (uint32_t)data);
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m_rex3.m_color_i = (uint32_t)data;
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if (BIT(m_rex3.m_draw_mode1, 15))
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{
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m_rex3.m_color_red = (data & 0xff) << 11;
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m_rex3.m_color_green = (data & 0xff00) << 3;
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m_rex3.m_color_blue = (data & 0xff0000) >> 5;
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m_rex3.m_curr_color_red = m_rex3.m_color_red;
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m_rex3.m_curr_color_green = m_rex3.m_color_green;
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m_rex3.m_curr_color_blue = m_rex3.m_color_blue;
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}
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}
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break;
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case 0x0228/8:
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@ -3986,13 +4084,13 @@ WRITE64_MEMBER(newport_base_device::rex3_w)
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break;
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case DCB_ADDR_CMAP01:
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cmap0_write(data32);
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//cmap1_write(data32);
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cmap1_write(data32);
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break;
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case DCB_ADDR_CMAP0:
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cmap0_write(data32);
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break;
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case DCB_ADDR_CMAP1:
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//cmap1_write(data32);
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cmap1_write(data32);
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break;
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case DCB_ADDR_XMAP01:
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xmap0_write(data32);
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@ -226,6 +226,7 @@ protected:
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uint32_t cmap0_read();
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void cmap0_write(uint32_t data);
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uint32_t cmap1_read();
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void cmap1_write(uint32_t data);
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uint32_t xmap0_read();
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void xmap0_write(uint32_t data);
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uint32_t xmap1_read();
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@ -271,6 +272,8 @@ protected:
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uint32_t convert_8bpp_bgr_to_24bpp_rgb(uint8_t pix_in);
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uint32_t convert_12bpp_bgr_to_24bpp_rgb(uint16_t pix_in);
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uint32_t do_endian_swap(uint32_t color);
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struct bresenham_octant_info_t
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{
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int16_t incrx1;
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@ -311,6 +314,7 @@ protected:
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std::unique_ptr<uint32_t[]> m_cid;
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std::unique_ptr<uint32_t[]> m_vt_table;
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cmap_t m_cmap0;
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cmap_t m_cmap1;
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uint32_t m_global_mask;
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emu_timer *m_dcb_timeout_timer;
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