mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
naomi: Better IRQ isolation [O. Galibert]
This commit is contained in:
Olivier Galibert
parent
b1fa04fbea
commit
165c949747
@ -3069,7 +3069,7 @@ static MACHINE_CONFIG_START( chihiro_base, chihiro_state )
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( chihirogd, chihiro_base )
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MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", "pic", NULL, "maincpu", NULL)
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MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", "pic", NULL, "maincpu", NOOP)
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MACHINE_CONFIG_END
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#define ROM_LOAD16_WORD_SWAP_BIOS(bios,name,offset,length,hash) \
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@ -2498,7 +2498,7 @@ static MACHINE_CONFIG_START( naomi_aw_base, naomi_state )
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MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
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MCFG_SCREEN_UPDATE_DEVICE("powervr2", powervr2_device, screen_update)
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MCFG_PALETTE_LENGTH(0x1000)
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MCFG_POWERVR2_ADD("powervr2")
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MCFG_POWERVR2_ADD("powervr2", WRITE8(dc_state, pvr_irq))
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MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
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@ -2521,7 +2521,7 @@ MACHINE_CONFIG_END
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*/
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static MACHINE_CONFIG_DERIVED( naomi, naomi_base )
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MCFG_NAOMI_ROM_BOARD_ADD("rom_board", "naomibd_eeprom", "maincpu", naomi_g1_irq)
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MCFG_NAOMI_ROM_BOARD_ADD("rom_board", "naomibd_eeprom", "maincpu", WRITE8(dc_state, g1_irq))
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MACHINE_CONFIG_END
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/*
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@ -2529,7 +2529,7 @@ MACHINE_CONFIG_END
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*/
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static MACHINE_CONFIG_DERIVED( naomigd, naomi_base )
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MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", ":pic", "naomibd_eeprom", "maincpu", naomi_g1_irq)
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MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", ":pic", "naomibd_eeprom", "maincpu", WRITE8(dc_state, g1_irq))
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MACHINE_CONFIG_END
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/*
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@ -2537,7 +2537,7 @@ MACHINE_CONFIG_END
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*/
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static MACHINE_CONFIG_DERIVED( naomim1, naomi_base )
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MCFG_NAOMI_M1_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", "maincpu", naomi_g1_irq)
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MCFG_NAOMI_M1_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", "maincpu", WRITE8(dc_state, g1_irq))
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MACHINE_CONFIG_END
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/*
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@ -2545,7 +2545,7 @@ MACHINE_CONFIG_END
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*/
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static MACHINE_CONFIG_DERIVED( naomim2, naomi_base )
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MCFG_NAOMI_M2_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", "maincpu", naomi_g1_irq)
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MCFG_NAOMI_M2_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", "maincpu", WRITE8(dc_state, g1_irq))
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MACHINE_CONFIG_END
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/*
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@ -2553,7 +2553,7 @@ MACHINE_CONFIG_END
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*/
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static MACHINE_CONFIG_DERIVED( naomim4, naomi_base )
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MCFG_NAOMI_M4_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", "maincpu", naomi_g1_irq)
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MCFG_NAOMI_M4_BOARD_ADD("rom_board", ":rom_key", "naomibd_eeprom", "maincpu", WRITE8(dc_state, g1_irq))
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MACHINE_CONFIG_END
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/*
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@ -2600,7 +2600,7 @@ static MACHINE_CONFIG_DERIVED( aw_base, naomi_aw_base )
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MCFG_CPU_MODIFY("maincpu")
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MCFG_CPU_PROGRAM_MAP(aw_map)
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MCFG_MACRONIX_29L001MC_ADD("awflash")
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MCFG_AW_ROM_BOARD_ADD("rom_board", ":rom_key", "maincpu", naomi_g1_irq)
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MCFG_AW_ROM_BOARD_ADD("rom_board", ":rom_key", "maincpu", WRITE8(dc_state, g1_irq))
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( aw1c, aw_base )
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@ -547,7 +547,7 @@ static MACHINE_CONFIG_START( triforce_base, triforce_state )
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( triforcegd, triforce_base )
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MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", "picreturn", NULL, "maincpu", NULL)
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MCFG_NAOMI_GDROM_BOARD_ADD("rom_board", ":gdrom", "picreturn", NULL, "maincpu", NOOP)
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MACHINE_CONFIG_END
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@ -52,7 +52,6 @@ class dc_state : public driver_device
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virtual void machine_start();
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virtual void machine_reset();
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TIMER_CALLBACK_MEMBER(aica_dma_irq);
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TIMER_CALLBACK_MEMBER(pvr_dma_irq);
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TIMER_CALLBACK_MEMBER(ch2_dma_irq);
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TIMER_CALLBACK_MEMBER(yuv_fifo_irq);
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TIMER_CALLBACK_MEMBER(dc_rtc_increment);
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@ -77,6 +76,8 @@ class dc_state : public driver_device
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DECLARE_WRITE64_MEMBER( dc_modem_w );
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DECLARE_READ64_MEMBER( dc_rtc_r );
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DECLARE_WRITE64_MEMBER( dc_rtc_w );
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DECLARE_WRITE8_MEMBER( g1_irq );
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DECLARE_WRITE8_MEMBER( pvr_irq );
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required_device<cpu_device> m_maincpu;
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required_device<cpu_device> m_soundcpu;
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@ -318,29 +319,30 @@ class dc_state : public driver_device
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/* 0x005f8600 - 0x005f8f5c TA_OL_POINTERS (read only) */
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/* ------------- normal interrupts ------------- */
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#define IST_EOR_VIDEO 0x00000001
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#define IST_EOR_ISP 0x00000002
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#define IST_EOR_TSP 0x00000004
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#define IST_VBL_IN 0x00000008
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#define IST_VBL_OUT 0x00000010
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#define IST_HBL_IN 0x00000020
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#define IST_EOXFER_YUV 0x00000040
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#define IST_EOR_VIDEO 0x00000001
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#define IST_EOR_ISP 0x00000002
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#define IST_EOR_TSP 0x00000004
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#define IST_VBL_IN 0x00000008
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#define IST_VBL_OUT 0x00000010
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#define IST_HBL_IN 0x00000020
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#define IST_EOXFER_YUV 0x00000040
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#define IST_EOXFER_OPLST 0x00000080
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#define IST_EOXFER_OPMV 0x00000100
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#define IST_EOXFER_OPMV 0x00000100
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#define IST_EOXFER_TRLST 0x00000200
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#define IST_EOXFER_TRMV 0x00000400
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#define IST_DMA_PVR 0x00000800
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#define IST_DMA_MAPLE 0x00001000
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#define IST_DMA_MAPLEVB 0x00002000
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#define IST_DMA_GDROM 0x00004000
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#define IST_DMA_AICA 0x00008000
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#define IST_DMA_EXT1 0x00010000
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#define IST_DMA_EXT2 0x00020000
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#define IST_DMA_DEV 0x00040000
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#define IST_DMA_CH2 0x00080000
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#define IST_DMA_SORT 0x00100000
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#define IST_G1G2EXTSTAT 0x40000000
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#define IST_ERROR 0x80000000
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#define IST_EOXFER_TRMV 0x00000400
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#define IST_DMA_PVR 0x00000800
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#define IST_DMA_MAPLE 0x00001000
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#define IST_DMA_MAPLEVB 0x00002000
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#define IST_DMA_GDROM 0x00004000
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#define IST_DMA_AICA 0x00008000
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#define IST_DMA_EXT1 0x00010000
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#define IST_DMA_EXT2 0x00020000
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#define IST_DMA_DEV 0x00040000
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#define IST_DMA_CH2 0x00080000
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#define IST_DMA_SORT 0x00100000
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#define IST_EOXFER_PTLST 0x00200000
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#define IST_G1G2EXTSTAT 0x40000000
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#define IST_ERROR 0x80000000
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/* ------------ external interrupts ------------ */
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#define IST_EXT_EXTERNAL 0x00000008
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#define IST_EXT_MODEM 0x00000004
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@ -10,6 +10,8 @@
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#include "cpu/sh4/sh4.h"
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#include "sound/aica.h"
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#include "machine/mie.h"
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#include "machine/naomig1.h"
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#include "video/powervr2.h"
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#define DEBUG_REGISTERS (1)
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@ -81,12 +83,72 @@ TIMER_CALLBACK_MEMBER(dc_state::aica_dma_irq)
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dc_update_interrupt_status();
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}
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void naomi_g1_irq(running_machine &machine)
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WRITE8_MEMBER(dc_state::g1_irq)
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{
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dc_state *state = machine.driver_data<dc_state>();
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switch(data) {
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case naomi_g1_device::DMA_GDROM_IRQ:
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dc_sysctrl_regs[SB_ISTNRM] |= IST_DMA_GDROM;
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break;
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}
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dc_update_interrupt_status();
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}
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state->dc_sysctrl_regs[SB_ISTNRM] |= IST_DMA_GDROM;
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state->dc_update_interrupt_status();
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WRITE8_MEMBER(dc_state::pvr_irq)
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{
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switch(data) {
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case powervr2_device::EOXFER_YUV_IRQ:
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dc_sysctrl_regs[SB_ISTNRM] |= IST_EOXFER_YUV;
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break;
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case powervr2_device::EOXFER_OPLST_IRQ:
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dc_sysctrl_regs[SB_ISTNRM] |= IST_EOXFER_OPLST;
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break;
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case powervr2_device::EOXFER_OPMV_IRQ:
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dc_sysctrl_regs[SB_ISTNRM] |= IST_EOXFER_OPMV;
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break;
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case powervr2_device::EOXFER_TRLST_IRQ:
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dc_sysctrl_regs[SB_ISTNRM] |= IST_EOXFER_TRLST;
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break;
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case powervr2_device::EOXFER_TRMV_IRQ:
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dc_sysctrl_regs[SB_ISTNRM] |= IST_EOXFER_TRMV;
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break;
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case powervr2_device::EOXFER_PTLST_IRQ:
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dc_sysctrl_regs[SB_ISTNRM] |= IST_EOXFER_PTLST;
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break;
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case powervr2_device::VBL_IN_IRQ:
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dc_sysctrl_regs[SB_ISTNRM] |= IST_VBL_IN;
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break;
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case powervr2_device::VBL_OUT_IRQ:
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dc_sysctrl_regs[SB_ISTNRM] |= IST_VBL_OUT;
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break;
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case powervr2_device::HBL_IN_IRQ:
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dc_sysctrl_regs[SB_ISTNRM] |= IST_VBL_IN;
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break;
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case powervr2_device::EOR_VIDEO_IRQ:
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dc_sysctrl_regs[SB_ISTNRM] |= IST_EOR_VIDEO;
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break;
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case powervr2_device::EOR_TSP_IRQ:
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dc_sysctrl_regs[SB_ISTNRM] |= IST_EOR_TSP;
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break;
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case powervr2_device::EOR_ISP_IRQ:
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dc_sysctrl_regs[SB_ISTNRM] |= IST_EOR_ISP;
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break;
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case powervr2_device::DMA_PVR_IRQ:
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dc_sysctrl_regs[SB_ISTNRM] |= IST_DMA_PVR;
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break;
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}
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dc_update_interrupt_status();
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}
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void dc_maple_irq(running_machine &machine)
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@ -24,27 +24,22 @@ DEVICE_ADDRESS_MAP_START(amap, 32, naomi_g1_device)
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ADDRESS_MAP_END
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naomi_g1_device::naomi_g1_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock)
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: device_t(mconfig, type, name, tag, owner, clock)
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: device_t(mconfig, type, name, tag, owner, clock),
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irq_cb(*this)
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{
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cpu = 0;
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}
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void naomi_g1_device::static_set_maincpu_tag(device_t &device, const char *maincpu_tag)
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void naomi_g1_device::set_maincpu_tag(const char *_maincpu_tag)
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{
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naomi_g1_device &naomi_g1 = downcast<naomi_g1_device &>(device);
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naomi_g1.maincpu_tag = maincpu_tag;
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}
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void naomi_g1_device::static_set_irq_cb(device_t &device, void (*irq_cb)(running_machine &))
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{
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naomi_g1_device &naomi_g1 = downcast<naomi_g1_device &>(device);
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naomi_g1.irq_cb = irq_cb;
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maincpu_tag = _maincpu_tag;
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}
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void naomi_g1_device::device_start()
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{
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cpu = machine().device<sh4_device>(maincpu_tag);
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timer = timer_alloc(G1_TIMER_ID);
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irq_cb.resolve_safe();
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save_item(NAME(gdstar));
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save_item(NAME(gdlen));
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@ -68,8 +63,7 @@ void naomi_g1_device::device_timer(emu_timer &timer, device_timer_id id, int par
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if(!gdst)
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return;
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gdst = 0;
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if(irq_cb)
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irq_cb(machine());
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irq_cb(DMA_GDROM_IRQ);
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}
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READ32_MEMBER(naomi_g1_device::sb_gdstar_r)
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@ -2,18 +2,23 @@
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#define _NAOMIG1_H_
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#include "cpu/sh4/sh4.h"
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#include "includes/dc.h"
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#define MCFG_NAOMI_G1_ADD(_tag, type, _maincpu_tag, _irq_cb) \
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MCFG_DEVICE_ADD(_tag, type, 0) \
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naomi_g1_device::static_set_maincpu_tag(*device, _maincpu_tag); \
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naomi_g1_device::static_set_irq_cb(*device, _irq_cb);
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downcast<naomi_g1_device *>(device)->set_maincpu_tag(_maincpu_tag); \
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downcast<naomi_g1_device *>(device)->set_irq_cb(DEVCB2_ ## _irq_cb);
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class naomi_g1_device : public device_t
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{
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public:
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enum {
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DMA_GDROM_IRQ
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};
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naomi_g1_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
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static void static_set_maincpu_tag(device_t &device, const char *maincpu_tag);
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static void static_set_irq_cb(device_t &device, void (*irq_cb)(running_machine &));
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void set_maincpu_tag(const char *maincpu_tag);
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template<class _cb> void set_irq_cb(_cb cb) { irq_cb.set_callback(cb); }
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DECLARE_ADDRESS_MAP(amap, 32);
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@ -59,7 +64,7 @@ private:
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sh4_device *cpu;
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const char *maincpu_tag;
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emu_timer *timer;
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void (*irq_cb)(running_machine &);
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devcb2_write8 irq_cb;
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void dma(void *dma_ptr, UINT32 main_adr, UINT32 size, bool to_mainram);
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};
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@ -124,7 +124,7 @@ SPG_STATUS
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---- ---- ---- ---- ---x ---- ---- ---- hsync
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---- ---- ---- ---- ---- x--- ---- ---- blank
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---- ---- ---- ---- ---- -x-- ---- ---- field number
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---- ---- ---- ---- ---- --xx xxxx xxxx state->scanline
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---- ---- ---- ---- ---- --xx xxxx xxxx scanline
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*/
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@ -832,7 +832,7 @@ void powervr2_device::tex_get_info(texinfo *t)
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static const int mipmap_4_8_offset[8] = { 0x00018, 0x00058, 0x00158, 0x00558, 0x01558, 0x05558, 0x15558, 0x55558 }; // 4bpp (4bit offset) / 8bpp (8bit offset)
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static const int mipmap_np_offset[8] = { 0x00030, 0x000B0, 0x002B0, 0x00AB0, 0x02AB0, 0x0AAB0, 0x2AAB0, 0xAAAB0 }; // nonpalette textures
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static const int mipmap_vq_offset[8] = { 0x00006, 0x00016, 0x00056, 0x00156, 0x00556, 0x01556, 0x05556, 0x15556 }; // vq textures
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static const int mipmap_vq_offset[8] = { 0x00006, 0x00016, 0x00056, 0x00156, 0x00556, 0x01556, 0x05556, 0x15556 }; // vq textures
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switch (miptype)
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{
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@ -1106,8 +1106,7 @@ WRITE32_MEMBER( powervr2_device::pvr_ta_w )
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printf("TA_YUV_TEX_BASE initialized to %08x\n", data);
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// hack, this interrupt is generated after transfering a set amount of data
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//state->state->dc_sysctrl_regs[SB_ISTNRM] |= IST_EOXFER_YUV;
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//state->state->dc_update_interrupt_status();
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//irq_cb(EOXFER_YUV_IRQ);
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break;
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case TA_YUV_TEX_CTRL:
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@ -1160,37 +1159,27 @@ WRITE32_MEMBER( powervr2_device::pvr_ta_w )
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TIMER_CALLBACK_MEMBER(powervr2_device::transfer_opaque_list_irq)
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{
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dc_state *state = machine().driver_data<dc_state>();
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state->dc_sysctrl_regs[SB_ISTNRM] |= IST_EOXFER_OPLST;
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state->dc_update_interrupt_status();
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irq_cb(EOXFER_OPLST_IRQ);
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}
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TIMER_CALLBACK_MEMBER(powervr2_device::transfer_opaque_modifier_volume_list_irq)
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{
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dc_state *state = machine().driver_data<dc_state>();
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state->dc_sysctrl_regs[SB_ISTNRM] |= IST_EOXFER_OPMV;
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state->dc_update_interrupt_status();
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irq_cb(EOXFER_OPMV_IRQ);
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}
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TIMER_CALLBACK_MEMBER(powervr2_device::transfer_translucent_list_irq)
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{
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dc_state *state = machine().driver_data<dc_state>();
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state->dc_sysctrl_regs[SB_ISTNRM] |= IST_EOXFER_TRLST;
|
||||
state->dc_update_interrupt_status();
|
||||
irq_cb(EOXFER_TRLST_IRQ);
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(powervr2_device::transfer_translucent_modifier_volume_list_irq)
|
||||
{
|
||||
dc_state *state = machine().driver_data<dc_state>();
|
||||
state->dc_sysctrl_regs[SB_ISTNRM] |= IST_EOXFER_TRMV;
|
||||
state->dc_update_interrupt_status();
|
||||
irq_cb(EOXFER_TRMV_IRQ);
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(powervr2_device::transfer_punch_through_list_irq)
|
||||
{
|
||||
dc_state *state = machine().driver_data<dc_state>();
|
||||
state->dc_sysctrl_regs[SB_ISTNRM] |= (1 << 21);
|
||||
state->dc_update_interrupt_status();
|
||||
irq_cb(EOXFER_PTLST_IRQ);
|
||||
}
|
||||
|
||||
void powervr2_device::process_ta_fifo()
|
||||
@ -1511,16 +1500,6 @@ WRITE64_MEMBER( powervr2_device::ta_fifo_poly_w )
|
||||
|
||||
WRITE64_MEMBER( powervr2_device::ta_fifo_yuv_w )
|
||||
{
|
||||
//dc_state *state = space.machine().driver_data<dc_state>();
|
||||
|
||||
// int reg;
|
||||
// UINT64 shift;
|
||||
// UINT32 dat;
|
||||
|
||||
// reg = decode_reg_64(offset, mem_mask, &shift);
|
||||
// dat = (UINT32)(data >> shift);
|
||||
|
||||
// printf("YUV FIFO: [%08x=%x] write %" I64FMT "x to %x, mask %" I64FMT "x %08x\n", 0x10800000+reg*4, dat, data, offset, mem_mask,test);
|
||||
}
|
||||
|
||||
// SB_LMMODE0
|
||||
@ -2376,18 +2355,14 @@ void powervr2_device::pvr_build_parameterconfig()
|
||||
|
||||
TIMER_CALLBACK_MEMBER(powervr2_device::vbin)
|
||||
{
|
||||
dc_state *state = machine().driver_data<dc_state>();
|
||||
state->dc_sysctrl_regs[SB_ISTNRM] |= IST_VBL_IN; // V Blank-in interrupt
|
||||
state->dc_update_interrupt_status();
|
||||
irq_cb(VBL_IN_IRQ);
|
||||
|
||||
vbin_timer->adjust(machine().primary_screen->time_until_pos(spg_vblank_in_irq_line_num));
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(powervr2_device::vbout)
|
||||
{
|
||||
dc_state *state = machine().driver_data<dc_state>();
|
||||
state->dc_sysctrl_regs[SB_ISTNRM] |= IST_VBL_OUT; // V Blank-out interrupt
|
||||
state->dc_update_interrupt_status();
|
||||
irq_cb(VBL_OUT_IRQ);
|
||||
|
||||
vbout_timer->adjust(machine().primary_screen->time_until_pos(spg_vblank_out_irq_line_num));
|
||||
}
|
||||
@ -2398,17 +2373,13 @@ TIMER_CALLBACK_MEMBER(powervr2_device::hbin)
|
||||
{
|
||||
if(scanline == next_y)
|
||||
{
|
||||
dc_state *state = machine().driver_data<dc_state>();
|
||||
state->dc_sysctrl_regs[SB_ISTNRM] |= IST_HBL_IN; // H Blank-in interrupt
|
||||
state->dc_update_interrupt_status();
|
||||
irq_cb(HBL_IN_IRQ);
|
||||
next_y+=spg_line_comp_val;
|
||||
}
|
||||
}
|
||||
else if((scanline == spg_line_comp_val) || (spg_hblank_int_mode & 2))
|
||||
{
|
||||
dc_state *state = machine().driver_data<dc_state>();
|
||||
state->dc_sysctrl_regs[SB_ISTNRM] |= IST_HBL_IN; // H Blank-in interrupt
|
||||
state->dc_update_interrupt_status();
|
||||
irq_cb(HBL_IN_IRQ);
|
||||
}
|
||||
|
||||
// printf("hbin on scanline %d\n",scanline);
|
||||
@ -2428,17 +2399,13 @@ TIMER_CALLBACK_MEMBER(powervr2_device::hbin)
|
||||
|
||||
TIMER_CALLBACK_MEMBER(powervr2_device::endofrender_video)
|
||||
{
|
||||
dc_state *state = machine().driver_data<dc_state>();
|
||||
state->dc_sysctrl_regs[SB_ISTNRM] |= IST_EOR_VIDEO;// VIDEO end of render
|
||||
state->dc_update_interrupt_status();
|
||||
irq_cb(EOR_VIDEO_IRQ); // VIDEO end of render
|
||||
endofrender_timer_video->adjust(attotime::never);
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(powervr2_device::endofrender_tsp)
|
||||
{
|
||||
dc_state *state = machine().driver_data<dc_state>();
|
||||
state->dc_sysctrl_regs[SB_ISTNRM] |= IST_EOR_TSP; // TSP end of render
|
||||
state->dc_update_interrupt_status();
|
||||
{
|
||||
irq_cb(EOR_TSP_IRQ); // TSP end of render
|
||||
|
||||
endofrender_timer_tsp->adjust(attotime::never);
|
||||
endofrender_timer_video->adjust(attotime::from_usec(500) );
|
||||
@ -2446,9 +2413,7 @@ TIMER_CALLBACK_MEMBER(powervr2_device::endofrender_tsp)
|
||||
|
||||
TIMER_CALLBACK_MEMBER(powervr2_device::endofrender_isp)
|
||||
{
|
||||
dc_state *state = machine().driver_data<dc_state>();
|
||||
state->dc_sysctrl_regs[SB_ISTNRM] |= IST_EOR_ISP; // ISP end of render
|
||||
state->dc_update_interrupt_status();
|
||||
irq_cb(EOR_ISP_IRQ); // ISP end of render
|
||||
|
||||
endofrender_timer_isp->adjust(attotime::never);
|
||||
endofrender_timer_tsp->adjust(attotime::from_usec(500) );
|
||||
@ -2574,10 +2539,8 @@ WRITE32_MEMBER( powervr2_device::pvrs_ta_w )
|
||||
|
||||
TIMER_CALLBACK_MEMBER(powervr2_device::pvr_dma_irq)
|
||||
{
|
||||
dc_state *state = machine().driver_data<dc_state>();
|
||||
m_pvr_dma.start = pvrctrl_regs[SB_PDST] = 0;
|
||||
state->dc_sysctrl_regs[SB_ISTNRM] |= IST_DMA_PVR;
|
||||
state->dc_update_interrupt_status();
|
||||
irq_cb(DMA_PVR_IRQ);
|
||||
}
|
||||
|
||||
READ32_MEMBER(powervr2_device::pvr_ctrl_r)
|
||||
@ -2660,12 +2623,15 @@ void powervr2_device::pvr_dma_execute(address_space &space)
|
||||
}
|
||||
|
||||
powervr2_device::powervr2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
|
||||
: device_t(mconfig, POWERVR2, "PowerVR 2", tag, owner, clock)
|
||||
: device_t(mconfig, POWERVR2, "PowerVR 2", tag, owner, clock),
|
||||
irq_cb(*this)
|
||||
{
|
||||
}
|
||||
|
||||
void powervr2_device::device_start()
|
||||
{
|
||||
irq_cb.resolve_safe();
|
||||
|
||||
memset(pvrctrl_regs, 0, sizeof(pvrctrl_regs));
|
||||
memset(pvrta_regs, 0, sizeof(pvrta_regs));
|
||||
memset(grab, 0, sizeof(grab));
|
||||
|
||||
@ -1,13 +1,29 @@
|
||||
#ifndef __POWERVR2_H__
|
||||
#define __POWERVR2_H__
|
||||
|
||||
#define MCFG_POWERVR2_ADD(_tag) \
|
||||
MCFG_DEVICE_ADD(_tag, POWERVR2, 0)
|
||||
#define MCFG_POWERVR2_ADD(_tag, _irq_cb) \
|
||||
MCFG_DEVICE_ADD(_tag, POWERVR2, 0) \
|
||||
downcast<powervr2_device *>(device)->set_irq_cb(DEVCB2_ ## _irq_cb);
|
||||
|
||||
class powervr2_device : public device_t
|
||||
{
|
||||
public:
|
||||
enum { NUM_BUFFERS = 4 };
|
||||
enum {
|
||||
EOXFER_YUV_IRQ,
|
||||
EOXFER_OPLST_IRQ,
|
||||
EOXFER_OPMV_IRQ,
|
||||
EOXFER_TRLST_IRQ,
|
||||
EOXFER_TRMV_IRQ,
|
||||
EOXFER_PTLST_IRQ,
|
||||
VBL_IN_IRQ,
|
||||
VBL_OUT_IRQ,
|
||||
HBL_IN_IRQ,
|
||||
EOR_VIDEO_IRQ,
|
||||
EOR_TSP_IRQ,
|
||||
EOR_ISP_IRQ,
|
||||
DMA_PVR_IRQ
|
||||
};
|
||||
|
||||
struct {
|
||||
UINT32 pvr_addr;
|
||||
@ -110,6 +126,7 @@ public:
|
||||
int next_y;
|
||||
|
||||
powervr2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
template<class _cb> void set_irq_cb(_cb cb) { irq_cb.set_callback(cb); }
|
||||
|
||||
DECLARE_READ32_MEMBER( pvr_ctrl_r );
|
||||
DECLARE_WRITE32_MEMBER( pvr_ctrl_w );
|
||||
@ -147,6 +164,8 @@ protected:
|
||||
virtual void device_reset();
|
||||
|
||||
private:
|
||||
devcb2_write8 irq_cb;
|
||||
|
||||
static UINT32 (*const blend_functions[64])(UINT32 s, UINT32 d);
|
||||
|
||||
static inline INT32 clamp(INT32 in, INT32 min, INT32 max);
|
||||
|
||||
@ -206,7 +206,7 @@ static MACHINE_CONFIG_START( dc, dc_cons_state )
|
||||
MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
|
||||
MCFG_SCREEN_UPDATE_DEVICE("powervr2", powervr2_device, screen_update)
|
||||
MCFG_PALETTE_LENGTH(0x1000)
|
||||
MCFG_POWERVR2_ADD("powervr2")
|
||||
MCFG_POWERVR2_ADD("powervr2", WRITE8(dc_state, pvr_irq))
|
||||
|
||||
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
|
||||
MCFG_SOUND_ADD("aica", AICA, 0)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user