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vt61_cpu: Some registers for later (nw)

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This commit is contained in:
AJR 2020-01-14 12:48:10 -05:00
parent 7b84518047
commit 16b5162af2
2 changed files with 21 additions and 2 deletions
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13
src/devices/cpu/vt61/vt61.cpp
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@ -30,6 +30,9 @@ vt61_cpu_device::vt61_cpu_device(const machine_config &mconfig, const char *tag,
, m_ir(0) , m_ir(0)
, m_sp{0} , m_sp{0}
, m_icount(0) , m_icount(0)
, m_misc_flags(0)
, m_modem_flags(0)
, m_intrpt_control(0)
{ {
m_program_config.m_is_octal = true; m_program_config.m_is_octal = true;
m_memory_config.m_is_octal = true; m_memory_config.m_is_octal = true;
@ -75,6 +78,9 @@ void vt61_cpu_device::device_start()
state_add(VT61_IR, "IR", m_ir).mask(6); state_add(VT61_IR, "IR", m_ir).mask(6);
for (int i = 0; i < 16; i++) for (int i = 0; i < 16; i++)
state_add(VT61_R0 + i, string_format("R%d", i).c_str(), m_sp[i]).formatstr("%03O"); state_add(VT61_R0 + i, string_format("R%d", i).c_str(), m_sp[i]).formatstr("%03O");
state_add(VT61_MISC, "MISC", m_misc_flags).formatstr("%03O");
state_add(VT61_MOD, "MOD", m_modem_flags).formatstr("%02O").mask(017);
state_add(VT61_INTRC, "INTRC", m_intrpt_control).formatstr("%02O").mask(017);
save_item(NAME(m_pc)); save_item(NAME(m_pc));
save_item(NAME(m_ac)); save_item(NAME(m_ac));
@ -82,11 +88,18 @@ void vt61_cpu_device::device_start()
save_item(NAME(m_mdr)); save_item(NAME(m_mdr));
save_item(NAME(m_ir)); save_item(NAME(m_ir));
save_item(NAME(m_sp)); save_item(NAME(m_sp));
save_item(NAME(m_misc_flags));
save_item(NAME(m_modem_flags));
save_item(NAME(m_intrpt_control));
} }
void vt61_cpu_device::device_reset() void vt61_cpu_device::device_reset()
{ {
m_pc = 0; m_pc = 0;
m_misc_flags = 0;
m_modem_flags = 0;
m_intrpt_control = 0;
} }
void vt61_cpu_device::execute_run() void vt61_cpu_device::execute_run()

10
src/devices/cpu/vt61/vt61.h
View File

@ -18,7 +18,8 @@ public:
VT61_R0, VT61_R1, VT61_R2, VT61_R3, VT61_R0, VT61_R1, VT61_R2, VT61_R3,
VT61_R4, VT61_R5, VT61_R6, VT61_R7, VT61_R4, VT61_R5, VT61_R6, VT61_R7,
VT61_R8, VT61_R9, VT61_R10, VT61_R11, VT61_R8, VT61_R9, VT61_R10, VT61_R11,
VT61_R12, VT61_R13, VT61_R14, VT61_R15 VT61_R12, VT61_R13, VT61_R14, VT61_R15,
VT61_MISC, VT61_MOD, VT61_INTRC
}; };
enum { enum {
@ -54,7 +55,7 @@ private:
memory_access_cache<0, 0, ENDIANNESS_LITTLE> *m_memory_cache; memory_access_cache<0, 0, ENDIANNESS_LITTLE> *m_memory_cache;
memory_access_cache<0, 0, ENDIANNESS_LITTLE> *m_idr_cache; memory_access_cache<0, 0, ENDIANNESS_LITTLE> *m_idr_cache;
// internal state // processor state
u16 m_pc; u16 m_pc;
u8 m_ac; u8 m_ac;
u16 m_mar; u16 m_mar;
@ -62,6 +63,11 @@ private:
u8 m_ir; u8 m_ir;
u8 m_sp[16]; // scratchpad memory u8 m_sp[16]; // scratchpad memory
s32 m_icount; s32 m_icount;
// I/O registers
u8 m_misc_flags;
u8 m_modem_flags;
u8 m_intrpt_control;
}; };
DECLARE_DEVICE_TYPE(VT61_CPU, vt61_cpu_device) DECLARE_DEVICE_TYPE(VT61_CPU, vt61_cpu_device)