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XaviX: fixes to allow ttv_sw to show graphics, and ttv_lotr to play music on title (#4302)

Browse Source 
* xavix fixes (nw)

* fix2 (nw)

* more (nw)

* more fixes (nw)
This commit is contained in:
David Haywood 2018-11-15 23:48:13 +00:00 committed by ajrhacker
parent e7f93e5af7
commit 1777d0cbb1
10 changed files with 339 additions and 181 deletions
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18
src/devices/cpu/m6502/dxavix.lst
View File

@ -1,20 +1,20 @@
# license:BSD-3-Clause
# copyright-holders:David Haywood
# xavix - m6502 with custom opcodes
brk_xav_imp ora_idx kil_non slo_idx nop_zpg ora_zpg asl_zpg slo_zpg php_imp ora_imm asl_acc anc_imm nop_aba ora_aba asl_aba slo_aba
brk_xav_imp xavora_idx kil_non slo_idx nop_zpg ora_zpg asl_zpg slo_zpg php_imp ora_imm asl_acc anc_imm nop_aba ora_aba asl_aba slo_aba
bpl_rel xavora_idy kil_non slo_idy nop_zpx ora_zpx asl_zpx slo_zpx clc_imp ora_aby nop_imp slo_aby nop_abx ora_abx asl_abx slo_abx
jsr_adr and_idx callf_xa3 rla_idx bit_zpg and_zpg rol_zpg rla_zpg plp_imp and_imm rol_acc anc_imm bit_aba and_aba rol_aba rla_aba
jsr_adr xavand_idx callf_xa3 rla_idx bit_zpg and_zpg rol_zpg rla_zpg plp_imp and_imm rol_acc anc_imm bit_aba and_aba rol_aba rla_aba
bmi_rel xavand_idy kil_non rla_idy nop_zpx and_zpx rol_zpx rla_zpx sec_imp and_aby nop_imp rla_aby nop_abx and_abx rol_abx rla_abx
rti_xav_imp eor_idx kil_non sre_idx nop_zpg eor_zpg lsr_zpg sre_zpg pha_imp eor_imm lsr_acc asr_imm jmp_adr eor_aba lsr_aba sre_aba
rti_xav_imp xaveor_idx kil_non sre_idx nop_zpg eor_zpg lsr_zpg sre_zpg pha_imp eor_imm lsr_acc asr_imm jmp_adr eor_aba lsr_aba sre_aba
bvc_rel xaveor_idy kil_non sre_idy nop_zpx eor_zpx lsr_zpx sre_zpx cli_imp eor_aby nop_imp sre_aby nop_abx eor_abx lsr_abx sre_abx
rts_imp adc_idx kil_non rra_idx nop_zpg adc_zpg ror_zpg rra_zpg pla_imp adc_imm ror_acc arr_imm jmp_ind adc_aba ror_aba rra_aba
rts_imp xavadc_idx kil_non rra_idx nop_zpg adc_zpg ror_zpg rra_zpg pla_imp adc_imm ror_acc arr_imm jmp_ind adc_aba ror_aba rra_aba
bvs_rel xavadc_idy kil_non rra_idy nop_zpx adc_zpx ror_zpx rra_zpx sei_imp adc_aby nop_imp rra_aby nop_abx adc_abx ror_abx rra_abx
retf_imp sta_idx nop_imm sax_idx sty_zpg sta_zpg stx_zpg sax_zpg dey_imp nop_imm txa_imp ane_imm sty_aba sta_aba stx_aba sax_aba
bcc_rel sta_idy kil_non sha_idy sty_zpx sta_zpx stx_zpy sax_zpy tya_imp sta_aby txs_imp shs_aby shy_abx sta_abx shx_aby sha_aby
ldy_imm lda_idx ldx_imm lax_idx ldy_zpg lda_zpg ldx_zpg lax_zpg tay_imp lda_imm tax_imp lxa_imm ldy_aba lda_aba ldx_aba lax_aba
retf_imp xavsta_idx nop_imm sax_idx sty_zpg sta_zpg stx_zpg sax_zpg dey_imp nop_imm txa_imp ane_imm sty_aba sta_aba stx_aba sax_aba
bcc_rel xavsta_idy kil_non sha_idy sty_zpx sta_zpx stx_zpy sax_zpy tya_imp sta_aby txs_imp shs_aby shy_abx sta_abx shx_aby sha_aby
ldy_imm xavlda_idx ldx_imm lax_idx ldy_zpg lda_zpg ldx_zpg lax_zpg tay_imp lda_imm tax_imp lxa_imm ldy_aba lda_aba ldx_aba lax_aba
bcs_rel xavlda_idy kil_non lax_idy ldy_zpx lda_zpx ldx_zpy lax_zpy clv_imp lda_aby tsx_imp las_aby ldy_abx lda_abx ldx_aby lax_aby
cpy_imm cmp_idx nop_imm dcp_idx cpy_zpg cmp_zpg dec_zpg dcp_zpg iny_imp cmp_imm dex_imp sbx_imm cpy_aba cmp_aba dec_aba dcp_aba
cpy_imm xavcmp_idx nop_imm dcp_idx cpy_zpg cmp_zpg dec_zpg dcp_zpg iny_imp cmp_imm dex_imp sbx_imm cpy_aba cmp_aba dec_aba dcp_aba
bne_rel xavcmp_idy kil_non dcp_idy nop_zpx cmp_zpx dec_zpx dcp_zpx cld_imp cmp_aby nop_imp dcp_aby nop_abx cmp_abx dec_abx dcp_abx
cpx_imm sbc_idx nop_imm isb_idx cpx_zpg sbc_zpg inc_zpg isb_zpg inx_imp sbc_imm nop_imp sbc_imm cpx_aba sbc_aba inc_aba isb_aba
cpx_imm xavsbc_idx nop_imm isb_idx cpx_zpg sbc_zpg inc_zpg isb_zpg inx_imp sbc_imm nop_imp sbc_imm cpx_aba sbc_aba inc_aba isb_aba
beq_rel xavsbc_idy kil_non isb_idy nop_zpx sbc_zpx inc_zpx isb_zpx sed_imp sbc_aby nop_imp isb_aby nop_abx sbc_abx inc_abx isb_abx
reset

32
src/devices/cpu/m6502/dxavix2000.lst
View File

@ -1,20 +1,20 @@
# license:BSD-3-Clause
# copyright-holders:David Haywood
# Super XaviX (SSD 2000) - m6502 with custom opcodes
brk_xav_imp ora_idx cmc_imp oral0_acc asr_zpg ora_zpg asl_zpg oral1_acc php_imp ora_imm asl_acc oral2_acc asr_aba ora_aba asl_aba oral3_acc
bpl_rel xavora_idy phx_imp orapa_imp asr_zpx ora_zpx asl_zpx orapb_imp clc_imp ora_aby asr_acc spa0_acc asr_abx ora_abx asl_abx spb0_acc
jsr_adr and_idx callf_xa3 andl0_acc bit_zpg and_zpg rol_zpg andl1_acc plp_imp and_imm rol_acc andl2_acc bit_aba and_aba rol_aba andl3_acc
bmi_rel xavand_idy plx_imp andpa_imp bit_zpx and_zpx rol_zpx andpb_imp sec_imp and_aby bit_imm lpa0_acc bit_abx and_abx rol_abx lpb0_acc
rti_xav_imp eor_idx nop_imp eorl0_acc nop_imp eor_zpg lsr_zpg eorl1_acc pha_imp eor_imm lsr_acc eorl2_acc jmp_adr eor_aba lsr_aba eorl3_acc
bvc_rel xaveor_idy phy_imp eorpa_imp nop_imp eor_zpx lsr_zpx eorpb_imp cli_imp eor_aby nop_imp spa1_acc callf_aba eor_abx lsr_abx spb1_acc
rts_imp adc_idx nop_imp adcl0_acc nop_imp adc_zpg ror_zpg adcl1_acc pla_imp adc_imm ror_acc adcl2_acc jmp_ind adc_aba ror_aba adcl3_acc
bvs_rel xavadc_idy ply_imp adcpa_imp nop_imp adc_zpx ror_zpx adcpb_imp sei_imp adc_aby nop_imp lpa1_acc jmpf_ind adc_abx ror_abx lpb1_acc
retf_imp sta_idx stz_zpg stal0_acc sty_zpg sta_zpg stx_zpg stal1_acc dey_imp sev_imp txa_imp stal2_acc sty_aba sta_aba stx_aba stal3_acc
bcc_rel sta_idy stz_aba stapa_imp sty_zpx sta_zpx stx_zpy stapb_imp tya_imp sta_aby txs_imp spa2_acc sty_abx sta_abx stx_aby spb2_acc
ldy_imm lda_idx ldx_imm ldal0_acc ldy_zpg lda_zpg ldx_zpg ldal1_acc tay_imp lda_imm tax_imp ldal2_acc ldy_aba lda_aba ldx_aba ldal3_acc
bcs_rel xavlda_idy clr_acc ldapa_imp ldy_zpx lda_zpx ldx_zpy ldapb_imp clv_imp lda_aby tsx_imp lpa2_acc ldy_abx lda_abx ldx_aby lpb2_acc
cpy_imm cmp_idx dec_acc cmpl0_acc cpy_zpg cmp_zpg dec_zpg cmpl1_acc iny_imp cmp_imm dex_imp cmpl2_acc cpy_aba cmp_aba dec_aba cmpl3_acc
bne_rel xavcmp_idy not_acc cmppa_imp nop_imp cmp_zpx dec_zpx cmppb_imp cld_imp cmp_aby nop_imp decpa_imp nop_imp cmp_abx dec_abx decpb_imp
cpx_imm sbc_idx inc_acc sbcl0_acc cpx_zpg sbc_zpg inc_zpg sbcl1_acc inx_imp sbc_imm nop_imp sbcl2_acc cpx_aba sbc_aba inc_aba sbcl3_acc
beq_rel xavsbc_idy neg_acc sbcpa_imp nop_imp sbc_zpx inc_zpx sbcpb_imp sed_imp sbc_aby nop_imp incpa_imp nop_imp sbc_abx inc_abx incpb_imp
brk_xav_imp xavora_idx cmc_imp oraj_imp asr_zpg ora_zpg asl_zpg orak_imp php_imp ora_imm asl_acc oral_imp asr_aba ora_aba asl_aba oram_imp
bpl_rel xavora_idy phx_imp orapa_imp asr_zpx ora_zpx asl_zpx orapb_imp clc_imp ora_aby asr_acc spa0_imp asr_abx ora_abx asl_abx spb0_imp
jsr_adr xavand_idx callf_xa3 andj_imp bit_zpg and_zpg rol_zpg andk_imp plp_imp and_imm rol_acc andl_imp bit_aba and_aba rol_aba andm_imp
bmi_rel xavand_idy plx_imp andpa_imp bit_zpx and_zpx rol_zpx andpb_imp sec_imp and_aby bit_imm lpa0_imp bit_abx and_abx rol_abx lpb0_imp
rti_xav_imp xaveor_idx nop_imp eorj_imp nop_imp eor_zpg lsr_zpg eork_imp pha_imp eor_imm lsr_acc eorl_imp jmp_adr eor_aba lsr_aba eorm_imp
bvc_rel xaveor_idy phy_imp eorpa_imp nop_imp eor_zpx lsr_zpx eorpb_imp cli_imp eor_aby nop_imp spa1_imp callf_aba eor_abx lsr_abx spb1_imp
rts_imp xavadc_idx nop_imp adcj_imp nop_imp adc_zpg ror_zpg adck_imp pla_imp adc_imm ror_acc adcl_imp jmp_ind adc_aba ror_aba adcm_imp
bvs_rel xavadc_idy ply_imp adcpa_imp nop_imp adc_zpx ror_zpx adcpb_imp sei_imp adc_aby nop_imp lpa1_imp jmpf_ind adc_abx ror_abx lpb1_imp
retf_imp xavsta_idx stz_zpg staj_imp sty_zpg sta_zpg stx_zpg stak_imp dey_imp sev_imp txa_imp stal_imp sty_aba sta_aba stx_aba stam_imp
bcc_rel xavsta_idy stz_aba stapa_imp sty_zpx sta_zpx stx_zpy stapb_imp tya_imp sta_aby txs_imp spa2_imp sty_abx sta_abx stx_aby spb2_imp
ldy_imm xavlda_idx ldx_imm ldaj_imp ldy_zpg lda_zpg ldx_zpg ldak_imp tay_imp lda_imm tax_imp ldal_imp ldy_aba lda_aba ldx_aba ldam_imp
bcs_rel xavlda_idy clr_acc ldapa_imp ldy_zpx lda_zpx ldx_zpy ldapb_imp clv_imp lda_aby tsx_imp lpa2_imp ldy_abx lda_abx ldx_aby lpb2_imp
cpy_imm xavcmp_idx dec_acc cmpj_imp cpy_zpg cmp_zpg dec_zpg cmpk_imp iny_imp cmp_imm dex_imp cmpl_imp cpy_aba cmp_aba dec_aba cmpm_imp
bne_rel xavcmp_idy not_acc cmppa_imp nop_imp cmp_zpx dec_zpx cmppb_imp cld_imp cmp_aby nop_imp decpa_imp nop_imp cmp_abx dec_abx decpb_imp
cpx_imm xavsbc_idx inc_acc sbcj_imp cpx_zpg sbc_zpg inc_zpg sbck_imp inx_imp sbc_imm nop_imp sbcl_imp cpx_aba sbc_aba inc_aba sbcm_imp
beq_rel xavsbc_idy neg_acc sbcpa_imp nop_imp sbc_zpx inc_zpx sbcpb_imp sed_imp sbc_aby nop_imp incpa_imp nop_imp sbc_abx inc_abx incpb_imp
reset

83
src/devices/cpu/m6502/oxavix.lst
View File

@ -187,3 +187,86 @@ xavora_idy
set_nz(A);
prefetch();
xavora_idx
TMP2 = read_pc();
read(TMP2);
TMP2 += X;
TMP = read(TMP2 & 0xff);
TMP = set_h(TMP, read((TMP2+1) & 0xff));
A |= read_special(TMP);
set_nz(A);
prefetch();
xavand_idx
TMP2 = read_pc();
read(TMP2);
TMP2 += X;
TMP = read(TMP2 & 0xff);
TMP = set_h(TMP, read((TMP2+1) & 0xff));
A &= read_special(TMP);
set_nz(A);
prefetch();
xaveor_idx
TMP2 = read_pc();
read(TMP2);
TMP2 += X;
TMP = read(TMP2 & 0xff);
TMP = set_h(TMP, read((TMP2+1) & 0xff));
A ^= read_special(TMP);
set_nz(A);
prefetch();
xavadc_idx
TMP2 = read_pc();
read(TMP2);
TMP2 += X;
TMP = read(TMP2 & 0xff);
TMP = set_h(TMP, read((TMP2+1) & 0xff));
do_adc(read_special(TMP));
prefetch();
xavlda_idx
TMP2 = read_pc();
read(TMP2);
TMP2 += X;
TMP = read(TMP2 & 0xff);
TMP = set_h(TMP, read((TMP2+1) & 0xff));
A = read_special(TMP);
set_nz(A);
prefetch();
xavcmp_idx
TMP2 = read_pc();
read(TMP2);
TMP2 += X;
TMP = read(TMP2 & 0xff);
TMP = set_h(TMP, read((TMP2+1) & 0xff));
do_cmp(A, read_special(TMP));
prefetch();
xavsbc_idx
TMP2 = read_pc();
read(TMP2);
TMP2 += X;
TMP = read(TMP2 & 0xff);
TMP = set_h(TMP, read((TMP2+1) & 0xff));
do_sbc(read_special(TMP));
prefetch();
xavsta_idy
TMP2 = read_pc();
TMP = read(TMP2);
TMP = set_h(TMP, read((TMP2+1) & 0xff));
read(set_l(TMP, TMP+Y));
write(TMP+Y, A); // TODO
prefetch();
xavsta_idx
TMP2 = read_pc();
read(TMP2);
TMP2 += X;
TMP = read(TMP2 & 0xff);
TMP = set_h(TMP, read((TMP2+1) & 0xff));
write(TMP, A); // TODO
prefetch();

223
src/devices/cpu/m6502/oxavix2000.lst
View File

@ -60,249 +60,259 @@ neg_acc
set_nz(A);
prefetch();
oral0_acc
fatalerror("unhandled opcode %02x%04x: %02x\n", m_codebank, PPC, inst_state);
oraj_imp
read_pc_noinc();
prefetch();
oral1_acc
read_pc_noinc();
A |= (m_l & 0x0000ff00) >> 8;
A |= m_j;
set_nz(A);
prefetch();
oral2_acc
fatalerror("unhandled opcode %02x%04x: %02x\n", m_codebank, PPC, inst_state);
orak_imp
read_pc_noinc();
prefetch();
oral3_acc
fatalerror("unhandled opcode %02x%04x: %02x\n", m_codebank, PPC, inst_state);
read_pc_noinc();
prefetch();
andl0_acc
fatalerror("unhandled opcode %02x%04x: %02x\n", m_codebank, PPC, inst_state);
read_pc_noinc();
prefetch();
andl1_acc
fatalerror("unhandled opcode %02x%04x: %02x\n", m_codebank, PPC, inst_state);
read_pc_noinc();
prefetch();
andl2_acc
fatalerror("unhandled opcode %02x%04x: %02x\n", m_codebank, PPC, inst_state);
read_pc_noinc();
prefetch();
andl3_acc
fatalerror("unhandled opcode %02x%04x: %02x\n", m_codebank, PPC, inst_state);
read_pc_noinc();
prefetch();
eorl0_acc
read_pc_noinc();
A ^= (m_l & 0x000000ff) >> 0;
A |= m_k;
set_nz(A);
prefetch();
eorl1_acc
fatalerror("unhandled opcode %02x%04x: %02x\n", m_codebank, PPC, inst_state);
oral_imp
read_pc_noinc();
A |= m_l;
set_nz(A);
prefetch();
eorl2_acc
fatalerror("unhandled opcode %02x%04x: %02x\n", m_codebank, PPC, inst_state);
oram_imp
read_pc_noinc();
A |= m_m;
set_nz(A);
prefetch();
eorl3_acc
fatalerror("unhandled opcode %02x%04x: %02x\n", m_codebank, PPC, inst_state);
andj_imp
read_pc_noinc();
A &= m_j;
set_nz(A);
prefetch();
adcl0_acc
andk_imp
read_pc_noinc();
do_adc((m_l & 0x000000ff) >> 0);
A &= m_k;
set_nz(A);
prefetch();
adcl1_acc
andl_imp
read_pc_noinc();
do_adc((m_l & 0x0000ff00) >> 8);
A &= m_l;
set_nz(A);
prefetch();
adcl2_acc
andm_imp
read_pc_noinc();
do_adc((m_l & 0x00ff0000) >> 16);
A &= m_m;
set_nz(A);
prefetch();
adcl3_acc
eorj_imp
read_pc_noinc();
do_adc((m_l & 0xff000000) >> 24);
A ^= m_j;
set_nz(A);
prefetch();
stal0_acc
eork_imp
read_pc_noinc();
m_l = (m_l & 0xffffff00) | (A & 0xff); // TODO: flags
A ^= m_k;
set_nz(A);
prefetch();
stal1_acc
eorl_imp
read_pc_noinc();
m_l = (m_l & 0xffff00ff) | ((A & 0xff) << 8); // TODO: flags
A ^= m_l;
set_nz(A);
prefetch();
stal2_acc
eorm_imp
read_pc_noinc();
m_l = (m_l & 0xff00ffff) | ((A & 0xff) << 16); // TODO: flags
A ^= m_m;
set_nz(A);
prefetch();
stal3_acc
adcj_imp
read_pc_noinc();
m_l = (m_l & 0x00ffffff) | ((A & 0xff) << 24); // TODO: flags
do_adc(m_j);
prefetch();
ldal0_acc
adck_imp
read_pc_noinc();
A = (m_l & 0x000000ff) >> 0; // TODO: flags
do_adc(m_k);
prefetch();
ldal1_acc
adcl_imp
read_pc_noinc();
A = (m_l & 0x0000ff00) >> 8; // TODO: flags
do_adc(m_l);
prefetch();
ldal2_acc
adcm_imp
read_pc_noinc();
A = (m_l & 0x00ff0000) >> 16; // TODO: flags
do_adc(m_m);
prefetch();
ldal3_acc
staj_imp
read_pc_noinc();
A = (m_l & 0xff000000) >> 24; // TODO: flags
m_j = A;
prefetch();
cmpl0_acc
stak_imp
read_pc_noinc();
do_cmp(A, (m_l & 0x000000ff) >> 0);
m_k = A;
prefetch();
cmpl1_acc
stal_imp
read_pc_noinc();
do_cmp(A, (m_l & 0x0000ff00) >> 8);
m_l = A;
prefetch();
cmpl2_acc
stam_imp
read_pc_noinc();
do_cmp(A, (m_l & 0x00ff0000) >> 16);
m_m = A;
prefetch();
cmpl3_acc
ldaj_imp
read_pc_noinc();
do_cmp(A, (m_l & 0xff000000) >> 24);
A = m_j; // TODO: flags
prefetch();
sbcl0_acc
ldak_imp
read_pc_noinc();
do_sbc((m_l & 0x000000ff) >> 0);
A = m_k; // TODO: flags
prefetch();
sbcl1_acc
ldal_imp
read_pc_noinc();
do_sbc((m_l & 0x0000ff00) >> 8);
A = m_l; // TODO: flags
prefetch();
sbcl2_acc
ldam_imp
read_pc_noinc();
do_sbc((m_l & 0x00ff0000) >> 16);
A = m_m; // TODO: flags
prefetch();
sbcl3_acc
cmpj_imp
read_pc_noinc();
do_sbc((m_l & 0xff000000) >> 24);
do_cmp(A, m_j);
prefetch();
spa0_acc
cmpk_imp
read_pc_noinc();
m_pa = (m_pa & 0xffff00) | A; // TODO: Flags?
do_cmp(A, m_k);
prefetch();
lpa0_acc
cmpl_imp
read_pc_noinc();
do_cmp(A, m_l);
prefetch();
cmpm_imp
read_pc_noinc();
do_cmp(A, m_m);
prefetch();
sbcj_imp
read_pc_noinc();
do_sbc(m_j);
prefetch();
sbck_imp
read_pc_noinc();
do_sbc(m_k);
prefetch();
sbcl_imp
read_pc_noinc();
do_sbc(m_l);
prefetch();
sbcm_imp
read_pc_noinc();
do_sbc(m_m);
prefetch();
spa0_imp
read_pc_noinc();
m_pa = (m_pa & 0xffff00) | A;
prefetch();
lpa0_imp
read_pc_noinc();
A = (m_pa & 0x0000ff) >> 0; // TODO: Flags?
prefetch();
spa1_acc
spa1_imp
read_pc_noinc();
m_pa = (m_pa & 0xff00ff) | (A << 8); // TODO: Flags?
m_pa = (m_pa & 0xff00ff) | (A << 8);
prefetch();
lpa1_acc
lpa1_imp
read_pc_noinc();
A = (m_pa & 0x00ff00) >> 8; // TODO: Flags?
prefetch();
spa2_acc
spa2_imp
read_pc_noinc();
m_pa = (m_pa & 0x00ffff) | (A << 16); // TODO: Flags?
m_pa = (m_pa & 0x00ffff) | (A << 16);
prefetch();
lpa2_acc
lpa2_imp
read_pc_noinc();
A = (m_pa & 0xff0000) >> 16; // TODO: Flags?
prefetch();
spb0_acc
spb0_imp
read_pc_noinc();
m_pb = (m_pb & 0xffff00) | A; // TODO: Flags?
prefetch();
lpb0_acc
lpb0_imp
read_pc_noinc();
A = (m_pb & 0x0000ff) >> 0; // TODO: Flags?
prefetch();
spb1_acc
spb1_imp
read_pc_noinc();
m_pb = (m_pb & 0xff00ff) | (A << 8); // TODO: Flags?
prefetch();
lpb1_acc
lpb1_imp
read_pc_noinc();
A = (m_pb & 0x00ff00) >> 8; // TODO: Flags?
prefetch();
spb2_acc
spb2_imp
read_pc_noinc();
m_pb = (m_pb & 0x00ffff) | (A << 16); // TODO: Flags?
prefetch();
lpb2_acc
lpb2_imp
read_pc_noinc();
A = (m_pb & 0xff0000) >> 16; // TODO: Flags?
prefetch();
incpa_imp
read_pc_noinc();
m_pa++;
m_pa = (m_pa & ~0xff) | ((m_pa+1) & 0xff);
set_nz(m_pa&0xff); // startup code seems to require flag to set if low byte is 0x00?
prefetch();
incpb_imp
read_pc_noinc();
m_pb++;
m_pb = (m_pb & ~0xff) | ((m_pb+1) & 0xff);
set_nz(m_pb&0xff); // startup code seems to require flag to set if low byte is 0x00?
prefetch();
decpa_imp
read_pc_noinc();
m_pa--;
m_pa = (m_pa & ~0xff) | ((m_pa-1) & 0xff);
set_nz(m_pa&0xff); // startup code seems to require flag to set if low byte is 0x00?
prefetch();
decpb_imp
read_pc_noinc();
m_pb--;
m_pb = (m_pb & ~0xff) | ((m_pb-1) & 0xff);
set_nz(m_pb&0xff); // startup code seems to require flag to set if low byte is 0x00?
prefetch();
@ -420,8 +430,9 @@ bit_imm
prefetch();
asr_zpg
fatalerror("unhandled opcode %02x%04x: %02x\n", m_codebank, PPC, inst_state);
read_pc_noinc();
TMP = read_pc(); // TODO: verify this, should it write back or set A?
TMP = read(TMP);
do_asr(TMP);
prefetch();
asr_aba

9
src/devices/cpu/m6502/xavix.h
View File

@ -32,12 +32,21 @@ public:
O(brk_xav_imp);
O(rti_xav_imp);
O(xavora_idx);
O(xavora_idy);
O(xavand_idx);
O(xavand_idy);
O(xaveor_idx);
O(xaveor_idy);
O(xavadc_idx);
O(xavadc_idy);
O(xavsta_idx);
O(xavsta_idy);
O(xavlda_idx);
O(xavlda_idy);
O(xavcmp_idx);
O(xavcmp_idy);
O(xavsbc_idx);
O(xavsbc_idy);
typedef device_delegate<int16_t (int which, int half)> xavix_interrupt_vector_delegate;

20
src/devices/cpu/m6502/xavix2000.cpp
View File

@ -111,7 +111,10 @@ void xavix2000_device::device_start()
{
xavix_device::device_start();
state_add(SXAVIX_J, "J", m_j).callimport().formatstr("%8s");;
state_add(SXAVIX_K, "K", m_k).callimport().formatstr("%8s");;
state_add(SXAVIX_L, "L", m_l).callimport().formatstr("%8s");;
state_add(SXAVIX_M, "M", m_m).callimport().formatstr("%8s");;
state_add(SXAVIX_PA, "PA", m_pa).callimport().formatstr("%8s");
state_add(SXAVIX_PB, "PB", m_pb).callimport().formatstr("%8s");
}
@ -128,8 +131,14 @@ void xavix2000_device::state_import(const device_state_entry &entry)
switch(entry.index())
{
case SXAVIX_J:
break;
case SXAVIX_K:
break;
case SXAVIX_L:
break;
case SXAVIX_M:
break;
case SXAVIX_PA:
break;
case SXAVIX_PB:
@ -143,8 +152,17 @@ void xavix2000_device::state_string_export(const device_state_entry &entry, std:
switch(entry.index())
{
case SXAVIX_J:
str = string_format("%02x", m_j);
break;
case SXAVIX_K:
str = string_format("%02x", m_k);
break;
case SXAVIX_L:
str = string_format("%08x", m_l);
str = string_format("%02x", m_l);
break;
case SXAVIX_M:
str = string_format("%02x", m_m);
break;
case SXAVIX_PA:
str = string_format("%08x", m_pa);

99
src/devices/cpu/m6502/xavix2000.h
View File

@ -42,59 +42,59 @@ public:
O(inc_acc); // e2
O(neg_acc); // f2
O(oral0_acc);
O(oral1_acc);
O(oral2_acc);
O(oral3_acc);
O(oraj_imp);
O(orak_imp);
O(oral_imp);
O(oram_imp);
O(andl0_acc);
O(andl1_acc);
O(andl2_acc);
O(andl3_acc);
O(andj_imp);
O(andk_imp);
O(andl_imp);
O(andm_imp);
O(eorl0_acc);
O(eorl1_acc);
O(eorl2_acc);
O(eorl3_acc);
O(eorj_imp);
O(eork_imp);
O(eorl_imp);
O(eorm_imp);
O(adcl0_acc);
O(adcl1_acc);
O(adcl2_acc);
O(adcl3_acc);
O(adcj_imp);
O(adck_imp);
O(adcl_imp);
O(adcm_imp);
O(stal0_acc);
O(stal1_acc);
O(stal2_acc);
O(stal3_acc);
O(staj_imp);
O(stak_imp);
O(stal_imp);
O(stam_imp);
O(ldal0_acc);
O(ldal1_acc);
O(ldal2_acc);
O(ldal3_acc);
O(ldaj_imp);
O(ldak_imp);
O(ldal_imp);
O(ldam_imp);
O(cmpl0_acc);
O(cmpl1_acc);
O(cmpl2_acc);
O(cmpl3_acc);
O(cmpj_imp);
O(cmpk_imp);
O(cmpl_imp);
O(cmpm_imp);
O(sbcl0_acc);
O(sbcl1_acc);
O(sbcl2_acc);
O(sbcl3_acc);
O(sbcj_imp);
O(sbck_imp);
O(sbcl_imp);
O(sbcm_imp);
O(spa2_acc); // Store accumulator in 24-bit address register PA MSB (Bank bit)
O(lpa2_acc); // Load accumulator from 24-bit address register PA MSB (Bank bit)
O(spa0_acc); // Store accumulator in 24-bit address register PA LSB (Low 8 bits of address)
O(lpa0_acc); // Load accumulator from 24-bit address register PA LSB (Low 8 bits of address)
O(spa1_acc); // Store accumulator in 24-bit address register PA MID (High 8 bits of address)
O(lpa1_acc); // Load accumulator from 24-bit address register PA MID (High 8 bits of address)
O(spa2_imp); // Store accumulator in 24-bit address register PA MSB (Bank bit)
O(lpa2_imp); // Load accumulator from 24-bit address register PA MSB (Bank bit)
O(spa0_imp); // Store accumulator in 24-bit address register PA LSB (Low 8 bits of address)
O(lpa0_imp); // Load accumulator from 24-bit address register PA LSB (Low 8 bits of address)
O(spa1_imp); // Store accumulator in 24-bit address register PA MID (High 8 bits of address)
O(lpa1_imp); // Load accumulator from 24-bit address register PA MID (High 8 bits of address)
O(spb2_acc); // Store accumulator in 24-bit address register PB MSB (Bank bit)
O(lpb2_acc); // Load accumulator from 24-bit address register PB MSB (Bank bit)
O(spb0_acc); // Store accumulator in 24-bit address register PB LSB (Low 8 bits of address)
O(lpb0_acc); // Load accumulator from 24-bit address register PB LSB (Low 8 bits of address)
O(spb1_acc); // Store accumulator in 24-bit address register PB MID (High 8 bits of address)
O(lpb1_acc); // Load accumulator from 24-bit address register PB MID (High 8 bits of address)
O(spb2_imp); // Store accumulator in 24-bit address register PB MSB (Bank bit)
O(lpb2_imp); // Load accumulator from 24-bit address register PB MSB (Bank bit)
O(spb0_imp); // Store accumulator in 24-bit address register PB LSB (Low 8 bits of address)
O(lpb0_imp); // Load accumulator from 24-bit address register PB LSB (Low 8 bits of address)
O(spb1_imp); // Store accumulator in 24-bit address register PB MID (High 8 bits of address)
O(lpb1_imp); // Load accumulator from 24-bit address register PB MID (High 8 bits of address)
O(incpa_imp);
O(decpa_imp);
@ -144,14 +144,21 @@ public:
#undef O
uint32_t m_l; // 32-bit register?
uint8_t m_j;
uint8_t m_k;
uint8_t m_l;
uint8_t m_m;
uint32_t m_pa; // 24-bit address register?
uint32_t m_pb; // ^
};
enum {
SXAVIX_L = XAVIX_CODEBANK+1,
SXAVIX_J = XAVIX_CODEBANK+1,
SXAVIX_K,
SXAVIX_L,
SXAVIX_M,
SXAVIX_PA,
SXAVIX_PB
};

6
src/mame/drivers/xavix.cpp
View File

@ -1138,7 +1138,7 @@ ROM_END
CONS( 2004, xavtenni, 0, 0, xavix2000_i2c_24c04, xavix, xavix_i2c_state, init_xavix, "SSD Company LTD", "XaviX Tennis (XaviXPORT)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
CONS( 2005, ttv_sw, 0, 0, xavix2000_i2c_24c02, xavix, xavix_i2c_state, init_xavix, "Tiger / SSD Company LTD", "Star Wars Saga Edition - Lightsaber Battle Game", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
CONS( 2005, ttv_lotr, 0, 0, xavix2000_i2c_24c02, xavix, xavix_i2c_state, init_xavix, "Tiger / SSD Company LTD", "Lord Of The Rings - Warrior of Middle-Earth", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
CONS( 2005, ttv_sw, 0, 0, xavix2000_i2c_24c02, xavix, xavix_i2c_lotr_state, init_xavix, "Tiger / SSD Company LTD", "Star Wars Saga Edition - Lightsaber Battle Game", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
CONS( 2005, ttv_lotr, 0, 0, xavix2000_i2c_24c02, xavix, xavix_i2c_lotr_state, init_xavix, "Tiger / SSD Company LTD", "Lord Of The Rings - Warrior of Middle-Earth", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
CONS( 2005, ttv_mx, 0, 0, xavix2000_i2c_24c04, ttv_mx, xavix_i2c_state, init_xavix, "Tiger / SSD Company LTD", "MX Dirt Rebel", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
CONS( 2003, drgqst, 0, 0, xavix2000_i2c_24c02, xavix, xavix_i2c_state, init_xavix, "Square Enix / SSD Company LTD", "Kenshin Dragon Quest: Yomigaerishi Densetsu no Ken", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
CONS( 2003, drgqst, 0, 0, xavix2000_i2c_24c02, xavix, xavix_i2c_lotr_state, init_xavix, "Square Enix / SSD Company LTD", "Kenshin Dragon Quest: Yomigaerishi Densetsu no Ken", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )

13
src/mame/includes/xavix.h
View File

@ -527,6 +527,19 @@ protected:
required_device<i2cmem_device> m_i2cmem;
};
class xavix_i2c_lotr_state : public xavix_i2c_state
{
public:
xavix_i2c_lotr_state(const machine_config &mconfig, device_type type, const char *tag)
: xavix_i2c_state(mconfig, type, tag)
{ }
protected:
virtual uint8_t read_io1(uint8_t direction) override;
//virtual void write_io1(uint8_t data, uint8_t direction) override;
};
class xavix_mtrk_state : public xavix_state
{

17
src/mame/machine/xavix.cpp
View File

@ -421,6 +421,23 @@ void xavix_i2c_state::write_io1(uint8_t data, uint8_t direction)
}
}
uint8_t xavix_i2c_lotr_state::read_io1(uint8_t direction)
{
uint8_t ret = m_in1->read();
// some kind of comms with the IR sensor?
ret ^= (machine().rand() & 0x02);
ret ^= (machine().rand() & 0x04);
if (!(direction & 0x08))
{
ret &= ~0x08;
ret |= (m_i2cmem->read_sda() & 1) << 3;
}
return ret;
}
uint8_t xavix_ekara_state::read_io1(uint8_t direction)
{
uint8_t extrainlatch0 = 0x00;