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https://github.com/holub/mame
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(MESS) pentagon tags (nw)
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e6d0d09b88
commit
1778afc2e8
@ -15,6 +15,12 @@ public:
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pentagon_state(const machine_config &mconfig, device_type type, const char *tag)
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: spectrum_state(mconfig, type, tag)
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, m_maincpu(*this, "maincpu")
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, m_bank1(*this, "bank1")
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, m_bank2(*this, "bank2")
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, m_bank3(*this, "bank3")
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, m_bank4(*this, "bank4")
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, m_beta(*this, BETA_DISK_TAG)
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, m_ram(*this, RAM_TAG)
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{ }
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DECLARE_DIRECT_UPDATE_MEMBER(pentagon_direct);
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@ -23,70 +29,78 @@ public:
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protected:
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required_device<cpu_device> m_maincpu;
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UINT8 *m_maincpu_rom;
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required_memory_bank m_bank1;
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required_memory_bank m_bank2;
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required_memory_bank m_bank3;
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required_memory_bank m_bank4;
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required_device<device_t> m_beta;
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required_device<ram_device> m_ram;
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private:
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UINT8 *m_p_ram;
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void pentagon_update_memory();
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};
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DIRECT_UPDATE_MEMBER(pentagon_state::pentagon_direct)
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{
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device_t *beta = machine().device(BETA_DISK_TAG);
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UINT16 pc = m_maincpu->pcbase();
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if (beta->started() && betadisk_is_active(beta))
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if (m_beta->started() && betadisk_is_active(m_beta) && (pc >= 0x4000))
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{
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if (pc >= 0x4000)
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{
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m_ROMSelection = ((m_port_7ffd_data>>4) & 0x01) ? 1 : 0;
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betadisk_disable(beta);
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membank("bank1")->set_base(m_maincpu_rom + 0x010000 + (m_ROMSelection<<14));
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}
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} else if (((pc & 0xff00) == 0x3d00) && (m_ROMSelection==1))
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m_ROMSelection = BIT(m_port_7ffd_data, 4);
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betadisk_disable(m_beta);
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m_bank1->set_base(&m_p_ram[0x10000 + (m_ROMSelection<<14)]);
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}
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else
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if (((pc & 0xff00) == 0x3d00) && (m_ROMSelection==1))
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{
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m_ROMSelection = 3;
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if (beta->started())
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betadisk_enable(beta);
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if (m_beta->started())
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betadisk_enable(m_beta);
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}
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if(address<=0x3fff)
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if (address<=0x3fff)
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{
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if (m_ROMSelection == 3) {
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if (beta->started()) {
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if (m_ROMSelection == 3)
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{
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if (m_beta->started())
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{
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direct.explicit_configure(0x0000, 0x3fff, 0x3fff, machine().root_device().memregion("beta:beta")->base());
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membank("bank1")->set_base(machine().root_device().memregion("beta:beta")->base());
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m_bank1->set_base(machine().root_device().memregion("beta:beta")->base());
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}
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} else {
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direct.explicit_configure(0x0000, 0x3fff, 0x3fff, m_maincpu_rom + 0x010000 + (m_ROMSelection<<14));
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membank("bank1")->set_base(m_maincpu_rom + 0x010000 + (m_ROMSelection<<14));
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}
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else
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{
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direct.explicit_configure(0x0000, 0x3fff, 0x3fff, &m_p_ram[0x10000 + (m_ROMSelection<<14)]);
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m_bank1->set_base(&m_p_ram[0x10000 + (m_ROMSelection<<14)]);
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}
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return ~0;
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}
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return address;
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}
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void pentagon_state::pentagon_update_memory()
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{
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device_t *beta = machine().device(BETA_DISK_TAG);
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UINT8 *messram = machine().device<ram_device>(RAM_TAG)->pointer();
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UINT8 *messram = m_ram->pointer();
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m_screen_location = messram + ((m_port_7ffd_data & 8) ? (7<<14) : (5<<14));
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membank("bank4")->set_base(messram + ((m_port_7ffd_data & 0x07) * 0x4000));
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m_bank4->set_base(messram + ((m_port_7ffd_data & 0x07) * 0x4000));
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if (beta->started() && betadisk_is_active(beta) && !( m_port_7ffd_data & 0x10 ) )
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if (m_beta->started() && betadisk_is_active(m_beta) && !( m_port_7ffd_data & 0x10 ) )
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{
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/* GLUK */
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if (strcmp(machine().system().name, "pent1024")==0) {
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if (strcmp(machine().system().name, "pent1024")==0)
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m_ROMSelection = 2;
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} else {
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m_ROMSelection = ((m_port_7ffd_data>>4) & 0x01) ;
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}
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else
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m_ROMSelection = BIT(m_port_7ffd_data, 4);
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}
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else {
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else
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/* ROM switching */
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m_ROMSelection = ((m_port_7ffd_data>>4) & 0x01) ;
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}
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m_ROMSelection = BIT(m_port_7ffd_data, 4);
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/* rom 0 is 128K rom, rom 1 is 48 BASIC */
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membank("bank1")->set_base(m_maincpu_rom + 0x010000 + (m_ROMSelection<<14));
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m_bank1->set_base(&m_p_ram[0x10000 + (m_ROMSelection<<14)]);
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}
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WRITE8_MEMBER(pentagon_state::pentagon_port_7ffd_w)
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@ -117,28 +131,27 @@ ADDRESS_MAP_END
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MACHINE_RESET_MEMBER(pentagon_state,pentagon)
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{
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UINT8 *messram = machine().device<ram_device>(RAM_TAG)->pointer();
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device_t *beta = machine().device(BETA_DISK_TAG);
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UINT8 *messram = m_ram->pointer();
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address_space &space = m_maincpu->space(AS_PROGRAM);
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m_maincpu_rom = memregion("maincpu")->base();
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m_p_ram = memregion("maincpu")->base();
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space.install_read_bank(0x0000, 0x3fff, "bank1");
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space.unmap_write(0x0000, 0x3fff);
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if (beta->started()) {
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betadisk_enable(beta);
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betadisk_clear_status(beta);
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if (m_beta->started())
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{
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betadisk_enable(m_beta);
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betadisk_clear_status(m_beta);
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}
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space.set_direct_update_handler(direct_update_delegate(FUNC(pentagon_state::pentagon_direct), this));
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memset(messram,0,128*1024);
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/* Bank 5 is always in 0x4000 - 0x7fff */
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membank("bank2")->set_base(messram + (5<<14));
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m_bank2->set_base(messram + (5<<14));
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/* Bank 2 is always in 0x8000 - 0xbfff */
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membank("bank3")->set_base(messram + (2<<14));
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m_bank3->set_base(messram + (2<<14));
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m_port_7ffd_data = 0;
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m_port_1ffd_data = -1;
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