From 17e7fa2f1ecb7017c2b136b9b70b9c53988427da Mon Sep 17 00:00:00 2001 From: Scott Stone Date: Thu, 6 Sep 2012 09:02:11 +0000 Subject: [PATCH] Some notes / observations + changes to act as an example so you can see what I'm talking about (and a fix to the input ports), regarding ttchamp.c. From Haze (nw) --- src/mame/drivers/ttchamp.c | 59 ++++++++++++++++++++++++++++++-------- 1 file changed, 47 insertions(+), 12 deletions(-) diff --git a/src/mame/drivers/ttchamp.c b/src/mame/drivers/ttchamp.c index 7d64ee5f1cd..6dd817fe42d 100644 --- a/src/mame/drivers/ttchamp.c +++ b/src/mame/drivers/ttchamp.c @@ -49,10 +49,12 @@ class ttchamp_state : public driver_device { public: ttchamp_state(const machine_config &mconfig, device_type type, const char *tag) - : driver_device(mconfig, type, tag) , - m_peno_vram(*this, "peno_vram"){ } + : driver_device(mconfig, type, tag) + { } + + UINT16* m_peno_vram; + UINT16* m_peno_mainram; - required_shared_ptr m_peno_vram; UINT16 m_paloff; DECLARE_WRITE16_MEMBER(paloff_w); DECLARE_WRITE16_MEMBER(pcup_prgbank_w); @@ -60,11 +62,39 @@ public: DECLARE_READ16_MEMBER(peno_rand); DECLARE_READ16_MEMBER(peno_rand2); DECLARE_DRIVER_INIT(ttchamp); + + DECLARE_WRITE16_MEMBER( penocup_vid_w ) + { + offset &=0x7fff; + COMBINE_DATA(&m_peno_vram[offset]); + } + + DECLARE_READ16_MEMBER( penocup_mainram_r ) + { + return m_peno_mainram[offset]; + } + + DECLARE_WRITE16_MEMBER( penocup_mainram_w ) + { + offset &=0x7fff; + COMBINE_DATA(&m_peno_mainram[offset]); +// COMBINE_DATA(&m_peno_vram[offset]); + } + + + }; + static VIDEO_START(ttchamp) { + ttchamp_state *state = machine.driver_data(); + state->m_peno_vram = (UINT16*)auto_alloc_array_clear(machine, UINT16, 0x10000/2); + state->m_peno_mainram = (UINT16*)auto_alloc_array_clear(machine, UINT16, 0x10000/2); + + + } static SCREEN_UPDATE_IND16(ttchamp) @@ -88,7 +118,7 @@ static SCREEN_UPDATE_IND16(ttchamp) // } count=0; - UINT8 *videoram = reinterpret_cast(state->m_peno_vram.target()); + UINT8 *videoram = (UINT8*)state->m_peno_vram; for (y=0;ybase(); - machine().root_device().membank("bank1")->set_base(&ROM1[0x120000]); + machine().root_device().membank("bank1")->set_base(&ROM1[0x100000]); machine().root_device().membank("bank2")->set_base(&ROM1[0x180000]); }