mirror of
https://github.com/holub/mame
synced 2025-04-21 07:52:35 +03:00
- converted CDP1869 to the new device system
- refactored to represent how the hardware actually works - added PMA latching on OUT5 - separated Cidelsa video to its own file
This commit is contained in:
Curt Coder
parent
12589d9abd
commit
1859e012d2
2
.gitattributes
vendored
2
.gitattributes
vendored
@ -2146,6 +2146,7 @@ src/mame/includes/ccastles.h svneol=native#text/plain
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src/mame/includes/cchasm.h svneol=native#text/plain
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src/mame/includes/cclimber.h svneol=native#text/plain
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src/mame/includes/centiped.h svneol=native#text/plain
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src/mame/includes/cidelsa.h svneol=native#text/plain
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src/mame/includes/cinemat.h svneol=native#text/plain
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src/mame/includes/circus.h svneol=native#text/plain
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src/mame/includes/cloak.h svneol=native#text/plain
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@ -2689,6 +2690,7 @@ src/mame/video/champbas.c svneol=native#text/plain
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src/mame/video/changela.c svneol=native#text/plain
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src/mame/video/cheekyms.c svneol=native#text/plain
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src/mame/video/chqflag.c svneol=native#text/plain
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src/mame/video/cidelsa.c svneol=native#text/plain
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src/mame/video/cinemat.c svneol=native#text/plain
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src/mame/video/circus.c svneol=native#text/plain
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src/mame/video/circusc.c svneol=native#text/plain
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File diff suppressed because it is too large
Load Diff
@ -34,13 +34,6 @@
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#ifndef __CDP1869_VIDEO__
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#define __CDP1869_VIDEO__
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typedef enum _cdp1869_video_format cdp1869_video_format;
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enum _cdp1869_video_format {
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CDP1869_NTSC,
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CDP1869_PAL
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};
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#define CDP1869_DOT_CLK_PAL 5626000.0
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#define CDP1869_DOT_CLK_NTSC 5670000.0
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#define CDP1869_COLOR_CLK_PAL 8867236.0
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@ -54,8 +47,8 @@ enum _cdp1869_video_format {
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#define CDP1869_HSYNC_START (56 * CDP1869_CHAR_WIDTH)
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#define CDP1869_HSYNC_END (60 * CDP1869_CHAR_WIDTH)
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#define CDP1869_HBLANK_START (54 * CDP1869_CHAR_WIDTH)
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#define CDP1869_HBLANK_END (5 * CDP1869_CHAR_WIDTH)
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#define CDP1869_SCREEN_START_PAL (9 * CDP1869_CHAR_WIDTH)
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#define CDP1869_HBLANK_END ( 5 * CDP1869_CHAR_WIDTH)
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#define CDP1869_SCREEN_START_PAL ( 9 * CDP1869_CHAR_WIDTH)
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#define CDP1869_SCREEN_START_NTSC (10 * CDP1869_CHAR_WIDTH)
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#define CDP1869_SCREEN_START (10 * CDP1869_CHAR_WIDTH)
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#define CDP1869_SCREEN_END (50 * CDP1869_CHAR_WIDTH)
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@ -83,48 +76,85 @@ enum _cdp1869_video_format {
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#define CDP1869_SCANLINE_PREDISPLAY_END_NTSC 228
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#define CDP1869_VISIBLE_SCANLINES_NTSC (CDP1869_SCANLINE_DISPLAY_END_NTSC - CDP1869_SCANLINE_DISPLAY_START_NTSC)
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#define CDP1869_FPS_PAL CDP1869_DOT_CLK_PAL / CDP1869_SCREEN_WIDTH / CDP1869_TOTAL_SCANLINES_PAL
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#define CDP1869_FPS_NTSC CDP1869_DOT_CLK_NTSC / CDP1869_SCREEN_WIDTH / CDP1869_TOTAL_SCANLINES_NTSC
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#define CDP1869_PALETTE_LENGTH 8+64
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#define CDP1869_WEIGHT_RED 30 // % of max luminance
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#define CDP1869_WEIGHT_GREEN 59
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#define CDP1869_WEIGHT_BLUE 11
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#define CDP1869_VIDEO DEVICE_GET_INFO_NAME(cdp1869_video)
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#define CDP1869_CHARRAM_SIZE 0x1000
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#define CDP1869_PAGERAM_SIZE 0x800
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typedef UINT8 (*cdp1869_char_ram_read_func)(const device_config *device, UINT16 pma, UINT8 cma);
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#define CDP1869_CHAR_RAM_READ(name) UINT8 name(const device_config *device, UINT16 pma, UINT8 cma)
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#define CDP1869_COLUMNS_HALF 20
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#define CDP1869_COLUMNS_FULL 40
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#define CDP1869_ROWS_HALF 12
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#define CDP1869_ROWS_FULL_PAL 25
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#define CDP1869_ROWS_FULL_NTSC 24
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typedef void (*cdp1869_char_ram_write_func)(const device_config *device, UINT16 pma, UINT8 cma, UINT8 data);
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#define CDP1869_CHAR_RAM_WRITE(name) void name(const device_config *device, UINT16 pma, UINT8 cma, UINT8 data)
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typedef struct CDP1869_interface
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typedef UINT8 (*cdp1869_page_ram_read_func)(const device_config *device, UINT16 pma);
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#define CDP1869_PAGE_RAM_READ(name) UINT8 name(const device_config *device, UINT16 pma)
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typedef void (*cdp1869_page_ram_write_func)(const device_config *device, UINT16 pma, UINT8 data);
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#define CDP1869_PAGE_RAM_WRITE(name) void name(const device_config *device, UINT16 pma, UINT8 data)
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typedef int (*cdp1869_pcb_read_func)(const device_config *device, UINT16 pma, UINT8 cma);
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#define CDP1869_PCB_READ(name) int name(const device_config *device, UINT16 pma, UINT8 cma)
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typedef void (*cdp1869_on_prd_changed_func) (const device_config *device, int prd);
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#define CDP1869_ON_PRD_CHANGED(name) void name(const device_config *device, int prd)
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typedef enum _cdp1869_format cdp1869_format;
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enum _cdp1869_format {
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CDP1869_NTSC = 0,
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CDP1869_PAL
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};
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/* interface */
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typedef struct _cdp1869_interface cdp1869_interface;
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struct _cdp1869_interface
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{
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cdp1869_video_format video_format; // display format (NTSC/PAL)
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int charrom_region; // memory region to load CHARRAM from
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UINT16 charram_size; // CHARRAM size
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UINT16 pageram_size; // PAGERAM size
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UINT8 (*get_color_bits)(UINT8 cramdata, UINT16 cramaddr, UINT16 pramaddr); // 0x01 = PCB, 0x02 = CCB0, 0x04 = CCB1
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} CDP1869_interface;
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const char *screen_tag; /* screen we are acting on */
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int pixel_clock; /* the dot clock of the chip */
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int color_clock; /* the chroma clock of the chip */
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WRITE8_HANDLER ( cdp1869_out3_w );
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WRITE8_HANDLER ( cdp1869_out4_w );
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WRITE8_HANDLER ( cdp1869_out5_w );
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WRITE8_HANDLER ( cdp1869_out6_w );
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WRITE8_HANDLER ( cdp1869_out7_w );
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cdp1869_format pal_ntsc; /* screen format */
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/* page memory read function */
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cdp1869_page_ram_read_func page_ram_r;
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/* page memory write function */
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cdp1869_page_ram_write_func page_ram_w;
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/* page memory color bit read function */
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cdp1869_pcb_read_func pcb_r;
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/* character memory read function */
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cdp1869_char_ram_read_func char_ram_r;
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/* character memory write function */
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cdp1869_char_ram_write_func char_ram_w;
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/* if specified, this gets called for every change of the predisplay pin (CDP1870/76 pin 1) */
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cdp1869_on_prd_changed_func on_prd_changed;
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};
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/* device interface */
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DEVICE_GET_INFO( cdp1869_video );
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/* palette initialization */
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PALETTE_INIT( cdp1869 );
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VIDEO_START( cdp1869 );
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VIDEO_UPDATE( cdp1869 );
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READ8_HANDLER ( cdp1869_charram_r );
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READ8_HANDLER ( cdp1869_pageram_r );
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WRITE8_HANDLER ( cdp1869_charram_w );
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WRITE8_HANDLER ( cdp1869_pageram_w );
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/* io port access */
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WRITE8_DEVICE_HANDLER( cdp1869_out3_w );
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WRITE8_DEVICE_HANDLER( cdp1869_out4_w );
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WRITE8_DEVICE_HANDLER( cdp1869_out5_w );
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WRITE8_DEVICE_HANDLER( cdp1869_out6_w );
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WRITE8_DEVICE_HANDLER( cdp1869_out7_w );
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void cdp1869_configure(const CDP1869_interface *intf);
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/* character memory access */
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READ8_DEVICE_HANDLER ( cdp1869_charram_r );
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WRITE8_DEVICE_HANDLER ( cdp1869_charram_w );
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UINT16 cdp1869_get_cma(UINT16 offset);
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/* page memory access */
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READ8_DEVICE_HANDLER ( cdp1869_pageram_r );
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WRITE8_DEVICE_HANDLER ( cdp1869_pageram_w );
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/* updates the screen */
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void cdp1869_update(const device_config *device, bitmap_t *bitmap, const rectangle *cliprect);
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#endif
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@ -1,9 +1,11 @@
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#include "driver.h"
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#include "deprecat.h"
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#include "cpu/cdp1802/cdp1802.h"
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#include "cpu/cop400/cop400.h"
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#include "video/cdp1869.h"
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#include "sound/cdp1869.h"
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#include "sound/ay8910.h"
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#include "cidelsa.h"
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/*
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@ -14,118 +16,137 @@
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*/
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#define DESTRYER_CHR1 3579000.0 // unverified
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#define DESTRYER_CHR2 XTAL_5_7143MHz
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#define ALTAIR_CHR1 3579000.0 // unverified
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#define ALTAIR_CHR2 CDP1869_DOT_CLK_PAL // unverified
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#define DRACO_CHR1 XTAL_4_43361MHz
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#define DRACO_CHR2 CDP1869_DOT_CLK_PAL // unverified
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#define DRACO_SND_CHR1 XTAL_2_01216MHz
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#define CDP1869_TAG "cdp1869"
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/* CDP1802 Interface */
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static int cdp1869_prd;
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static int cdp1869_pcb;
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static UINT8 *pcb_ram; // 2048x1 bit PCB ram
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static int cdp1802_mode = CDP1802_MODE_RESET;
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static UINT8 cidelsa_mode_r(void)
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{
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return cdp1802_mode;
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cidelsa_state *state = Machine->driver_data;
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return state->cdp1802_mode;
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}
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static UINT8 cidelsa_ef_r(void)
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{
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/*
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EF1 CDP1869 _PRD
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EF2 Test
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EF3 Coin 2
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EF4 Coin 1
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*/
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return readinputportbytag("EF");
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}
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static void cidelsa_q_w(int q)
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{
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cidelsa_state *state = Machine->driver_data;
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state->cdp1802_q = q;
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}
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static const CDP1802_CONFIG cidelsa_cdp1802_config =
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{
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cidelsa_mode_r, // MODE input
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cidelsa_ef_r, // EF input
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NULL, // SC output
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NULL, // Q output
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NULL, // DMA read
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NULL // DMA write
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cidelsa_mode_r, // MODE
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cidelsa_ef_r, // EF
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NULL, // SC
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cidelsa_q_w, // Q
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NULL, // DMA read
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NULL // DMA write
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};
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/* Draco Sound Interface */
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/* Sound Interface */
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static int draco_sound;
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static int draco_ay_latch;
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static WRITE8_HANDLER ( draco_sound_bankswitch_w )
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{
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memory_set_bank(1, BIT(data, 3));
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}
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static WRITE8_HANDLER ( draco_sound_g_w )
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static WRITE8_HANDLER( draco_sound_bankswitch_w )
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{
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/*
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G1 G0 description
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pin description
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0 0 IAB inactive
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0 1 DWS write to PSG
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1 0 DTB read from PSG
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1 1 INTAK latch address
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D0 not connected
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D1 not connected
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D2 not connected
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D3 2716 A10
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*/
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int bank = BIT(data, 3);
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memory_set_bank(1, bank);
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}
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static WRITE8_HANDLER( draco_sound_g_w )
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{
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cidelsa_state *state = machine->driver_data;
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/*
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G1 G0 description
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0 0 IAB inactive
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0 1 DWS write to PSG
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1 0 DTB read from PSG
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1 1 INTAK latch address
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*/
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switch (data)
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{
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case 0x01:
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AY8910_write_port_0_w(machine, 0, draco_ay_latch);
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AY8910_write_port_0_w(machine, 0, state->draco_ay_latch);
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break;
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case 0x02:
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draco_ay_latch = AY8910_read_port_0_r(machine, 0);
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state->draco_ay_latch = AY8910_read_port_0_r(machine, 0);
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break;
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case 0x03:
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AY8910_control_port_0_w(machine, 0, draco_ay_latch);
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AY8910_control_port_0_w(machine, 0, state->draco_ay_latch);
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break;
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}
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}
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static READ8_HANDLER ( draco_sound_in_r )
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static READ8_HANDLER( draco_sound_in_r )
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{
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return ~draco_sound & 0x07; // inverted
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cidelsa_state *state = machine->driver_data;
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return ~(state->draco_sound) & 0x07;
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}
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static READ8_HANDLER ( draco_sound_ay8910_r )
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static READ8_HANDLER( draco_sound_ay8910_r )
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{
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return draco_ay_latch;
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cidelsa_state *state = machine->driver_data;
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return state->draco_ay_latch;
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}
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static WRITE8_HANDLER ( draco_sound_ay8910_w )
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static WRITE8_HANDLER( draco_sound_ay8910_w )
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{
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draco_ay_latch = data;
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cidelsa_state *state = machine->driver_data;
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state->draco_ay_latch = data;
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}
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static WRITE8_HANDLER ( draco_ay8910_port_a_w )
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static WRITE8_HANDLER( draco_ay8910_port_a_w )
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{
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/*
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bit description
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0 N/C
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1 N/C
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2 N/C
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3 N/C
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4 N/C
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5 N/C
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6 N/C
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7 N/C
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0 not connected
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1 not connected
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2 not connected
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3 not connected
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4 not connected
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5 not connected
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6 not connected
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7 not connected
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*/
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}
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static WRITE8_HANDLER ( draco_ay8910_port_b_w )
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static WRITE8_HANDLER( draco_ay8910_port_b_w )
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{
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/*
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bit description
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0 RELE0
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@ -133,27 +154,25 @@ static WRITE8_HANDLER ( draco_ay8910_port_b_w )
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2 sound output -> * -> 22K capacitor -> GND
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3 sound output -> * -> 220K capacitor -> GND
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4 5V -> 1K resistor -> * -> 10uF capacitor -> GND (volume pot voltage adjustment)
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5 N/C
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6 N/C
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7 N/C
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5 not connected
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6 not connected
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7 not connected
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*/
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}
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static const struct AY8910interface ay8910_interface =
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{
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0, // port A read
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0, // port B read
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draco_ay8910_port_a_w, // port A write
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draco_ay8910_port_b_w // port B write
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0,
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0,
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draco_ay8910_port_a_w,
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draco_ay8910_port_b_w
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};
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/* Read/Write Handlers */
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static WRITE8_HANDLER ( destryer_out1_w )
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static WRITE8_HANDLER( destryer_out1_w )
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{
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/*
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bit description
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0
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@ -164,14 +183,12 @@ static WRITE8_HANDLER ( destryer_out1_w )
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5
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6
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7
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*/
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}
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static WRITE8_HANDLER ( altair_out1_w )
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static WRITE8_HANDLER( altair_out1_w )
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{
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/*
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bit description
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0 S1 (CARTUCHO)
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@ -182,50 +199,31 @@ static WRITE8_HANDLER ( altair_out1_w )
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5 LGF
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6 CONT. M2
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7 CONT. M1
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*/
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set_led_status(0, BIT(data, 3)); // 1P
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set_led_status(1, BIT(data, 4)); // 2P
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set_led_status(2, BIT(data, 5)); // FIRE
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set_led_status(0, data & 0x08); // 1P
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set_led_status(1, data & 0x10); // 2P
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set_led_status(2, data & 0x20); // FIRE
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||||
}
|
||||
|
||||
static WRITE8_HANDLER ( draco_out1_w )
|
||||
static WRITE8_HANDLER( draco_out1_w )
|
||||
{
|
||||
/*
|
||||
cidelsa_state *state = machine->driver_data;
|
||||
|
||||
/*
|
||||
bit description
|
||||
|
||||
0 3K9 -> Green signal
|
||||
1 820R -> Blue signal
|
||||
2 510R -> Red signal
|
||||
3 1K -> N/C
|
||||
4 N/C
|
||||
3 1K -> not connected
|
||||
4 not connected
|
||||
5 SONIDO A -> COP402 IN0
|
||||
6 SONIDO B -> COP402 IN1
|
||||
7 SONIDO C -> COP402 IN2
|
||||
|
||||
*/
|
||||
|
||||
draco_sound = (data >> 5) & 0x07;
|
||||
}
|
||||
|
||||
static WRITE8_HANDLER ( cidelsa_charram_w )
|
||||
{
|
||||
int addr = cdp1869_get_cma(offset);
|
||||
|
||||
pcb_ram[addr] = activecpu_get_reg(CDP1802_Q);
|
||||
|
||||
cdp1869_charram_w(machine, offset, data);
|
||||
}
|
||||
|
||||
static READ8_HANDLER ( cidelsa_charram_r )
|
||||
{
|
||||
int addr = cdp1869_get_cma(offset);
|
||||
|
||||
cdp1869_pcb = pcb_ram[addr];
|
||||
|
||||
return cdp1869_charram_r(machine, offset);
|
||||
state->draco_sound = (data & 0xe0) >> 5;
|
||||
}
|
||||
|
||||
/* Memory Maps */
|
||||
@ -235,25 +233,25 @@ static READ8_HANDLER ( cidelsa_charram_r )
|
||||
static ADDRESS_MAP_START( destryer_map, ADDRESS_SPACE_PROGRAM, 8 )
|
||||
AM_RANGE(0x0000, 0x1fff) AM_ROM
|
||||
AM_RANGE(0x2000, 0x20ff) AM_RAM AM_BASE(&generic_nvram) AM_SIZE(&generic_nvram_size)
|
||||
AM_RANGE(0xf400, 0xf7ff) AM_READWRITE(cidelsa_charram_r, cidelsa_charram_w)
|
||||
AM_RANGE(0xf800, 0xffff) AM_READWRITE(cdp1869_pageram_r, cdp1869_pageram_w)
|
||||
AM_RANGE(0xf400, 0xf7ff) AM_DEVREADWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_charram_r, cdp1869_charram_w)
|
||||
AM_RANGE(0xf800, 0xffff) AM_DEVREADWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_pageram_r, cdp1869_pageram_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( destryea_map, ADDRESS_SPACE_PROGRAM, 8 )
|
||||
AM_RANGE(0x0000, 0x1fff) AM_ROM
|
||||
AM_RANGE(0x3000, 0x30ff) AM_RAM AM_BASE(&generic_nvram) AM_SIZE(&generic_nvram_size)
|
||||
AM_RANGE(0xf400, 0xf7ff) AM_READWRITE(cidelsa_charram_r, cidelsa_charram_w)
|
||||
AM_RANGE(0xf800, 0xffff) AM_READWRITE(cdp1869_pageram_r, cdp1869_pageram_w)
|
||||
AM_RANGE(0xf400, 0xf7ff) AM_DEVREADWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_charram_r, cdp1869_charram_w)
|
||||
AM_RANGE(0xf800, 0xffff) AM_DEVREADWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_pageram_r, cdp1869_pageram_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( destryer_io_map, ADDRESS_SPACE_IO, 8 )
|
||||
AM_RANGE(0x01, 0x01) AM_READ_PORT("IN0") AM_WRITE(destryer_out1_w)
|
||||
AM_RANGE(0x02, 0x02) AM_READ_PORT("IN1")
|
||||
AM_RANGE(0x03, 0x03) AM_WRITE(cdp1869_out3_w)
|
||||
AM_RANGE(0x04, 0x04) AM_WRITE(cdp1869_out4_w)
|
||||
AM_RANGE(0x05, 0x05) AM_WRITE(cdp1869_out5_w)
|
||||
AM_RANGE(0x06, 0x06) AM_WRITE(cdp1869_out6_w)
|
||||
AM_RANGE(0x07, 0x07) AM_WRITE(cdp1869_out7_w)
|
||||
AM_RANGE(0x03, 0x03) AM_DEVWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_out3_w)
|
||||
AM_RANGE(0x04, 0x04) AM_DEVWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_out4_w)
|
||||
AM_RANGE(0x05, 0x05) AM_DEVWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_out5_w)
|
||||
AM_RANGE(0x06, 0x06) AM_DEVWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_out6_w)
|
||||
AM_RANGE(0x07, 0x07) AM_DEVWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_out7_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
// Altair
|
||||
@ -261,18 +259,18 @@ ADDRESS_MAP_END
|
||||
static ADDRESS_MAP_START( altair_map, ADDRESS_SPACE_PROGRAM, 8 )
|
||||
AM_RANGE(0x0000, 0x2fff) AM_ROM
|
||||
AM_RANGE(0x3000, 0x30ff) AM_RAM
|
||||
AM_RANGE(0xf400, 0xf7ff) AM_READWRITE(cidelsa_charram_r, cidelsa_charram_w)
|
||||
AM_RANGE(0xf800, 0xffff) AM_READWRITE(cdp1869_pageram_r, cdp1869_pageram_w)
|
||||
AM_RANGE(0xf400, 0xf7ff) AM_DEVREADWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_charram_r, cdp1869_charram_w)
|
||||
AM_RANGE(0xf800, 0xffff) AM_DEVREADWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_pageram_r, cdp1869_pageram_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( altair_io_map, ADDRESS_SPACE_IO, 8 )
|
||||
AM_RANGE(0x01, 0x01) AM_READ_PORT("IN0") AM_WRITE(altair_out1_w)
|
||||
AM_RANGE(0x02, 0x02) AM_READ_PORT("IN1")
|
||||
AM_RANGE(0x03, 0x03) AM_WRITE(cdp1869_out3_w)
|
||||
AM_RANGE(0x04, 0x04) AM_READ_PORT("IN2") AM_WRITE(cdp1869_out4_w)
|
||||
AM_RANGE(0x05, 0x05) AM_WRITE(cdp1869_out5_w)
|
||||
AM_RANGE(0x06, 0x06) AM_WRITE(cdp1869_out6_w)
|
||||
AM_RANGE(0x07, 0x07) AM_WRITE(cdp1869_out7_w)
|
||||
AM_RANGE(0x03, 0x03) AM_DEVWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_out3_w)
|
||||
AM_RANGE(0x04, 0x04) AM_READ_PORT("IN2") AM_DEVWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_out4_w)
|
||||
AM_RANGE(0x05, 0x05) AM_DEVWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_out5_w)
|
||||
AM_RANGE(0x06, 0x06) AM_DEVWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_out6_w)
|
||||
AM_RANGE(0x07, 0x07) AM_DEVWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_out7_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
// Draco
|
||||
@ -280,18 +278,18 @@ ADDRESS_MAP_END
|
||||
static ADDRESS_MAP_START( draco_map, ADDRESS_SPACE_PROGRAM, 8 )
|
||||
AM_RANGE(0x0000, 0x3fff) AM_ROM
|
||||
AM_RANGE(0x8000, 0x83ff) AM_RAM AM_BASE(&generic_nvram) AM_SIZE(&generic_nvram_size)
|
||||
AM_RANGE(0xf400, 0xf7ff) AM_READWRITE(cidelsa_charram_r, cidelsa_charram_w)
|
||||
AM_RANGE(0xf800, 0xffff) AM_READWRITE(cdp1869_pageram_r, cdp1869_pageram_w)
|
||||
AM_RANGE(0xf400, 0xf7ff) AM_DEVREADWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_charram_r, cdp1869_charram_w)
|
||||
AM_RANGE(0xf800, 0xffff) AM_DEVREADWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_pageram_r, cdp1869_pageram_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( draco_io_map, ADDRESS_SPACE_IO, 8 )
|
||||
AM_RANGE(0x01, 0x01) AM_READ_PORT("IN0") AM_WRITE(draco_out1_w)
|
||||
AM_RANGE(0x02, 0x02) AM_READ_PORT("IN1")
|
||||
AM_RANGE(0x03, 0x03) AM_WRITE(cdp1869_out3_w)
|
||||
AM_RANGE(0x04, 0x04) AM_READ_PORT("IN2") AM_WRITE(cdp1869_out4_w)
|
||||
AM_RANGE(0x05, 0x05) AM_WRITE(cdp1869_out5_w)
|
||||
AM_RANGE(0x06, 0x06) AM_WRITE(cdp1869_out6_w)
|
||||
AM_RANGE(0x07, 0x07) AM_WRITE(cdp1869_out7_w)
|
||||
AM_RANGE(0x03, 0x03) AM_DEVWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_out3_w)
|
||||
AM_RANGE(0x04, 0x04) AM_READ_PORT("IN2") AM_DEVWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_out4_w)
|
||||
AM_RANGE(0x05, 0x05) AM_DEVWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_out5_w)
|
||||
AM_RANGE(0x06, 0x06) AM_DEVWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_out6_w)
|
||||
AM_RANGE(0x07, 0x07) AM_DEVWRITE(CDP1869_VIDEO, CDP1869_TAG, cdp1869_out7_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( draco_sound_map, ADDRESS_SPACE_PROGRAM, 8 )
|
||||
@ -311,12 +309,16 @@ ADDRESS_MAP_END
|
||||
|
||||
static CUSTOM_INPUT( cdp1869_pcb_r )
|
||||
{
|
||||
return cdp1869_pcb;
|
||||
cidelsa_state *state = machine->driver_data;
|
||||
|
||||
return state->cdp1869_pcb;
|
||||
}
|
||||
|
||||
static CUSTOM_INPUT( cdp1869_predisplay_r )
|
||||
{
|
||||
return cdp1869_prd;
|
||||
cidelsa_state *state = machine->driver_data;
|
||||
|
||||
return state->cdp1869_prd;
|
||||
}
|
||||
|
||||
static INPUT_PORTS_START( destryer )
|
||||
@ -461,118 +463,49 @@ static INPUT_PORTS_START( draco )
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN1 ) // M1
|
||||
INPUT_PORTS_END
|
||||
|
||||
/* Video Timer Callbacks */
|
||||
|
||||
static TIMER_CALLBACK( altair_prd_start )
|
||||
{
|
||||
cpunum_set_input_line(machine, 0, INPUT_LINE_IRQ0, ASSERT_LINE);
|
||||
cdp1869_prd = 1; // inverted
|
||||
}
|
||||
|
||||
static TIMER_CALLBACK( altair_prd_end )
|
||||
{
|
||||
cpunum_set_input_line(machine, 0, INPUT_LINE_IRQ0, CLEAR_LINE);
|
||||
cdp1869_prd = 0; // inverted
|
||||
}
|
||||
|
||||
static TIMER_CALLBACK( draco_prd_start )
|
||||
{
|
||||
cdp1869_prd = 0;
|
||||
}
|
||||
|
||||
static TIMER_CALLBACK( draco_prd_end )
|
||||
{
|
||||
cdp1869_prd = 1;
|
||||
}
|
||||
|
||||
/* Machine Start */
|
||||
|
||||
static TIMER_CALLBACK( set_cpu_mode )
|
||||
{
|
||||
cdp1802_mode = CDP1802_MODE_RUN;
|
||||
cidelsa_state *state = machine->driver_data;
|
||||
|
||||
state->cdp1802_mode = CDP1802_MODE_RUN;
|
||||
}
|
||||
|
||||
static UINT8 cidelsa_get_color_bits(UINT8 cramdata, UINT16 cramaddr, UINT16 pramaddr)
|
||||
static MACHINE_START( cidelsa )
|
||||
{
|
||||
int ccb0 = BIT(cramdata, 6);
|
||||
int ccb1 = BIT(cramdata, 7);
|
||||
int pcb = BIT(pcb_ram[cramaddr & 0x7ff], 0);
|
||||
cidelsa_state *state = machine->driver_data;
|
||||
|
||||
return (ccb0 << 2) + (ccb1 << 1) + pcb;
|
||||
}
|
||||
|
||||
static const CDP1869_interface destryer_CDP1869_interface =
|
||||
{
|
||||
CDP1869_PAL, // display format
|
||||
REGION_INVALID, // character RAM region
|
||||
0x800, // character RAM size
|
||||
0x400, // page RAM size
|
||||
cidelsa_get_color_bits // color callback function
|
||||
};
|
||||
|
||||
static const CDP1869_interface draco_CDP1869_interface =
|
||||
{
|
||||
CDP1869_PAL, // display format
|
||||
REGION_INVALID, // character RAM region
|
||||
0x800, // character RAM size
|
||||
0x800, // page RAM size
|
||||
cidelsa_get_color_bits // color callback function
|
||||
};
|
||||
|
||||
static MACHINE_START( destryer )
|
||||
{
|
||||
// allocate PCB RAM
|
||||
|
||||
pcb_ram = auto_malloc(0x800);
|
||||
|
||||
// configure CDP1869
|
||||
|
||||
cdp1869_configure(&destryer_CDP1869_interface);
|
||||
|
||||
// allocate one-shot CPU mode set timer
|
||||
// reset the CPU
|
||||
|
||||
state->cdp1802_mode = CDP1802_MODE_RESET;
|
||||
timer_set(ATTOTIME_IN_MSEC(200), NULL, 0, set_cpu_mode);
|
||||
|
||||
// save state support
|
||||
// register save states
|
||||
|
||||
state_save_register_global(cdp1802_mode);
|
||||
state_save_register_global_pointer(pcb_ram, 0x800);
|
||||
state_save_register_global(cdp1869_prd);
|
||||
state_save_register_global(cdp1869_pcb);
|
||||
state_save_register_global(state->cdp1802_mode);
|
||||
}
|
||||
|
||||
static MACHINE_START( draco )
|
||||
{
|
||||
// configure COP402 ROM banking
|
||||
cidelsa_state *state = machine->driver_data;
|
||||
|
||||
UINT8 *ROM = memory_region(REGION_CPU2);
|
||||
memory_configure_bank(1, 0, 2, &ROM[0x000], 0x400);
|
||||
MACHINE_START_CALL( cidelsa );
|
||||
|
||||
// allocate PCB RAM
|
||||
// COP402 memory banking
|
||||
|
||||
pcb_ram = auto_malloc(0x800);
|
||||
memory_configure_bank(1, 0, 2, memory_region(REGION_CPU2), 0x400);
|
||||
memory_set_bank(1, 0);
|
||||
|
||||
// configure CDP1869
|
||||
// register save states
|
||||
|
||||
cdp1869_configure(&draco_CDP1869_interface);
|
||||
|
||||
// allocate one-shot CPU mode set timer
|
||||
|
||||
timer_set(ATTOTIME_IN_MSEC(200), NULL, 0, set_cpu_mode);
|
||||
|
||||
// save state support
|
||||
|
||||
state_save_register_global(cdp1802_mode);
|
||||
state_save_register_global_pointer(pcb_ram, 0x800);
|
||||
state_save_register_global(cdp1869_prd);
|
||||
state_save_register_global(cdp1869_pcb);
|
||||
state_save_register_global(draco_sound);
|
||||
state_save_register_global(draco_ay_latch);
|
||||
state_save_register_global(state->draco_sound);
|
||||
state_save_register_global(state->draco_ay_latch);
|
||||
}
|
||||
|
||||
/* Machine Reset */
|
||||
|
||||
static MACHINE_RESET( destryer )
|
||||
static MACHINE_RESET( cidelsa )
|
||||
{
|
||||
cpunum_set_input_line(machine, 0, INPUT_LINE_RESET, PULSE_LINE);
|
||||
}
|
||||
@ -580,6 +513,8 @@ static MACHINE_RESET( destryer )
|
||||
/* Machine Drivers */
|
||||
|
||||
static MACHINE_DRIVER_START( destryer )
|
||||
MDRV_DRIVER_DATA(cidelsa_state)
|
||||
|
||||
// basic system hardware
|
||||
|
||||
MDRV_CPU_ADD(CDP1802, DESTRYER_CHR1)
|
||||
@ -587,23 +522,13 @@ static MACHINE_DRIVER_START( destryer )
|
||||
MDRV_CPU_IO_MAP(destryer_io_map, 0)
|
||||
MDRV_CPU_CONFIG(cidelsa_cdp1802_config)
|
||||
MDRV_NVRAM_HANDLER(generic_0fill)
|
||||
MDRV_MACHINE_START(destryer)
|
||||
MDRV_MACHINE_RESET(destryer)
|
||||
|
||||
MDRV_MACHINE_START(cidelsa)
|
||||
MDRV_MACHINE_RESET(cidelsa)
|
||||
|
||||
// video hardware
|
||||
|
||||
MDRV_PALETTE_LENGTH(8+64)
|
||||
MDRV_PALETTE_INIT(cdp1869)
|
||||
MDRV_VIDEO_START(cdp1869)
|
||||
MDRV_VIDEO_UPDATE(cdp1869)
|
||||
|
||||
MDRV_SCREEN_ADD("main", RASTER)
|
||||
MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
|
||||
MDRV_SCREEN_RAW_PARAMS(DESTRYER_CHR2, CDP1869_SCREEN_WIDTH, CDP1869_HBLANK_END, CDP1869_HBLANK_START, CDP1869_TOTAL_SCANLINES_PAL, CDP1869_SCANLINE_VBLANK_END_PAL, CDP1869_SCANLINE_VBLANK_START_PAL)
|
||||
MDRV_SCREEN_DEFAULT_POSITION(1.226, 0.012, 1.4, 0.044)
|
||||
|
||||
MDRV_TIMER_ADD_SCANLINE("prd_start", altair_prd_start, "main", CDP1869_SCANLINE_PREDISPLAY_START_PAL, CDP1869_TOTAL_SCANLINES_PAL)
|
||||
MDRV_TIMER_ADD_SCANLINE("prd_end", altair_prd_end, "main", CDP1869_SCANLINE_PREDISPLAY_END_PAL, CDP1869_TOTAL_SCANLINES_PAL)
|
||||
MDRV_IMPORT_FROM(destryer_video)
|
||||
|
||||
// sound hardware
|
||||
|
||||
@ -614,6 +539,8 @@ static MACHINE_DRIVER_START( destryer )
|
||||
MACHINE_DRIVER_END
|
||||
|
||||
static MACHINE_DRIVER_START( destryea )
|
||||
MDRV_DRIVER_DATA(cidelsa_state)
|
||||
|
||||
// basic system hardware
|
||||
|
||||
MDRV_CPU_ADD(CDP1802, DESTRYER_CHR1)
|
||||
@ -621,23 +548,13 @@ static MACHINE_DRIVER_START( destryea )
|
||||
MDRV_CPU_IO_MAP(destryer_io_map, 0)
|
||||
MDRV_CPU_CONFIG(cidelsa_cdp1802_config)
|
||||
MDRV_NVRAM_HANDLER(generic_0fill)
|
||||
MDRV_MACHINE_START(destryer)
|
||||
MDRV_MACHINE_RESET(destryer)
|
||||
|
||||
MDRV_MACHINE_START(cidelsa)
|
||||
MDRV_MACHINE_RESET(cidelsa)
|
||||
|
||||
// video hardware
|
||||
|
||||
MDRV_PALETTE_LENGTH(8+64)
|
||||
MDRV_PALETTE_INIT(cdp1869)
|
||||
MDRV_VIDEO_START(cdp1869)
|
||||
MDRV_VIDEO_UPDATE(cdp1869)
|
||||
|
||||
MDRV_SCREEN_ADD("main", RASTER)
|
||||
MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
|
||||
MDRV_SCREEN_RAW_PARAMS(DESTRYER_CHR2, CDP1869_SCREEN_WIDTH, CDP1869_HBLANK_END, CDP1869_HBLANK_START, CDP1869_TOTAL_SCANLINES_PAL, CDP1869_SCANLINE_VBLANK_END_PAL, CDP1869_SCANLINE_VBLANK_START_PAL)
|
||||
MDRV_SCREEN_DEFAULT_POSITION(1.226, 0.012, 1.4, 0.044)
|
||||
|
||||
MDRV_TIMER_ADD_SCANLINE("prd_start", altair_prd_start, "main", CDP1869_SCANLINE_PREDISPLAY_START_PAL, CDP1869_TOTAL_SCANLINES_PAL)
|
||||
MDRV_TIMER_ADD_SCANLINE("prd_end", altair_prd_end, "main", CDP1869_SCANLINE_PREDISPLAY_END_PAL, CDP1869_TOTAL_SCANLINES_PAL)
|
||||
MDRV_IMPORT_FROM(destryer_video)
|
||||
|
||||
// sound hardware
|
||||
|
||||
@ -648,29 +565,21 @@ static MACHINE_DRIVER_START( destryea )
|
||||
MACHINE_DRIVER_END
|
||||
|
||||
static MACHINE_DRIVER_START( altair )
|
||||
MDRV_DRIVER_DATA(cidelsa_state)
|
||||
|
||||
// basic system hardware
|
||||
|
||||
MDRV_CPU_ADD(CDP1802, ALTAIR_CHR1)
|
||||
MDRV_CPU_PROGRAM_MAP(altair_map, 0)
|
||||
MDRV_CPU_IO_MAP(altair_io_map, 0)
|
||||
MDRV_CPU_CONFIG(cidelsa_cdp1802_config)
|
||||
MDRV_MACHINE_START(destryer)
|
||||
MDRV_MACHINE_RESET(destryer)
|
||||
|
||||
MDRV_MACHINE_START(cidelsa)
|
||||
MDRV_MACHINE_RESET(cidelsa)
|
||||
|
||||
// video hardware
|
||||
|
||||
MDRV_PALETTE_LENGTH(8+64)
|
||||
MDRV_PALETTE_INIT(cdp1869)
|
||||
MDRV_VIDEO_START(cdp1869)
|
||||
MDRV_VIDEO_UPDATE(cdp1869)
|
||||
|
||||
MDRV_SCREEN_ADD("main", RASTER)
|
||||
MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
|
||||
MDRV_SCREEN_RAW_PARAMS(ALTAIR_CHR2, CDP1869_SCREEN_WIDTH, CDP1869_HBLANK_END, CDP1869_HBLANK_START, CDP1869_TOTAL_SCANLINES_PAL, CDP1869_SCANLINE_VBLANK_END_PAL, CDP1869_SCANLINE_VBLANK_START_PAL)
|
||||
MDRV_SCREEN_DEFAULT_POSITION(1.226, 0.012, 1.4, 0.044)
|
||||
|
||||
MDRV_TIMER_ADD_SCANLINE("prd_start", altair_prd_start, "main", CDP1869_SCANLINE_PREDISPLAY_START_PAL, CDP1869_TOTAL_SCANLINES_PAL)
|
||||
MDRV_TIMER_ADD_SCANLINE("prd_end", altair_prd_end, "main", CDP1869_SCANLINE_PREDISPLAY_END_PAL, CDP1869_TOTAL_SCANLINES_PAL)
|
||||
MDRV_IMPORT_FROM(altair_video)
|
||||
|
||||
// sound hardware
|
||||
|
||||
@ -681,6 +590,8 @@ static MACHINE_DRIVER_START( altair )
|
||||
MACHINE_DRIVER_END
|
||||
|
||||
static MACHINE_DRIVER_START( draco )
|
||||
MDRV_DRIVER_DATA(cidelsa_state)
|
||||
|
||||
// basic system hardware
|
||||
|
||||
MDRV_CPU_ADD(CDP1802, DRACO_CHR1)
|
||||
@ -688,8 +599,9 @@ static MACHINE_DRIVER_START( draco )
|
||||
MDRV_CPU_IO_MAP(draco_io_map, 0)
|
||||
MDRV_CPU_CONFIG(cidelsa_cdp1802_config)
|
||||
MDRV_NVRAM_HANDLER(generic_0fill)
|
||||
|
||||
MDRV_MACHINE_START(draco)
|
||||
MDRV_MACHINE_RESET(destryer)
|
||||
MDRV_MACHINE_RESET(cidelsa)
|
||||
|
||||
MDRV_CPU_ADD(COP420, DRACO_SND_CHR1) // COP402N
|
||||
MDRV_CPU_PROGRAM_MAP(draco_sound_map, 0)
|
||||
@ -697,18 +609,7 @@ static MACHINE_DRIVER_START( draco )
|
||||
|
||||
// video hardware
|
||||
|
||||
MDRV_PALETTE_LENGTH(8+64)
|
||||
MDRV_PALETTE_INIT(cdp1869)
|
||||
MDRV_VIDEO_START(cdp1869)
|
||||
MDRV_VIDEO_UPDATE(cdp1869)
|
||||
|
||||
MDRV_SCREEN_ADD("main", RASTER)
|
||||
MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
|
||||
MDRV_SCREEN_RAW_PARAMS(DRACO_CHR2, CDP1869_SCREEN_WIDTH, CDP1869_HBLANK_END, CDP1869_HBLANK_START, CDP1869_TOTAL_SCANLINES_PAL, CDP1869_SCANLINE_VBLANK_END_PAL, CDP1869_SCANLINE_VBLANK_START_PAL)
|
||||
MDRV_SCREEN_DEFAULT_POSITION(1.226, 0.012, 1.360, 0.024)
|
||||
|
||||
MDRV_TIMER_ADD_SCANLINE("prd_start", draco_prd_start, "main", CDP1869_SCANLINE_PREDISPLAY_START_PAL, CDP1869_TOTAL_SCANLINES_PAL)
|
||||
MDRV_TIMER_ADD_SCANLINE("prd_end", draco_prd_end, "main", CDP1869_SCANLINE_PREDISPLAY_END_PAL, CDP1869_TOTAL_SCANLINES_PAL)
|
||||
MDRV_IMPORT_FROM(draco_video)
|
||||
|
||||
// sound hardware
|
||||
|
||||
@ -768,7 +669,7 @@ ROM_END
|
||||
|
||||
/* Game Drivers */
|
||||
|
||||
GAME( 1980, destryer, 0, destryer, destryer, 0, ROT90, "Cidelsa", "Destroyer (Cidelsa) (set 1)", GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1980, destryea, destryer, destryea, destryer, 0, ROT90, "Cidelsa", "Destroyer (Cidelsa) (set 2)", GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1981, altair, 0, altair, altair, 0, ROT90, "Cidelsa", "Altair", GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1980, destryer, 0, destryer, destryer, 0, ROT90, "Cidelsa", "Destroyer (Cidelsa) (set 1)", GAME_IMPERFECT_COLORS | GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1980, destryea, destryer, destryea, destryer, 0, ROT90, "Cidelsa", "Destroyer (Cidelsa) (set 2)", GAME_IMPERFECT_COLORS | GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1981, altair, 0, altair, altair, 0, ROT90, "Cidelsa", "Altair", GAME_IMPERFECT_COLORS | GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1981, draco, 0, draco, draco, 0, ROT90, "Cidelsa", "Draco", GAME_IMPERFECT_COLORS | GAME_IMPERFECT_SOUND | GAME_SUPPORTS_SAVE )
|
||||
|
||||
38
src/mame/includes/cidelsa.h
Normal file
38
src/mame/includes/cidelsa.h
Normal file
@ -0,0 +1,38 @@
|
||||
#ifndef __CIDELSA__
|
||||
#define __CIDELSA__
|
||||
|
||||
#include "video/cdp1869.h"
|
||||
|
||||
#define DESTRYER_CHR1 3579000.0 // unverified
|
||||
#define DESTRYER_CHR2 XTAL_5_7143MHz
|
||||
#define ALTAIR_CHR1 3579000.0 // unverified
|
||||
#define ALTAIR_CHR2 CDP1869_DOT_CLK_PAL // unverified
|
||||
#define DRACO_CHR1 XTAL_4_43361MHz
|
||||
#define DRACO_CHR2 CDP1869_DOT_CLK_PAL // unverified
|
||||
#define DRACO_SND_CHR1 XTAL_2_01216MHz
|
||||
|
||||
typedef struct _cidelsa_state cidelsa_state;
|
||||
|
||||
struct _cidelsa_state
|
||||
{
|
||||
int cdp1802_mode;
|
||||
int cdp1802_q;
|
||||
|
||||
int cdp1869_prd;
|
||||
int cdp1869_pcb;
|
||||
|
||||
int draco_sound;
|
||||
int draco_ay_latch;
|
||||
|
||||
UINT8 *pageram;
|
||||
UINT8 *pcbram;
|
||||
UINT8 *charram;
|
||||
};
|
||||
|
||||
/*----------- defined in video/cidelsa.c -----------*/
|
||||
|
||||
MACHINE_DRIVER_EXTERN( destryer_video );
|
||||
MACHINE_DRIVER_EXTERN( altair_video );
|
||||
MACHINE_DRIVER_EXTERN( draco_video );
|
||||
|
||||
#endif
|
||||
@ -1515,7 +1515,7 @@ $(MAMEOBJ)/misc.a: \
|
||||
$(DRIVERS)/carrera.o \
|
||||
$(DRIVERS)/cave.o $(VIDEO)/cave.o \
|
||||
$(DRIVERS)/cherrym.o \
|
||||
$(DRIVERS)/cidelsa.o \
|
||||
$(DRIVERS)/cidelsa.o $(VIDEO)/cidelsa.o \
|
||||
$(DRIVERS)/coinmstr.o \
|
||||
$(DRIVERS)/comebaby.o \
|
||||
$(DRIVERS)/coolpool.o \
|
||||
|
||||
298
src/mame/video/cidelsa.c
Normal file
298
src/mame/video/cidelsa.c
Normal file
@ -0,0 +1,298 @@
|
||||
#include "driver.h"
|
||||
#include "video/cdp1869.h"
|
||||
#include "cidelsa.h"
|
||||
|
||||
#define CIDELSA_PAGERAM_SIZE 0x400
|
||||
#define DRACO_PAGERAM_SIZE 0x800
|
||||
#define CIDELSA_CHARRAM_SIZE 0x800
|
||||
|
||||
#define CIDELSA_PAGERAM_MASK 0x3ff
|
||||
#define DRACO_PAGERAM_MASK 0x7ff
|
||||
#define CIDELSA_CHARRAM_MASK 0x7ff
|
||||
|
||||
#define SCREEN_TAG "main"
|
||||
#define CDP1869_TAG "cdp1869"
|
||||
|
||||
/* Page RAM Access */
|
||||
|
||||
static CDP1869_PAGE_RAM_READ(cidelsa_pageram_r)
|
||||
{
|
||||
cidelsa_state *state = device->machine->driver_data;
|
||||
|
||||
UINT16 addr = pma & CIDELSA_PAGERAM_MASK;
|
||||
|
||||
if (BIT(pma, 10))
|
||||
{
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
return state->pageram[addr];
|
||||
}
|
||||
|
||||
static CDP1869_PAGE_RAM_WRITE(cidelsa_pageram_w)
|
||||
{
|
||||
cidelsa_state *state = device->machine->driver_data;
|
||||
|
||||
UINT16 addr = pma & CIDELSA_PAGERAM_MASK;
|
||||
|
||||
if (BIT(pma, 10))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
state->pageram[addr] = data;
|
||||
}
|
||||
|
||||
static CDP1869_PAGE_RAM_READ(draco_pageram_r)
|
||||
{
|
||||
cidelsa_state *state = device->machine->driver_data;
|
||||
|
||||
UINT16 addr = pma & DRACO_PAGERAM_MASK;
|
||||
|
||||
return state->pageram[addr];
|
||||
}
|
||||
|
||||
static CDP1869_PAGE_RAM_WRITE(draco_pageram_w)
|
||||
{
|
||||
cidelsa_state *state = device->machine->driver_data;
|
||||
|
||||
UINT16 addr = pma & DRACO_PAGERAM_MASK;
|
||||
|
||||
state->pageram[addr] = data;
|
||||
}
|
||||
|
||||
/* Character RAM Access */
|
||||
|
||||
static CDP1869_CHAR_RAM_READ(cidelsa_charram_r)
|
||||
{
|
||||
cidelsa_state *state = device->machine->driver_data;
|
||||
|
||||
UINT8 column = BIT(pma, 10) ? 0xff : state->pageram[pma & CIDELSA_PAGERAM_MASK];
|
||||
UINT16 addr = ((column << 3) | (cma & 0x07)) & CIDELSA_CHARRAM_MASK;
|
||||
|
||||
UINT8 data = state->charram[addr];
|
||||
state->cdp1869_pcb = state->pcbram[addr];
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
static CDP1869_CHAR_RAM_WRITE(cidelsa_charram_w)
|
||||
{
|
||||
cidelsa_state *state = device->machine->driver_data;
|
||||
|
||||
UINT8 column = BIT(pma, 10) ? 0xff : state->pageram[pma & CIDELSA_PAGERAM_MASK];
|
||||
UINT16 addr = ((column << 3) | (cma & 0x07)) & CIDELSA_CHARRAM_MASK;
|
||||
|
||||
state->charram[addr] = data;
|
||||
state->pcbram[addr] = state->cdp1802_q;
|
||||
}
|
||||
|
||||
static CDP1869_CHAR_RAM_READ(draco_charram_r)
|
||||
{
|
||||
cidelsa_state *state = device->machine->driver_data;
|
||||
|
||||
UINT8 column = state->pageram[pma & DRACO_PAGERAM_MASK];
|
||||
UINT16 addr = ((column << 3) | (cma & 0x07)) & CIDELSA_CHARRAM_MASK;
|
||||
|
||||
UINT8 data = state->charram[addr];
|
||||
state->cdp1869_pcb = state->pcbram[addr];
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
static CDP1869_CHAR_RAM_WRITE(draco_charram_w)
|
||||
{
|
||||
cidelsa_state *state = device->machine->driver_data;
|
||||
|
||||
UINT8 column = state->pageram[pma & DRACO_PAGERAM_MASK];
|
||||
UINT16 addr = ((column << 3) | (cma & 0x07)) & CIDELSA_CHARRAM_MASK;
|
||||
|
||||
state->charram[addr] = data;
|
||||
state->pcbram[addr] = state->cdp1802_q;
|
||||
}
|
||||
|
||||
/* Page Color Bit Access */
|
||||
|
||||
static CDP1869_PCB_READ(cidelsa_pcb_r)
|
||||
{
|
||||
cidelsa_state *state = device->machine->driver_data;
|
||||
|
||||
UINT8 column = state->pageram[pma & CIDELSA_PAGERAM_MASK];
|
||||
UINT16 addr = ((column << 3) | (cma & 0x07)) & CIDELSA_CHARRAM_MASK;
|
||||
|
||||
return state->pcbram[addr];
|
||||
}
|
||||
|
||||
static CDP1869_PCB_READ(draco_pcb_r)
|
||||
{
|
||||
cidelsa_state *state = device->machine->driver_data;
|
||||
|
||||
UINT8 column = state->pageram[pma & DRACO_PAGERAM_MASK];
|
||||
UINT16 addr = ((column << 3) | (cma & 0x07)) & CIDELSA_CHARRAM_MASK;
|
||||
|
||||
return state->pcbram[addr];
|
||||
}
|
||||
|
||||
/* Predisplay Changed Handler */
|
||||
|
||||
static CDP1869_ON_PRD_CHANGED(cidelsa_prd_changed)
|
||||
{
|
||||
cidelsa_state *state = device->machine->driver_data;
|
||||
|
||||
// PRD is inverted
|
||||
|
||||
cpunum_set_input_line(device->machine, 0, INPUT_LINE_IRQ0, !prd);
|
||||
state->cdp1869_prd = !prd;
|
||||
}
|
||||
|
||||
static CDP1869_ON_PRD_CHANGED(draco_prd_changed)
|
||||
{
|
||||
cidelsa_state *state = device->machine->driver_data;
|
||||
|
||||
state->cdp1869_prd = prd;
|
||||
}
|
||||
|
||||
/* CDP1869 Interface */
|
||||
|
||||
static const cdp1869_interface destryer_cdp1869_intf =
|
||||
{
|
||||
SCREEN_TAG,
|
||||
DESTRYER_CHR2,
|
||||
0,
|
||||
CDP1869_PAL,
|
||||
cidelsa_pageram_r,
|
||||
cidelsa_pageram_w,
|
||||
cidelsa_pcb_r,
|
||||
cidelsa_charram_r,
|
||||
cidelsa_charram_w,
|
||||
cidelsa_prd_changed,
|
||||
};
|
||||
|
||||
static const cdp1869_interface altair_cdp1869_intf =
|
||||
{
|
||||
SCREEN_TAG,
|
||||
ALTAIR_CHR2,
|
||||
0,
|
||||
CDP1869_PAL,
|
||||
cidelsa_pageram_r,
|
||||
cidelsa_pageram_w,
|
||||
cidelsa_pcb_r,
|
||||
cidelsa_charram_r,
|
||||
cidelsa_charram_w,
|
||||
cidelsa_prd_changed,
|
||||
};
|
||||
|
||||
static const cdp1869_interface draco_cdp1869_intf =
|
||||
{
|
||||
SCREEN_TAG,
|
||||
DRACO_CHR2,
|
||||
0,
|
||||
CDP1869_PAL,
|
||||
draco_pageram_r,
|
||||
draco_pageram_w,
|
||||
draco_pcb_r,
|
||||
draco_charram_r,
|
||||
draco_charram_w,
|
||||
draco_prd_changed,
|
||||
};
|
||||
|
||||
/* Video Start */
|
||||
|
||||
static VIDEO_START(cidelsa)
|
||||
{
|
||||
cidelsa_state *state = machine->driver_data;
|
||||
|
||||
// allocate memory
|
||||
|
||||
state->pageram = auto_malloc(CIDELSA_PAGERAM_SIZE);
|
||||
state->pcbram = auto_malloc(CIDELSA_CHARRAM_SIZE);
|
||||
state->charram = auto_malloc(CIDELSA_CHARRAM_SIZE);
|
||||
|
||||
// register for save state
|
||||
|
||||
state_save_register_global(state->cdp1869_prd);
|
||||
state_save_register_global(state->cdp1869_pcb);
|
||||
state_save_register_global_pointer(state->pageram, CIDELSA_PAGERAM_SIZE);
|
||||
state_save_register_global_pointer(state->pcbram, CIDELSA_CHARRAM_SIZE);
|
||||
state_save_register_global_pointer(state->charram, CIDELSA_CHARRAM_SIZE);
|
||||
}
|
||||
|
||||
static VIDEO_START(draco)
|
||||
{
|
||||
cidelsa_state *state = machine->driver_data;
|
||||
|
||||
// allocate memory
|
||||
|
||||
state->pageram = auto_malloc(DRACO_PAGERAM_SIZE);
|
||||
state->pcbram = auto_malloc(CIDELSA_CHARRAM_SIZE);
|
||||
state->charram = auto_malloc(CIDELSA_CHARRAM_SIZE);
|
||||
|
||||
// register for save state
|
||||
|
||||
state_save_register_global(state->cdp1869_prd);
|
||||
state_save_register_global(state->cdp1869_pcb);
|
||||
state_save_register_global_pointer(state->pageram, DRACO_PAGERAM_SIZE);
|
||||
state_save_register_global_pointer(state->pcbram, CIDELSA_CHARRAM_SIZE);
|
||||
state_save_register_global_pointer(state->charram, CIDELSA_CHARRAM_SIZE);
|
||||
}
|
||||
|
||||
/* Video Update */
|
||||
|
||||
static VIDEO_UPDATE( cidelsa )
|
||||
{
|
||||
const device_config *cdp1869 = device_list_find_by_tag(screen->machine->config->devicelist, CDP1869_VIDEO, CDP1869_TAG);
|
||||
|
||||
cdp1869_update(cdp1869, bitmap, cliprect);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Machine Drivers */
|
||||
|
||||
MACHINE_DRIVER_START( destryer_video )
|
||||
MDRV_PALETTE_LENGTH(CDP1869_PALETTE_LENGTH)
|
||||
MDRV_PALETTE_INIT(cdp1869)
|
||||
|
||||
MDRV_VIDEO_START(cidelsa)
|
||||
MDRV_VIDEO_UPDATE(cidelsa)
|
||||
|
||||
MDRV_SCREEN_ADD(SCREEN_TAG, RASTER)
|
||||
MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
|
||||
MDRV_SCREEN_RAW_PARAMS(DESTRYER_CHR2, CDP1869_SCREEN_WIDTH, CDP1869_HBLANK_END, CDP1869_HBLANK_START, CDP1869_TOTAL_SCANLINES_PAL, CDP1869_SCANLINE_VBLANK_END_PAL, CDP1869_SCANLINE_VBLANK_START_PAL)
|
||||
MDRV_SCREEN_DEFAULT_POSITION(1.226, 0.012, 1.4, 0.044)
|
||||
|
||||
MDRV_DEVICE_ADD(CDP1869_TAG, CDP1869_VIDEO)
|
||||
MDRV_DEVICE_CONFIG(destryer_cdp1869_intf)
|
||||
MACHINE_DRIVER_END
|
||||
|
||||
MACHINE_DRIVER_START( altair_video )
|
||||
MDRV_PALETTE_LENGTH(CDP1869_PALETTE_LENGTH)
|
||||
MDRV_PALETTE_INIT(cdp1869)
|
||||
|
||||
MDRV_VIDEO_START(cidelsa)
|
||||
MDRV_VIDEO_UPDATE(cidelsa)
|
||||
|
||||
MDRV_SCREEN_ADD(SCREEN_TAG, RASTER)
|
||||
MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
|
||||
MDRV_SCREEN_RAW_PARAMS(ALTAIR_CHR2, CDP1869_SCREEN_WIDTH, CDP1869_HBLANK_END, CDP1869_HBLANK_START, CDP1869_TOTAL_SCANLINES_PAL, CDP1869_SCANLINE_VBLANK_END_PAL, CDP1869_SCANLINE_VBLANK_START_PAL)
|
||||
MDRV_SCREEN_DEFAULT_POSITION(1.226, 0.012, 1.4, 0.044)
|
||||
|
||||
MDRV_DEVICE_ADD(CDP1869_TAG, CDP1869_VIDEO)
|
||||
MDRV_DEVICE_CONFIG(altair_cdp1869_intf)
|
||||
MACHINE_DRIVER_END
|
||||
|
||||
MACHINE_DRIVER_START( draco_video )
|
||||
MDRV_PALETTE_LENGTH(CDP1869_PALETTE_LENGTH)
|
||||
MDRV_PALETTE_INIT(cdp1869)
|
||||
|
||||
MDRV_VIDEO_START(draco)
|
||||
MDRV_VIDEO_UPDATE(cidelsa)
|
||||
|
||||
MDRV_SCREEN_ADD(SCREEN_TAG, RASTER)
|
||||
MDRV_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
|
||||
MDRV_SCREEN_RAW_PARAMS(DRACO_CHR2, CDP1869_SCREEN_WIDTH, CDP1869_HBLANK_END, CDP1869_HBLANK_START, CDP1869_TOTAL_SCANLINES_PAL, CDP1869_SCANLINE_VBLANK_END_PAL, CDP1869_SCANLINE_VBLANK_START_PAL)
|
||||
MDRV_SCREEN_DEFAULT_POSITION(1.226, 0.012, 1.360, 0.024)
|
||||
|
||||
MDRV_DEVICE_ADD(CDP1869_TAG, CDP1869_VIDEO)
|
||||
MDRV_DEVICE_CONFIG(draco_cdp1869_intf)
|
||||
MACHINE_DRIVER_END
|
||||
Loading…
Reference in New Issue
Block a user