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chessmachine: bootstrap more likely like this anyway (nw)

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This commit is contained in:
hap 2019-06-03 00:35:10 +02:00
parent 8dd2834cf0
commit 195eda21cc
4 changed files with 43 additions and 15 deletions
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2
src/devices/bus/isa/chessmdr.cpp
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@ -63,7 +63,7 @@ void isa8_chessmdr_device::device_reset()
static INPUT_PORTS_START( chessmdr )
PORT_START("DSW") // DIP switch on the ISA card PCB, installer shows range 0x110-0x3D0
PORT_DIPNAME( 0x0f, 0x08, "I/O Port Address" ) PORT_DIPLOCATION("CM_SW1:1,2,3,4")
PORT_DIPNAME( 0x0f, 0x09, "I/O Port Address" ) PORT_DIPLOCATION("CMDR_SW1:1,2,3,4")
PORT_DIPSETTING( 0x00, "0x010 (Invalid)" )
PORT_DIPSETTING( 0x01, "0x050 (Invalid)" )
PORT_DIPSETTING( 0x02, "0x090 (Invalid)" )

2
src/devices/bus/isa/chessmsr.cpp
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@ -87,7 +87,7 @@ void isa8_chessmsr_device::device_reset_after_children()
static INPUT_PORTS_START( chessmsr )
PORT_START("DSW") // DIP switch on the ISA card PCB, installer shows range 0x110-0x3D0
PORT_DIPNAME( 0x0f, 0x08, "I/O Port Address" ) PORT_DIPLOCATION("CM_SW1:1,2,3,4")
PORT_DIPNAME( 0x0f, 0x08, "I/O Port Address" ) PORT_DIPLOCATION("CMSR_SW1:1,2,3,4")
PORT_DIPSETTING( 0x00, "0x010 (Invalid)" )
PORT_DIPSETTING( 0x01, "0x050 (Invalid)" )
PORT_DIPSETTING( 0x02, "0x090 (Invalid)" )

38
src/devices/machine/chessmachine.cpp
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@ -26,6 +26,7 @@ probably went for this solution to get optimum possible speed for each module.
TODO:
- is interrupt handling correct?
- timer shouldn't be needed for disabling bootstrap, real ARM has already read the next opcode
*/
@ -43,6 +44,8 @@ chessmachine_device::chessmachine_device(const machine_config &mconfig, const ch
device_t(mconfig, CHESSMACHINE, tag, owner, clock),
m_maincpu(*this, "maincpu"),
m_bootstrap(*this, "bootstrap"),
m_ram(*this, "ram"),
m_disable_bootstrap(*this, "disable_bootstrap"),
m_data_out(*this)
{ }
@ -57,8 +60,12 @@ void chessmachine_device::device_start()
// resolve callbacks
m_data_out.resolve_safe();
// zerofill, register for savestates
// zerofill
m_bootstrap_enabled = false;
m_latch[0] = m_latch[1] = 0;
// register for savestates
save_item(NAME(m_bootstrap_enabled));
save_item(NAME(m_latch));
}
@ -96,11 +103,7 @@ void chessmachine_device::reset_w(int state)
m_maincpu->set_input_line(INPUT_LINE_RESET, state ? ASSERT_LINE : CLEAR_LINE);
if (state)
{
// send bootstrap
for (int i = 0; i < 0x80; i++)
m_maincpu->space(AS_PROGRAM).write_byte(i, m_bootstrap[i]);
}
m_bootstrap_enabled = true;
}
@ -109,11 +112,26 @@ void chessmachine_device::reset_w(int state)
// internal
//-------------------------------------------------
u32 chessmachine_device::bootstrap_r(offs_t offset)
{
return (m_bootstrap_enabled) ? m_bootstrap[offset] : m_ram[offset];
}
u32 chessmachine_device::disable_bootstrap_r()
{
// disconnect bootstrap rom from the bus after next opcode
if (m_bootstrap_enabled && !m_disable_bootstrap->enabled() && !machine().side_effects_disabled())
m_disable_bootstrap->adjust(m_maincpu->cycles_to_attotime(5));
return 0;
}
void chessmachine_device::main_map(address_map &map)
{
map(0x00000000, 0x000fffff).ram();
map(0x00000000, 0x000fffff).ram().share("ram");
map(0x00000000, 0x0000007f).r(FUNC(chessmachine_device::bootstrap_r));
map(0x00400000, 0x00400000).mirror(0x003ffffc).rw(FUNC(chessmachine_device::internal_r), FUNC(chessmachine_device::internal_w));
//map(0x01800000, 0x01800003).nopr(); // disconnect bootstrap?
map(0x01800000, 0x01800003).r(FUNC(chessmachine_device::disable_bootstrap_r));
}
void chessmachine_device::device_add_mconfig(machine_config &config)
@ -121,6 +139,8 @@ void chessmachine_device::device_add_mconfig(machine_config &config)
ARM(config, m_maincpu, DERIVED_CLOCK(1,1));
m_maincpu->set_addrmap(AS_PROGRAM, &chessmachine_device::main_map);
m_maincpu->set_copro_type(arm_cpu_device::copro_type::VL86C020);
TIMER(config, "disable_bootstrap").configure_generic(FUNC(chessmachine_device::disable_bootstrap));
}
@ -130,7 +150,7 @@ void chessmachine_device::device_add_mconfig(machine_config &config)
//-------------------------------------------------
ROM_START( chessmachine )
ROM_REGION( 0x80, "bootstrap", 0 )
ROM_REGION32_LE( 0x80, "bootstrap", 0 )
ROM_LOAD32_BYTE( "74s288.1", 0x00, 0x20, CRC(284114e2) SHA1(df4037536d505d7240bb1d70dc58f59a34ab77b4) )
ROM_LOAD32_BYTE( "74s288.2", 0x01, 0x20, CRC(9f239c75) SHA1(aafaf30dac90f36b01f9ee89903649fc4ea0480d) )
ROM_LOAD32_BYTE( "74s288.3", 0x02, 0x20, CRC(0455360b) SHA1(f1486142330f2c39a4d6c479646030d31443d1c8) )

16
src/devices/machine/chessmachine.h
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@ -12,6 +12,7 @@
#pragma once
#include "cpu/arm/arm.h"
#include "machine/timer.h"
class chessmachine_device : public device_t
@ -31,14 +32,16 @@ public:
protected:
// device-level overrides
virtual void device_start() override;
virtual void device_reset_after_children() override { m_maincpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE); }
virtual void device_reset_after_children() override { reset_w(1); }
virtual void device_add_mconfig(machine_config &config) override;
virtual const tiny_rom_entry *device_rom_region() const override;
private:
required_device<arm_cpu_device> m_maincpu;
required_region_ptr<u8> m_bootstrap;
required_region_ptr<u32> m_bootstrap;
required_shared_ptr<u32> m_ram;
required_device<timer_device> m_disable_bootstrap;
devcb_write_line m_data_out;
@ -46,8 +49,13 @@ private:
void sync0_callback(void *ptr, s32 param);
void sync1_callback(void *ptr, s32 param);
DECLARE_READ8_MEMBER(internal_r) { return m_latch[0]; }
DECLARE_WRITE8_MEMBER(internal_w) { m_latch[1] = data & 1; m_data_out(m_latch[1]); }
bool m_bootstrap_enabled;
TIMER_DEVICE_CALLBACK_MEMBER(disable_bootstrap) { m_bootstrap_enabled = false; }
u32 disable_bootstrap_r();
u32 bootstrap_r(offs_t offset);
u8 internal_r() { return m_latch[0]; }
void internal_w(u8 data) { m_latch[1] = data & 1; m_data_out(m_latch[1]); }
void main_map(address_map &map);
};