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lindbergh: Fake pit and real pci bridges [O. Galibert]

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This commit is contained in:
Olivier Galibert 2014-12-07 22:35:44 +01:00
parent 68228c5e21
commit 19f96fbb50
6 changed files with 403 additions and 48 deletions
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8
src/emu/machine/i6300esb.c
View File

@ -83,11 +83,12 @@ DEVICE_ADDRESS_MAP_START(internal_io_map, 32, i6300esb_lpc_device)
AM_RANGE(0x00ec, 0x00ef) AM_WRITE8( nop_w, 0x0000ff00) // Non-existing, used for delays by the bios/os
ADDRESS_MAP_END
i6300esb_lpc_device::i6300esb_lpc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: pci_device(mconfig, I6300ESB_LPC, "i6300ESB southbridge ISA/LPC bridge", tag, owner, clock, "i6300esb_lpc", __FILE__),
acpi(*this, "acpi"),
rtc (*this, "rtc")
acpi(*this, "acpi"),
rtc (*this, "rtc"),
pit (*this, "pit")
{
}
@ -749,4 +750,5 @@ void i6300esb_lpc_device::map_extra(UINT64 memory_window_start, UINT64 memory_wi
rtc->map_device(memory_window_start, memory_window_end, 0, memory_space, io_window_start, io_window_end, 0, io_space);
if(rtc_conf & 4)
rtc->map_extdevice(memory_window_start, memory_window_end, 0, memory_space, io_window_start, io_window_end, 0, io_space);
pit->map_device(memory_window_start, memory_window_end, 0, memory_space, io_window_start, io_window_end, 0, io_space);
}

2
src/emu/machine/i6300esb.h
View File

@ -6,6 +6,7 @@
#include "pci.h"
#include "lpc-acpi.h"
#include "lpc-rtc.h"
#include "lpc-pit.h"
#define MCFG_I6300ESB_LPC_ADD(_tag) \
MCFG_PCI_DEVICE_ADD(_tag, I6300ESB_LPC, 0x808625a1, 0x02, 0x060100, 0x00000000)
@ -31,6 +32,7 @@ protected:
private:
required_device<lpc_acpi_device> acpi;
required_device<lpc_rtc_device> rtc;
required_device<lpc_pit_device> pit;
DECLARE_ADDRESS_MAP(internal_io_map, 32);

1
src/emu/machine/machine.mak
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@ -1263,6 +1263,7 @@ MACHINEOBJS += $(MACHINEOBJ)/i6300esb.o
MACHINEOBJS += $(MACHINEOBJ)/lpc.o
MACHINEOBJS += $(MACHINEOBJ)/lpc-acpi.o
MACHINEOBJS += $(MACHINEOBJ)/lpc-rtc.o
MACHINEOBJS += $(MACHINEOBJ)/lpc-pit.o
endif
#-------------------------------------------------

371
src/emu/machine/pci.c
View File

@ -4,22 +4,55 @@ const device_type PCI_ROOT = &device_creator<pci_root_device>;
const device_type PCI_BRIDGE = &device_creator<pci_bridge_device>;
DEVICE_ADDRESS_MAP_START(config_map, 32, pci_device)
AM_RANGE(0x00, 0x03) AM_READ16 (vendor_r, 0x0000ffff)
AM_RANGE(0x00, 0x03) AM_READ16 (device_r, 0xffff0000)
AM_RANGE(0x04, 0x07) AM_READWRITE16(command_r, command_w, 0x0000ffff)
AM_RANGE(0x04, 0x07) AM_READ16 (status_r, 0xffff0000)
AM_RANGE(0x00, 0x03) AM_READ16 (vendor_r, 0x0000ffff)
AM_RANGE(0x00, 0x03) AM_READ16 (device_r, 0xffff0000)
AM_RANGE(0x04, 0x07) AM_READWRITE16(command_r, command_w, 0x0000ffff)
AM_RANGE(0x04, 0x07) AM_READ16 (status_r, 0xffff0000)
AM_RANGE(0x08, 0x0b) AM_READ (class_rev_r)
AM_RANGE(0x0c, 0x0f) AM_READ8 (cache_line_size_r, 0x000000ff)
AM_RANGE(0x0c, 0x0f) AM_READ8 (latency_timer_r, 0x0000ff00)
AM_RANGE(0x0c, 0x0f) AM_READ8 (header_type_r, 0x00ff0000)
AM_RANGE(0x0c, 0x0f) AM_READ8 (bist_r, 0xff000000)
AM_RANGE(0x10, 0x27) AM_READWRITE (address_base_r, address_base_w)
AM_RANGE(0x0c, 0x0f) AM_READ8 (cache_line_size_r, 0x000000ff)
AM_RANGE(0x0c, 0x0f) AM_READ8 (latency_timer_r, 0x0000ff00)
AM_RANGE(0x0c, 0x0f) AM_READ8 (header_type_r, 0x00ff0000)
AM_RANGE(0x0c, 0x0f) AM_READ8 (bist_r, 0xff000000)
AM_RANGE(0x10, 0x27) AM_READWRITE (address_base_r, address_base_w)
AM_RANGE(0x2c, 0x2f) AM_READ16 (subvendor_r, 0x0000ffff)
AM_RANGE(0x2c, 0x2f) AM_READ16 (subsystem_r, 0xffff0000)
AM_RANGE(0x2c, 0x2f) AM_READ16 (subvendor_r, 0x0000ffff)
AM_RANGE(0x2c, 0x2f) AM_READ16 (subsystem_r, 0xffff0000)
AM_RANGE(0x2c, 0x2f) AM_WRITENOP
AM_RANGE(0x34, 0x37) AM_READ8 (capptr_r, 0x000000ff)
AM_RANGE(0x34, 0x37) AM_READ8 (capptr_r, 0x000000ff)
ADDRESS_MAP_END
DEVICE_ADDRESS_MAP_START(config_map, 32, pci_bridge_device)
AM_RANGE(0x00, 0x03) AM_READ16 (vendor_r, 0x0000ffff)
AM_RANGE(0x00, 0x03) AM_READ16 (device_r, 0xffff0000)
AM_RANGE(0x04, 0x07) AM_READWRITE16(command_r, command_w, 0x0000ffff)
AM_RANGE(0x04, 0x07) AM_READ16 (status_r, 0xffff0000)
AM_RANGE(0x08, 0x0b) AM_READ (class_rev_r)
AM_RANGE(0x0c, 0x0f) AM_READ8 (cache_line_size_r, 0x000000ff)
AM_RANGE(0x0c, 0x0f) AM_READ8 (latency_timer_r, 0x0000ff00)
AM_RANGE(0x0c, 0x0f) AM_READ8 (header_type_r, 0x00ff0000)
AM_RANGE(0x0c, 0x0f) AM_READ8 (bist_r, 0xff000000)
AM_RANGE(0x10, 0x17) AM_READWRITE (b_address_base_r, b_address_base_w)
AM_RANGE(0x18, 0x1b) AM_READWRITE8 (primary_bus_r, primary_bus_w, 0x000000ff)
AM_RANGE(0x18, 0x1b) AM_READWRITE8 (secondary_bus_r, secondary_bus_w, 0x0000ff00)
AM_RANGE(0x18, 0x1b) AM_READWRITE8 (subordinate_bus_r, subordinate_bus_w, 0x00ff0000)
AM_RANGE(0x18, 0x1b) AM_READWRITE8 (secondary_latency_r, secondary_latency_w, 0xff000000)
AM_RANGE(0x1c, 0x1f) AM_READWRITE8 (iobase_r, iobase_w, 0x000000ff)
AM_RANGE(0x1c, 0x1f) AM_READWRITE8 (iolimit_r, iolimit_w, 0x0000ff00)
AM_RANGE(0x1c, 0x1f) AM_READWRITE16(secondary_status_r, secondary_status_w, 0xffff0000)
AM_RANGE(0x20, 0x23) AM_READWRITE16(memory_base_r, memory_base_w, 0x0000ffff)
AM_RANGE(0x20, 0x23) AM_READWRITE16(memory_limit_r, memory_limit_w, 0xffff0000)
AM_RANGE(0x24, 0x27) AM_READWRITE16(prefetch_base_r, prefetch_base_w, 0x0000ffff)
AM_RANGE(0x24, 0x27) AM_READWRITE16(prefetch_limit_r, prefetch_limit_w, 0xffff0000)
AM_RANGE(0x28, 0x2b) AM_READWRITE (prefetch_baseu_r, prefetch_baseu_w)
AM_RANGE(0x2c, 0x2f) AM_READWRITE (prefetch_limitu_r, prefetch_limitu_w)
AM_RANGE(0x30, 0x33) AM_READWRITE16(iobaseu_r, iobaseu_w, 0x0000ffff)
AM_RANGE(0x30, 0x33) AM_READWRITE16(iolimitu_r, iolimitu_w, 0xffff0000)
AM_RANGE(0x34, 0x37) AM_READ8 (capptr_r, 0x000000ff)
AM_RANGE(0x38, 0x3b) AM_READWRITE (expansion_base_r, expansion_base_w)
AM_RANGE(0x3c, 0x3f) AM_READWRITE8 (interrupt_line_r, interrupt_line_w, 0x000000ff)
AM_RANGE(0x3c, 0x3f) AM_READWRITE8 (interrupt_pin_r, interrupt_pin_w, 0x0000ff00)
AM_RANGE(0x3c, 0x3f) AM_READWRITE16(bridge_control_r, bridge_control_w, 0xffff0000)
ADDRESS_MAP_END
pci_device::pci_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
@ -361,6 +394,11 @@ void pci_bridge_device::device_start()
void pci_bridge_device::device_reset()
{
pci_device::device_reset();
bridge_control = 0x0000;
primary_bus = 0x00;
secondary_bus = 0x00;
subordinate_bus = 0x00;
regenerate_config_mapping();
}
@ -371,7 +409,6 @@ void pci_bridge_device::reset_all_mappings()
all_devices[i]->reset_all_mappings();
}
void pci_bridge_device::map_device(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space)
{
@ -394,6 +431,282 @@ void pci_bridge_device::regenerate_config_mapping()
sub_devices[i]->map_config(i, config_space);
}
UINT32 pci_bridge_device::do_config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask)
{
if(sub_devices[device]) {
UINT32 data = space(AS_PROGRAM).read_dword((device << 12) | reg, mem_mask);
logerror("%s: config_read %02x:%02x.%x:%02x %08x @ %08x\n", tag(), bus, device >> 3, device & 7, reg, data, mem_mask);
return data;
} else
return 0xffffffff;
}
UINT32 pci_bridge_device::propagate_config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask)
{
UINT32 data = 0xffffffff;
for(int i=0; i != all_bridges.count(); i++)
data &= all_bridges[i]->config_read(bus, device, reg, mem_mask);
return data;
}
UINT32 pci_bridge_device::config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask)
{
if(bus == secondary_bus)
return do_config_read(bus, device, reg, mem_mask);
if(bus > secondary_bus && bus <= subordinate_bus)
return propagate_config_read(bus, device, reg, mem_mask);
return 0xffffffff;
}
void pci_bridge_device::do_config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask)
{
if(sub_devices[device]) {
space(AS_PROGRAM).write_dword((device << 12) | reg, data, mem_mask);
logerror("%s: config_write %02x:%02x.%x:%02x %08x @ %08x\n", tag(), bus, device >> 3, device & 7, reg, data, mem_mask);
}
}
void pci_bridge_device::propagate_config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask)
{
for(int i=0; i != all_bridges.count(); i++)
all_bridges[i]->config_write(bus, device, reg, data, mem_mask);
}
void pci_bridge_device::config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask)
{
if(bus == secondary_bus)
do_config_write(bus, device, reg, data, mem_mask);
else if(bus > secondary_bus && bus <= subordinate_bus)
propagate_config_write(bus, device, reg, data, mem_mask);
}
READ32_MEMBER (pci_bridge_device::b_address_base_r)
{
logerror("%s: b_address_base_r %d\n", tag(), offset);
return 0xffffffff;
}
WRITE32_MEMBER(pci_bridge_device::b_address_base_w)
{
logerror("%s: b_address_base_w %d, %08x\n", tag(), offset, data);
}
READ8_MEMBER (pci_bridge_device::primary_bus_r)
{
logerror("%s: primary_bus_r\n", tag());
return primary_bus;
}
WRITE8_MEMBER (pci_bridge_device::primary_bus_w)
{
primary_bus = data;
logerror("%s: primary_bus_w %02x\n", tag(), data);
}
READ8_MEMBER (pci_bridge_device::secondary_bus_r)
{
logerror("%s: secondary_bus_r\n", tag());
return secondary_bus;
}
WRITE8_MEMBER (pci_bridge_device::secondary_bus_w)
{
secondary_bus = data;
logerror("%s: secondary_bus_w %02x\n", tag(), data);
}
READ8_MEMBER (pci_bridge_device::subordinate_bus_r)
{
logerror("%s: subordinate_bus_r\n", tag());
return subordinate_bus;
}
WRITE8_MEMBER (pci_bridge_device::subordinate_bus_w)
{
subordinate_bus = data;
logerror("%s: subordinate_bus_w %02x\n", tag(), data);
}
READ8_MEMBER (pci_bridge_device::secondary_latency_r)
{
logerror("%s: secondary_latency_r\n", tag());
return 0xff;
}
WRITE8_MEMBER (pci_bridge_device::secondary_latency_w)
{
logerror("%s: secondary_latency_w %02x\n", tag(), data);
}
READ8_MEMBER (pci_bridge_device::iobase_r)
{
logerror("%s: iobase_r\n", tag());
return 0xff;
}
WRITE8_MEMBER (pci_bridge_device::iobase_w)
{
logerror("%s: iobase_w %02x\n", tag(), data);
}
READ8_MEMBER (pci_bridge_device::iolimit_r)
{
logerror("%s: iolimit_r\n", tag());
return 0xff;
}
WRITE8_MEMBER (pci_bridge_device::iolimit_w)
{
logerror("%s: iolimit_w %02x\n", tag(), data);
}
READ16_MEMBER (pci_bridge_device::secondary_status_r)
{
logerror("%s: secondary_status_r\n", tag());
return 0xffff;
}
WRITE16_MEMBER(pci_bridge_device::secondary_status_w)
{
logerror("%s: secondary_status_w %04x\n", tag(), data);
}
READ16_MEMBER (pci_bridge_device::memory_base_r)
{
logerror("%s: memory_base_r\n", tag());
return 0xffff;
}
WRITE16_MEMBER(pci_bridge_device::memory_base_w)
{
logerror("%s: memory_base_w %04x\n", tag(), data);
}
READ16_MEMBER (pci_bridge_device::memory_limit_r)
{
logerror("%s: memory_limit_r\n", tag());
return 0xffff;
}
WRITE16_MEMBER(pci_bridge_device::memory_limit_w)
{
logerror("%s: memory_limit_w %04x\n", tag(), data);
}
READ16_MEMBER (pci_bridge_device::prefetch_base_r)
{
logerror("%s: prefetch_base_r\n", tag());
return 0xffff;
}
WRITE16_MEMBER(pci_bridge_device::prefetch_base_w)
{
logerror("%s: prefetch_base_w %04x\n", tag(), data);
}
READ16_MEMBER (pci_bridge_device::prefetch_limit_r)
{
logerror("%s: prefetch_limit_r\n", tag());
return 0xffff;
}
WRITE16_MEMBER(pci_bridge_device::prefetch_limit_w)
{
logerror("%s: prefetch_limit_w %04x\n", tag(), data);
}
READ32_MEMBER (pci_bridge_device::prefetch_baseu_r)
{
logerror("%s: prefetch_baseu_r\n", tag());
return 0xffffffff;
}
WRITE32_MEMBER(pci_bridge_device::prefetch_baseu_w)
{
logerror("%s: prefetch_baseu_w %08x\n", tag(), data);
}
READ32_MEMBER (pci_bridge_device::prefetch_limitu_r)
{
logerror("%s: prefetch_limitu_r\n", tag());
return 0xffffffff;
}
WRITE32_MEMBER(pci_bridge_device::prefetch_limitu_w)
{
logerror("%s: prefetch_limitu_w %08x\n", tag(), data);
}
READ16_MEMBER (pci_bridge_device::iobaseu_r)
{
logerror("%s: iobaseu_r\n", tag());
return 0xffff;
}
WRITE16_MEMBER(pci_bridge_device::iobaseu_w)
{
logerror("%s: iobaseu_w %04x\n", tag(), data);
}
READ16_MEMBER (pci_bridge_device::iolimitu_r)
{
logerror("%s: iolimitu_r\n", tag());
return 0xffff;
}
WRITE16_MEMBER(pci_bridge_device::iolimitu_w)
{
logerror("%s: iolimitu_w %04x\n", tag(), data);
}
READ32_MEMBER (pci_bridge_device::expansion_base_r)
{
logerror("%s: expansion_base_r\n", tag());
return 0xffffffff;
}
WRITE32_MEMBER(pci_bridge_device::expansion_base_w)
{
logerror("%s: expansion_base_w %08x\n", tag(), data);
}
READ8_MEMBER (pci_bridge_device::interrupt_line_r)
{
logerror("%s: interrupt_line_r\n", tag());
return 0xff;
}
WRITE8_MEMBER (pci_bridge_device::interrupt_line_w)
{
logerror("%s: interrupt_line_w %02x\n", tag(), data);
}
READ8_MEMBER (pci_bridge_device::interrupt_pin_r)
{
logerror("%s: interrupt_pin_r\n", tag());
return 0xff;
}
WRITE8_MEMBER (pci_bridge_device::interrupt_pin_w)
{
logerror("%s: interrupt_pin_w %02x\n", tag(), data);
}
READ16_MEMBER (pci_bridge_device::bridge_control_r)
{
logerror("%s: bridge_control_r\n", tag());
return bridge_control;
}
WRITE16_MEMBER(pci_bridge_device::bridge_control_w)
{
COMBINE_DATA(&bridge_control);
logerror("%s: bridge_control_w %04x\n", tag(), bridge_control);
}
agp_bridge_device::agp_bridge_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source)
: pci_bridge_device(mconfig, type, name, tag, owner, clock, shortname, source)
@ -473,38 +786,30 @@ WRITE32_MEMBER(pci_host_device::config_address_w)
READ32_MEMBER(pci_host_device::config_data_r)
{
return config_address & 0x80000000 ? config_read((config_address >> 16) & 0xff, (config_address >> 8) & 0xff, config_address & 0xfc, mem_mask) : 0xffffffff;
return config_address & 0x80000000 ? root_config_read((config_address >> 16) & 0xff, (config_address >> 8) & 0xff, config_address & 0xfc, mem_mask) : 0xffffffff;
}
WRITE32_MEMBER(pci_host_device::config_data_w)
{
if(config_address & 0x80000000)
config_write((config_address >> 16) & 0xff, (config_address >> 8) & 0xff, config_address & 0xfc, data, mem_mask);
root_config_write((config_address >> 16) & 0xff, (config_address >> 8) & 0xff, config_address & 0xfc, data, mem_mask);
}
UINT32 pci_host_device::config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask)
UINT32 pci_host_device::root_config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask)
{
UINT32 data = 0xffffffff;
if(!bus) {
if(sub_devices[device]) {
data = space(AS_PROGRAM).read_dword((device << 12) | reg, mem_mask);
logerror("config_read %02x:%02x.%x:%02x %08x @ %08x\n", bus, device >> 3, device & 7, reg, data, mem_mask);
}
} else
abort();
if(bus == 0x00)
return do_config_read(bus, device, reg, mem_mask);
return data;
return propagate_config_read(bus, device, reg, mem_mask);
}
void pci_host_device::config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask)
void pci_host_device::root_config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask)
{
if(!bus) {
if(sub_devices[device]) {
space(AS_PROGRAM).write_dword((device << 12) | reg, data, mem_mask);
logerror("config_write %02x:%02x.%x:%02x %08x @ %08x\n", bus, device >> 3, device & 7, reg, data, mem_mask);
}
} else
abort();
if(bus == 0x00)
do_config_write(bus, device, reg, data, mem_mask);
else
propagate_config_write(bus, device, reg, data, mem_mask);
}

59
src/emu/machine/pci.h
View File

@ -139,10 +139,56 @@ public:
virtual DECLARE_READ8_MEMBER(header_type_r);
virtual DECLARE_ADDRESS_MAP(config_map, 32);
DECLARE_READ32_MEMBER (b_address_base_r);
DECLARE_WRITE32_MEMBER(b_address_base_w);
DECLARE_READ8_MEMBER (primary_bus_r);
DECLARE_WRITE8_MEMBER (primary_bus_w);
DECLARE_READ8_MEMBER (secondary_bus_r);
DECLARE_WRITE8_MEMBER (secondary_bus_w);
DECLARE_READ8_MEMBER (subordinate_bus_r);
DECLARE_WRITE8_MEMBER (subordinate_bus_w);
DECLARE_READ8_MEMBER (secondary_latency_r);
DECLARE_WRITE8_MEMBER (secondary_latency_w);
DECLARE_READ8_MEMBER (iobase_r);
DECLARE_WRITE8_MEMBER (iobase_w);
DECLARE_READ8_MEMBER (iolimit_r);
DECLARE_WRITE8_MEMBER (iolimit_w);
DECLARE_READ16_MEMBER (secondary_status_r);
DECLARE_WRITE16_MEMBER(secondary_status_w);
DECLARE_READ16_MEMBER (memory_base_r);
DECLARE_WRITE16_MEMBER(memory_base_w);
DECLARE_READ16_MEMBER (memory_limit_r);
DECLARE_WRITE16_MEMBER(memory_limit_w);
DECLARE_READ16_MEMBER (prefetch_base_r);
DECLARE_WRITE16_MEMBER(prefetch_base_w);
DECLARE_READ16_MEMBER (prefetch_limit_r);
DECLARE_WRITE16_MEMBER(prefetch_limit_w);
DECLARE_READ32_MEMBER (prefetch_baseu_r);
DECLARE_WRITE32_MEMBER(prefetch_baseu_w);
DECLARE_READ32_MEMBER (prefetch_limitu_r);
DECLARE_WRITE32_MEMBER(prefetch_limitu_w);
DECLARE_READ16_MEMBER (iobaseu_r);
DECLARE_WRITE16_MEMBER(iobaseu_w);
DECLARE_READ16_MEMBER (iolimitu_r);
DECLARE_WRITE16_MEMBER(iolimitu_w);
DECLARE_READ32_MEMBER (expansion_base_r);
DECLARE_WRITE32_MEMBER(expansion_base_w);
DECLARE_READ8_MEMBER (interrupt_line_r);
DECLARE_WRITE8_MEMBER (interrupt_line_w);
DECLARE_READ8_MEMBER (interrupt_pin_r);
DECLARE_WRITE8_MEMBER (interrupt_pin_w);
DECLARE_READ16_MEMBER (bridge_control_r);
DECLARE_WRITE16_MEMBER(bridge_control_w);
protected:
pci_device *sub_devices[32*8];
dynamic_array<pci_device *> all_devices;
dynamic_array<pci_device *> all_bridges;
dynamic_array<pci_bridge_device *> all_bridges;
UINT8 primary_bus, secondary_bus, subordinate_bus;
UINT16 bridge_control;
virtual void device_start();
virtual void device_reset();
@ -151,6 +197,13 @@ protected:
virtual device_t *bus_root();
virtual void regenerate_config_mapping();
UINT32 do_config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask);
UINT32 propagate_config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask);
UINT32 config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask);
void do_config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask);
void propagate_config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask);
void config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask);
private:
address_space_config configure_space_config;
};
@ -188,8 +241,8 @@ protected:
DECLARE_READ32_MEMBER(config_data_r);
DECLARE_WRITE32_MEMBER(config_data_w);
UINT32 config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask);
void config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask);
UINT32 root_config_read(UINT8 bus, UINT8 device, UINT16 reg, UINT32 mem_mask);
void root_config_write(UINT8 bus, UINT8 device, UINT16 reg, UINT32 data, UINT32 mem_mask);
void regenerate_mapping();
};

10
src/mame/drivers/lindbergh.c
View File

@ -347,16 +347,7 @@ void lindbergh_state::machine_reset()
}
static MACHINE_CONFIG_START(lindbergh, lindbergh_state)
// MCFG_CPU_ADD("maincpu", PENTIUM, 2800000000U) /* Actually Celeron D at 2,8 GHz */
MCFG_CPU_ADD("maincpu", PENTIUM4, 28000000U*5) /* Actually Celeron D at 2,8 GHz */
// MCFG_CPU_PROGRAM_MAP(lindbergh_map)
// MCFG_CPU_IO_MAP(lindbergh_io)
// MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259_1", pic8259_device, inta_cb)
// MCFG_FRAGMENT_ADD( pcat_common )
// MCFG_FRAGMENT_ADD( pcvideo_vga )
// MCFG_PCI_BUS_LEGACY_ADD("pcibus", 0)
MCFG_PCI_ROOT_ADD( ":pci")
MCFG_I82875P_HOST_ADD( ":pci:00.0", 0x103382c0, ":maincpu", 512*1024*1024)
@ -375,6 +366,7 @@ static MACHINE_CONFIG_START(lindbergh, lindbergh_state)
MCFG_I6300ESB_LPC_ADD( ":pci:1f.0")
MCFG_LPC_ACPI_ADD( ":pci:1f.0:acpi")
MCFG_LPC_RTC_ADD( ":pci:1f.0:rtc")
MCFG_LPC_PIT_ADD( ":pci:1f.0:pit")
MCFG_SATA_ADD( ":pci:1f.2", 0x808625a3, 0x02, 0x103382c0)
MCFG_SMBUS_ADD( ":pci:1f.3", 0x808625a4, 0x02, 0x103382c0)
MCFG_AC97_ADD( ":pci:1f.5", 0x808625a6, 0x02, 0x103382c0)