From 1a9ef1251fe3d2b814b95f6f40acee257a339e61 Mon Sep 17 00:00:00 2001 From: Wilbert Pol Date: Sun, 4 Aug 2013 12:16:02 +0000 Subject: [PATCH] i960.c: Modernized cpu core (nw) --- src/emu/cpu/i960/i960.c | 1900 +++++++++++++++++------------------- src/emu/cpu/i960/i960.h | 113 ++- src/mame/drivers/model2.c | 10 +- src/mame/includes/model2.h | 2 +- 4 files changed, 1007 insertions(+), 1018 deletions(-) diff --git a/src/emu/cpu/i960/i960.c b/src/emu/cpu/i960/i960.c index 2b93712589b..05c9f768d38 100644 --- a/src/emu/cpu/i960/i960.c +++ b/src/emu/cpu/i960/i960.c @@ -11,109 +11,81 @@ CPU_DISASSEMBLE( i960 ); #endif -// Warning, IP = Instruction Pointer, called PC outside of Intel -// PC = Process Control +const device_type I960 = &device_creator; -enum { RCACHE_SIZE = 4 }; -struct i960_state_t { - UINT32 r[0x20]; - UINT32 rcache[RCACHE_SIZE][0x10]; - UINT32 rcache_frame_addr[RCACHE_SIZE]; - // rcache_pos = how deep in the stack we are. 0-(RCACHE_SIZE-1) means in-cache. - // RCACHE_SIZE or greater means out of cache, must save to memory. - INT32 rcache_pos; - - double fp[4]; - - UINT32 SAT, PRCB, PC, AC; - UINT32 IP, PIP, ICR; - int bursting; - - int immediate_irq, immediate_vector, immediate_pri; - - device_irq_acknowledge_callback irq_cb; - legacy_cpu_device *device; - address_space *program; - direct_read_data *direct; - - int icount; -}; - -INLINE i960_state_t *get_safe_token(device_t *device) +i960_cpu_device::i960_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : cpu_device(mconfig, I960, "i960kb", tag, owner, clock, "i960kb", __FILE__) + , m_program_config("program", ENDIANNESS_LITTLE, 32, 32, 0) { - assert(device != NULL); - assert(device->type() == I960); - return (i960_state_t *)downcast(device)->token(); } -static void do_call(i960_state_t *i960, UINT32 adr, int type, UINT32 stack); -INLINE UINT32 i960_read_dword_unaligned(i960_state_t *i960, UINT32 address) +UINT32 i960_cpu_device::i960_read_dword_unaligned(UINT32 address) { if (address & 3) - return i960->program->read_byte(address) | i960->program->read_byte(address+1)<<8 | i960->program->read_byte(address+2)<<16 | i960->program->read_byte(address+3)<<24; + return m_program->read_byte(address) | m_program->read_byte(address+1)<<8 | m_program->read_byte(address+2)<<16 | m_program->read_byte(address+3)<<24; else - return i960->program->read_dword(address); + return m_program->read_dword(address); } -INLINE UINT16 i960_read_word_unaligned(i960_state_t *i960, UINT32 address) +UINT16 i960_cpu_device::i960_read_word_unaligned(UINT32 address) { if (address & 1) - return i960->program->read_byte(address) | i960->program->read_byte(address+1)<<8; + return m_program->read_byte(address) | m_program->read_byte(address+1)<<8; else - return i960->program->read_word(address); + return m_program->read_word(address); } -INLINE void i960_write_dword_unaligned(i960_state_t *i960, UINT32 address, UINT32 data) +void i960_cpu_device::i960_write_dword_unaligned(UINT32 address, UINT32 data) { if (address & 3) { - i960->program->write_byte(address, data & 0xff); - i960->program->write_byte(address+1, (data>>8)&0xff); - i960->program->write_byte(address+2, (data>>16)&0xff); - i960->program->write_byte(address+3, (data>>24)&0xff); + m_program->write_byte(address, data & 0xff); + m_program->write_byte(address+1, (data>>8)&0xff); + m_program->write_byte(address+2, (data>>16)&0xff); + m_program->write_byte(address+3, (data>>24)&0xff); } else { - i960->program->write_dword(address, data); + m_program->write_dword(address, data); } } -INLINE void i960_write_word_unaligned(i960_state_t *i960, UINT32 address, UINT16 data) +void i960_cpu_device::i960_write_word_unaligned(UINT32 address, UINT16 data) { if (address & 1) { - i960->program->write_byte(address, data & 0xff); - i960->program->write_byte(address+1, (data>>8)&0xff); + m_program->write_byte(address, data & 0xff); + m_program->write_byte(address+1, (data>>8)&0xff); } else { - i960->program->write_word(address, data); + m_program->write_word(address, data); } } -INLINE void send_iac(i960_state_t *i960, UINT32 adr) +void i960_cpu_device::send_iac(UINT32 adr) { UINT32 iac[4]; - iac[0] = i960->program->read_dword(adr); - iac[1] = i960->program->read_dword(adr+4); - iac[2] = i960->program->read_dword(adr+8); - iac[3] = i960->program->read_dword(adr+12); + iac[0] = m_program->read_dword(adr); + iac[1] = m_program->read_dword(adr+4); + iac[2] = m_program->read_dword(adr+8); + iac[3] = m_program->read_dword(adr+12); switch(iac[0]>>24) { case 0x93: // reinit - i960->SAT = iac[1]; - i960->PRCB = iac[2]; - i960->IP = iac[3]; + m_SAT = iac[1]; + m_PRCB = iac[2]; + m_IP = iac[3]; break; default: - fatalerror("I960: %x: IAC %08x %08x %08x %08x\n", i960->PIP, iac[0], iac[1], iac[2], iac[3]); + fatalerror("I960: %x: IAC %08x %08x %08x %08x\n", m_PIP, iac[0], iac[1], iac[2], iac[3]); break; } } -INLINE UINT32 get_ea(i960_state_t *i960, UINT32 opcode) +UINT32 i960_cpu_device::get_ea(UINT32 opcode) { int abase = (opcode >> 14) & 0x1f; if(!(opcode & 0x00001000)) { // MEMA @@ -121,7 +93,7 @@ INLINE UINT32 get_ea(i960_state_t *i960, UINT32 opcode) if(!(opcode & 0x2000)) return offset; else - return i960->r[abase]+offset; + return m_r[abase]+offset; } else { // MEMB int index = opcode & 0x1f; int scale = (opcode >> 7) & 0x7; @@ -130,188 +102,188 @@ INLINE UINT32 get_ea(i960_state_t *i960, UINT32 opcode) switch(mode) { case 0x4: - return i960->r[abase]; + return m_r[abase]; case 0x7: - return i960->r[abase] + (i960->r[index] << scale); + return m_r[abase] + (m_r[index] << scale); case 0xc: - ret = i960->direct->read_decrypted_dword(i960->IP); - i960->IP += 4; + ret = m_direct->read_decrypted_dword(m_IP); + m_IP += 4; return ret; case 0xd: - ret = i960->direct->read_decrypted_dword(i960->IP) + i960->r[abase]; - i960->IP += 4; + ret = m_direct->read_decrypted_dword(m_IP) + m_r[abase]; + m_IP += 4; return ret; case 0xe: - ret = i960->direct->read_decrypted_dword(i960->IP) + (i960->r[index] << scale); - i960->IP += 4; + ret = m_direct->read_decrypted_dword(m_IP) + (m_r[index] << scale); + m_IP += 4; return ret; case 0xf: - ret = i960->direct->read_decrypted_dword(i960->IP) + i960->r[abase] + (i960->r[index] << scale); - i960->IP += 4; + ret = m_direct->read_decrypted_dword(m_IP) + m_r[abase] + (m_r[index] << scale); + m_IP += 4; return ret; default: - fatalerror("I960: %x: unhandled MEMB mode %x\n", i960->PIP, mode); + fatalerror("I960: %x: unhandled MEMB mode %x\n", m_PIP, mode); return 0; } } } -INLINE UINT32 get_1_ri(i960_state_t *i960, UINT32 opcode) +UINT32 i960_cpu_device::get_1_ri(UINT32 opcode) { if(!(opcode & 0x00000800)) - return i960->r[opcode & 0x1f]; + return m_r[opcode & 0x1f]; else return opcode & 0x1f; } -INLINE UINT32 get_2_ri(i960_state_t *i960, UINT32 opcode) +UINT32 i960_cpu_device::get_2_ri(UINT32 opcode) { if(!(opcode & 0x00001000)) - return i960->r[(opcode>>14) & 0x1f]; + return m_r[(opcode>>14) & 0x1f]; else return (opcode>>14) & 0x1f; } -INLINE UINT64 get_2_ri64(i960_state_t *i960, UINT32 opcode) +UINT64 i960_cpu_device::get_2_ri64(UINT32 opcode) { if(!(opcode & 0x00001000)) - return i960->r[(opcode>>14) & 0x1f] | ((UINT64)i960->r[((opcode>>14) & 0x1f)+1]<<32); + return m_r[(opcode>>14) & 0x1f] | ((UINT64)m_r[((opcode>>14) & 0x1f)+1]<<32); else return (opcode>>14) & 0x1f; } -INLINE void set_ri(i960_state_t *i960, UINT32 opcode, UINT32 val) +void i960_cpu_device::set_ri(UINT32 opcode, UINT32 val) { if(!(opcode & 0x00002000)) - i960->r[(opcode>>19) & 0x1f] = val; + m_r[(opcode>>19) & 0x1f] = val; else { - fatalerror("I960: %x: set_ri on literal?\n", i960->PIP); + fatalerror("I960: %x: set_ri on literal?\n", m_PIP); } } -INLINE void set_ri2(i960_state_t *i960, UINT32 opcode, UINT32 val, UINT32 val2) +void i960_cpu_device::set_ri2(UINT32 opcode, UINT32 val, UINT32 val2) { if(!(opcode & 0x00002000)) { - i960->r[(opcode>>19) & 0x1f] = val; - i960->r[((opcode>>19) & 0x1f)+1] = val2; + m_r[(opcode>>19) & 0x1f] = val; + m_r[((opcode>>19) & 0x1f)+1] = val2; } else { - fatalerror("I960: %x: set_ri2 on literal?\n", i960->PIP); + fatalerror("I960: %x: set_ri2 on literal?\n", m_PIP); } } -INLINE void set_ri64(i960_state_t *i960, UINT32 opcode, UINT64 val) +void i960_cpu_device::set_ri64(UINT32 opcode, UINT64 val) { if(!(opcode & 0x00002000)) { - i960->r[(opcode>>19) & 0x1f] = val; - i960->r[((opcode>>19) & 0x1f)+1] = val >> 32; + m_r[(opcode>>19) & 0x1f] = val; + m_r[((opcode>>19) & 0x1f)+1] = val >> 32; } else - fatalerror("I960: %x: set_ri64 on literal?\n", i960->PIP); + fatalerror("I960: %x: set_ri64 on literal?\n", m_PIP); } -INLINE double get_1_rif(i960_state_t *i960, UINT32 opcode) +double i960_cpu_device::get_1_rif(UINT32 opcode) { if(!(opcode & 0x00000800)) - return u2f(i960->r[opcode & 0x1f]); + return u2f(m_r[opcode & 0x1f]); else { int idx = opcode & 0x1f; if(idx < 4) - return i960->fp[idx]; + return m_fp[idx]; if(idx == 0x16) return 1.0; return 0.0; } } -INLINE double get_2_rif(i960_state_t *i960, UINT32 opcode) +double i960_cpu_device::get_2_rif(UINT32 opcode) { if(!(opcode & 0x00001000)) - return u2f(i960->r[(opcode>>14) & 0x1f]); + return u2f(m_r[(opcode>>14) & 0x1f]); else { int idx = (opcode>>14) & 0x1f; if(idx < 4) - return i960->fp[idx]; + return m_fp[idx]; if(idx == 0x16) return 1.0; return 0.0; } } -INLINE void set_rif(i960_state_t *i960, UINT32 opcode, double val) +void i960_cpu_device::set_rif(UINT32 opcode, double val) { if(!(opcode & 0x00002000)) - i960->r[(opcode>>19) & 0x1f] = f2u(val); + m_r[(opcode>>19) & 0x1f] = f2u(val); else if(!(opcode & 0x00e00000)) - i960->fp[(opcode>>19) & 3] = val; + m_fp[(opcode>>19) & 3] = val; else - fatalerror("I960: %x: set_rif on literal?\n", i960->PIP); + fatalerror("I960: %x: set_rif on literal?\n", m_PIP); } -INLINE double get_1_rifl(i960_state_t *i960, UINT32 opcode) +double i960_cpu_device::get_1_rifl(UINT32 opcode) { if(!(opcode & 0x00000800)) { - UINT64 v = i960->r[opcode & 0x1e]; - v |= ((UINT64)(i960->r[(opcode & 0x1e)+1]))<<32; + UINT64 v = m_r[opcode & 0x1e]; + v |= ((UINT64)(m_r[(opcode & 0x1e)+1]))<<32; return u2d(v); } else { int idx = opcode & 0x1f; if(idx < 4) - return i960->fp[idx]; + return m_fp[idx]; if(idx == 0x16) return 1.0; return 0.0; } } -INLINE double get_2_rifl(i960_state_t *i960, UINT32 opcode) +double i960_cpu_device::get_2_rifl(UINT32 opcode) { if(!(opcode & 0x00001000)) { - UINT64 v = i960->r[(opcode >> 14) & 0x1e]; - v |= ((UINT64)(i960->r[((opcode>>14) & 0x1e)+1]))<<32; + UINT64 v = m_r[(opcode >> 14) & 0x1e]; + v |= ((UINT64)(m_r[((opcode>>14) & 0x1e)+1]))<<32; return u2d(v); } else { int idx = (opcode>>14) & 0x1f; if(idx < 4) - return i960->fp[idx]; + return m_fp[idx]; if(idx == 0x16) return 1.0; return 0.0; } } -INLINE void set_rifl(i960_state_t *i960, UINT32 opcode, double val) +void i960_cpu_device::set_rifl(UINT32 opcode, double val) { if(!(opcode & 0x00002000)) { UINT64 v = d2u(val); - i960->r[(opcode>>19) & 0x1e] = v; - i960->r[((opcode>>19) & 0x1e)+1] = v>>32; + m_r[(opcode>>19) & 0x1e] = v; + m_r[((opcode>>19) & 0x1e)+1] = v>>32; } else if(!(opcode & 0x00e00000)) - i960->fp[(opcode>>19) & 3] = val; + m_fp[(opcode>>19) & 3] = val; else - fatalerror("I960: %x: set_rifl on literal?\n", i960->PIP); + fatalerror("I960: %x: set_rifl on literal?\n", m_PIP); } -INLINE UINT32 get_1_ci(i960_state_t *i960, UINT32 opcode) +UINT32 i960_cpu_device::get_1_ci(UINT32 opcode) { if(!(opcode & 0x00002000)) - return i960->r[(opcode >> 19) & 0x1f]; + return m_r[(opcode >> 19) & 0x1f]; else return (opcode >> 19) & 0x1f; } -INLINE UINT32 get_2_ci(i960_state_t *i960, UINT32 opcode) +UINT32 i960_cpu_device::get_2_ci(UINT32 opcode) { - return i960->r[(opcode >> 14) & 0x1f]; + return m_r[(opcode >> 14) & 0x1f]; } -INLINE UINT32 get_disp(i960_state_t *i960, UINT32 opcode) +UINT32 i960_cpu_device::get_disp(UINT32 opcode) { UINT32 disp; disp = opcode & 0xffffff; @@ -320,7 +292,7 @@ INLINE UINT32 get_disp(i960_state_t *i960, UINT32 opcode) return disp-4; } -INLINE UINT32 get_disp_s(i960_state_t *i960, UINT32 opcode) +UINT32 i960_cpu_device::get_disp_s(UINT32 opcode) { UINT32 disp; disp = opcode & 0x1fff; @@ -329,140 +301,131 @@ INLINE UINT32 get_disp_s(i960_state_t *i960, UINT32 opcode) return disp-4; } -INLINE void cmp_s(i960_state_t *i960, INT32 v1, INT32 v2) +void i960_cpu_device::cmp_s(INT32 v1, INT32 v2) { - i960->AC &= ~7; + m_AC &= ~7; if(v1AC |= 4; + m_AC |= 4; else if(v1 == v2) - i960->AC |= 2; + m_AC |= 2; else - i960->AC |= 1; + m_AC |= 1; } -INLINE void cmp_u(i960_state_t *i960, UINT32 v1, UINT32 v2) +void i960_cpu_device::cmp_u(UINT32 v1, UINT32 v2) { - i960->AC &= ~7; + m_AC &= ~7; if(v1AC |= 4; + m_AC |= 4; else if(v1 == v2) - i960->AC |= 2; + m_AC |= 2; else - i960->AC |= 1; + m_AC |= 1; } -INLINE void concmp_s(i960_state_t *i960, INT32 v1, INT32 v2) +void i960_cpu_device::concmp_s(INT32 v1, INT32 v2) { - i960->AC &= ~7; + m_AC &= ~7; if(v1 <= v2) - i960->AC |= 2; + m_AC |= 2; else - i960->AC |= 1; + m_AC |= 1; } -INLINE void concmp_u(i960_state_t *i960, UINT32 v1, UINT32 v2) +void i960_cpu_device::concmp_u(UINT32 v1, UINT32 v2) { - i960->AC &= ~7; + m_AC &= ~7; if(v1 <= v2) - i960->AC |= 2; + m_AC |= 2; else - i960->AC |= 1; + m_AC |= 1; } -INLINE void cmp_d(i960_state_t *i960, double v1, double v2) +void i960_cpu_device::cmp_d(double v1, double v2) { - i960->AC &= ~7; + m_AC &= ~7; if(v1AC |= 4; + m_AC |= 4; else if(v1 == v2) - i960->AC |= 2; + m_AC |= 2; else if(v1 > v2) - i960->AC |= 1; + m_AC |= 1; } -INLINE void bxx(i960_state_t *i960, UINT32 opcode, int mask) +void i960_cpu_device::bxx(UINT32 opcode, int mask) { - if(i960->AC & mask) { - i960->IP += get_disp(i960, opcode); + if(m_AC & mask) { + m_IP += get_disp(opcode); } } -INLINE void bxx_s(i960_state_t *i960, UINT32 opcode, int mask) +void i960_cpu_device::bxx_s(UINT32 opcode, int mask) { - if(i960->AC & mask) { - i960->IP += get_disp_s(i960, opcode); + if(m_AC & mask) { + m_IP += get_disp_s(opcode); } } -INLINE void test(i960_state_t *i960, UINT32 opcode, int mask) +void i960_cpu_device::test(UINT32 opcode, int mask) { - if(i960->AC & mask) - i960->r[(opcode>>19) & 0x1f] = 1; + if(m_AC & mask) + m_r[(opcode>>19) & 0x1f] = 1; else - i960->r[(opcode>>19) & 0x1f] = 0; + m_r[(opcode>>19) & 0x1f] = 0; } -INLINE const char *i960_get_strflags(i960_state_t *i960) -{ - static const char *const conditions[8] = - { - "no", "g", "e", "ge", "l", "ne", "le", "o" - }; - - return (conditions[i960->AC & 7]); -} // interrupt dispatch -static void take_interrupt(i960_state_t *i960, int vector, int lvl) +void i960_cpu_device::take_interrupt(int vector, int lvl) { - int int_tab = i960->program->read_dword(i960->PRCB+20); // interrupt table - int int_SP = i960->program->read_dword(i960->PRCB+24); // interrupt stack + int int_tab = m_program->read_dword(m_PRCB+20); // interrupt table + int int_SP = m_program->read_dword(m_PRCB+24); // interrupt stack int SP; UINT32 IRQV; - IRQV = i960->program->read_dword(int_tab + 36 + (vector-8)*4); + IRQV = m_program->read_dword(int_tab + 36 + (vector-8)*4); // start the process - if(!(i960->PC & 0x2000)) // if this is a nested interrupt, don't re-get int_SP + if(!(m_PC & 0x2000)) // if this is a nested interrupt, don't re-get int_SP { SP = int_SP; } else { - SP = i960->r[I960_SP]; + SP = m_r[I960_SP]; } SP = (SP + 63) & ~63; SP += 128; // emulate ElSemi's core, this fixes the crash in sonic the fighters - do_call(i960, IRQV, 7, SP); + do_call(IRQV, 7, SP); // save the processor state - i960->program->write_dword(i960->r[I960_FP]-16, i960->PC); - i960->program->write_dword(i960->r[I960_FP]-12, i960->AC); + m_program->write_dword(m_r[I960_FP]-16, m_PC); + m_program->write_dword(m_r[I960_FP]-12, m_AC); // store the vector - i960->program->write_dword(i960->r[I960_FP]-8, vector-8); + m_program->write_dword(m_r[I960_FP]-8, vector-8); - i960->PC &= ~0x1f00; // clear priority, state, trace-fault pending, and trace enable - i960->PC |= (lvl<<16); // set CPU level to current IRQ level - i960->PC |= 0x2002; // set supervisor mode & interrupt flag + m_PC &= ~0x1f00; // clear priority, state, trace-fault pending, and trace enable + m_PC |= (lvl<<16); // set CPU level to current IRQ level + m_PC |= 0x2002; // set supervisor mode & interrupt flag } -static void check_irqs(i960_state_t *i960) +void i960_cpu_device::check_irqs() { - int int_tab = i960->program->read_dword(i960->PRCB+20); // interrupt table - int cpu_pri = (i960->PC>>16)&0x1f; + int int_tab = m_program->read_dword(m_PRCB+20); // interrupt table + int cpu_pri = (m_PC>>16)&0x1f; int pending_pri; int lvl, irq, take = -1; int vword; static const UINT32 lvlmask[4] = { 0x000000ff, 0x0000ff00, 0x00ff0000, 0xff000000 }; - pending_pri = i960->program->read_dword(int_tab); // read pending priorities + pending_pri = m_program->read_dword(int_tab); // read pending priorities - if ((i960->immediate_irq) && ((cpu_pri < i960->immediate_pri) || (i960->immediate_pri == 31))) + if ((m_immediate_irq) && ((cpu_pri < m_immediate_pri) || (m_immediate_pri == 31))) { - take_interrupt(i960, i960->immediate_vector, i960->immediate_pri); - i960->immediate_irq = 0; + take_interrupt(m_immediate_vector, m_immediate_pri); + m_immediate_irq = 0; } else { @@ -475,14 +438,14 @@ static void check_irqs(i960_state_t *i960) wordl = (lvl % 4) * 8; wordh = (wordl + 8) - 1; - vword = i960->program->read_dword(int_tab + word); + vword = m_program->read_dword(int_tab + word); // take the first vector we find for this level for (irq = wordh; irq >= wordl; irq--) { if(vword & (1 << irq)) { // clear pending bit vword &= ~(1 << irq); - i960->program->write_dword(int_tab + word, vword); + m_program->write_dword(int_tab + word, vword); take = irq; break; } @@ -494,629 +457,629 @@ static void check_irqs(i960_state_t *i960) // try to recover... pending_pri &= ~(1 << lvl); - i960->program->write_dword(int_tab, pending_pri); + m_program->write_dword(int_tab, pending_pri); return; } // if no vectors are waiting for this level, clear the level bit if(!(vword & lvlmask[lvl % 4])) { pending_pri &= ~(1 << lvl); - i960->program->write_dword(int_tab, pending_pri); + m_program->write_dword(int_tab, pending_pri); } take += ((lvl/4) * 32); - take_interrupt(i960, take, lvl); + take_interrupt(take, lvl); return; } } } } -static void do_call(i960_state_t *i960, UINT32 adr, int type, UINT32 stack) +void i960_cpu_device::do_call(UINT32 adr, int type, UINT32 stack) { int i; UINT32 FP; // call and callx take 9 cycles base - i960->icount -= 9; + m_icount -= 9; // set the new RIP - i960->r[I960_RIP] = i960->IP; -// mame_printf_debug("CALL (type %d): FP %x, %x => %x, stack %x, rcache_pos %d\n", type, i960->r[I960_FP], i960->r[I960_RIP], adr, stack, i960->rcache_pos); + m_r[I960_RIP] = m_IP; +// mame_printf_debug("CALL (type %d): FP %x, %x => %x, stack %x, rcache_pos %d\n", type, m_r[I960_FP], m_r[I960_RIP], adr, stack, m_rcache_pos); // are we out of cache entries? - if (i960->rcache_pos >= RCACHE_SIZE) { + if (m_rcache_pos >= I960_RCACHE_SIZE) { // flush the current register set to the current frame - FP = i960->r[I960_FP] & ~0x3f; + FP = m_r[I960_FP] & ~0x3f; for (i = 0; i < 16; i++) { - i960->program->write_dword(FP + (i*4), i960->r[i]); + m_program->write_dword(FP + (i*4), m_r[i]); } } else // a cache entry is available, use it { - memcpy(&i960->rcache[i960->rcache_pos][0], i960->r, 0x10 * sizeof(UINT32)); - i960->rcache_frame_addr[i960->rcache_pos] = i960->r[I960_FP] & ~0x3f; + memcpy(&m_rcache[m_rcache_pos][0], m_r, 0x10 * sizeof(UINT32)); + m_rcache_frame_addr[m_rcache_pos] = m_r[I960_FP] & ~0x3f; } - i960->rcache_pos++; + m_rcache_pos++; - i960->IP = adr; - i960->r[I960_PFP] = i960->r[I960_FP] & ~7; - i960->r[I960_PFP] |= type; + m_IP = adr; + m_r[I960_PFP] = m_r[I960_FP] & ~7; + m_r[I960_PFP] |= type; if(type == 7) { // interrupts need special handling // set the stack to the passed-in value to properly handle nested interrupts // (can't set it externally or the original program's SP will be lost) - i960->r[I960_SP] = stack; + m_r[I960_SP] = stack; } - i960->r[I960_FP] = (i960->r[I960_SP] + 63) & ~63; - i960->r[I960_SP] = i960->r[I960_FP] + 64; + m_r[I960_FP] = (m_r[I960_SP] + 63) & ~63; + m_r[I960_SP] = m_r[I960_FP] + 64; } -static void do_ret_0(i960_state_t *i960) +void i960_cpu_device::do_ret_0() { -// int type = i960->r[I960_PFP] & 7; +// int type = m_r[I960_PFP] & 7; - i960->r[I960_FP] = i960->r[I960_PFP] & ~0x3f; + m_r[I960_FP] = m_r[I960_PFP] & ~0x3f; - i960->rcache_pos--; + m_rcache_pos--; // normal situation: if we're still above rcache size, we're not in cache. // abnormal situation (after the app does a FLUSHREG): rcache_pos will be 0 // coming in, but we must still treat it as a not-in-cache situation. - if ((i960->rcache_pos >= RCACHE_SIZE) || (i960->rcache_pos < 0)) + if ((m_rcache_pos >= I960_RCACHE_SIZE) || (m_rcache_pos < 0)) { int i; for(i=0; i<0x10; i++) - i960->r[i] = i960->program->read_dword(i960->r[I960_FP]+4*i); + m_r[i] = m_program->read_dword(m_r[I960_FP]+4*i); - if (i960->rcache_pos < 0) + if (m_rcache_pos < 0) { - i960->rcache_pos = 0; + m_rcache_pos = 0; } } else { - memcpy(i960->r, i960->rcache[i960->rcache_pos], 0x10*sizeof(UINT32)); + memcpy(m_r, m_rcache[m_rcache_pos], 0x10*sizeof(UINT32)); } -// mame_printf_debug("RET (type %d): FP %x, %x => %x, rcache_pos %d\n", type, i960->r[I960_FP], i960->IP, i960->r[I960_RIP], i960->rcache_pos); - i960->IP = i960->r[I960_RIP]; +// mame_printf_debug("RET (type %d): FP %x, %x => %x, rcache_pos %d\n", type, m_r[I960_FP], m_IP, m_r[I960_RIP], m_rcache_pos); + m_IP = m_r[I960_RIP]; } -static void do_ret(i960_state_t *i960) +void i960_cpu_device::do_ret() { UINT32 x, y; - i960->icount -= 7; - switch(i960->r[I960_PFP] & 7) { + m_icount -= 7; + switch(m_r[I960_PFP] & 7) { case 0: - do_ret_0(i960); + do_ret_0(); break; case 7: - x = i960->program->read_dword(i960->r[I960_FP]-16); - y = i960->program->read_dword(i960->r[I960_FP]-12); - do_ret_0(i960); - i960->AC = y; + x = m_program->read_dword(m_r[I960_FP]-16); + y = m_program->read_dword(m_r[I960_FP]-12); + do_ret_0(); + m_AC = y; // #### test supervisor - i960->PC = x; + m_PC = x; // check for another IRQ now that we're back - check_irqs(i960); + check_irqs(); break; default: - fatalerror("I960: %x: Unsupported return mode %d\n", i960->PIP, i960->r[I960_PFP] & 7); + fatalerror("I960: %x: Unsupported return mode %d\n", m_PIP, m_r[I960_PFP] & 7); } } -INLINE void execute_op(i960_state_t *i960, UINT32 opcode) +void i960_cpu_device::execute_op(UINT32 opcode) { UINT32 t1, t2; double t1f, t2f; switch(opcode >> 24) { case 0x08: // b - i960->icount--; - i960->IP += get_disp(i960, opcode); + m_icount--; + m_IP += get_disp(opcode); break; case 0x09: // call - do_call(i960, i960->IP+get_disp(i960, opcode), 0, i960->r[I960_SP]); + do_call(m_IP+get_disp(opcode), 0, m_r[I960_SP]); break; case 0x0a: // ret - do_ret(i960); + do_ret(); break; case 0x0b: // bal - i960->icount -= 5; - i960->r[0x1e] = i960->IP; - i960->IP += get_disp(i960, opcode); + m_icount -= 5; + m_r[0x1e] = m_IP; + m_IP += get_disp(opcode); break; case 0x10: // bno - i960->icount--; - if(!(i960->AC & 7)) { - i960->IP += get_disp(i960, opcode); + m_icount--; + if(!(m_AC & 7)) { + m_IP += get_disp(opcode); } break; case 0x11: // bg - i960->icount--; - bxx(i960, opcode, 1); + m_icount--; + bxx(opcode, 1); break; case 0x12: // be - i960->icount--; - bxx(i960, opcode, 2); + m_icount--; + bxx(opcode, 2); break; case 0x13: // bge - i960->icount--; - bxx(i960, opcode, 3); + m_icount--; + bxx(opcode, 3); break; case 0x14: // bl - i960->icount--; - bxx(i960, opcode, 4); + m_icount--; + bxx(opcode, 4); break; case 0x15: // bne - i960->icount--; - bxx(i960, opcode, 5); + m_icount--; + bxx(opcode, 5); break; case 0x16: // ble - i960->icount--; - bxx(i960, opcode, 6); + m_icount--; + bxx(opcode, 6); break; case 0x17: // bo - i960->icount--; - bxx(i960, opcode, 7); + m_icount--; + bxx(opcode, 7); break; case 0x20: // testno - i960->icount--; - if(!(i960->AC & 7)) - i960->r[(opcode>>19) & 0x1f] = 1; + m_icount--; + if(!(m_AC & 7)) + m_r[(opcode>>19) & 0x1f] = 1; else - i960->r[(opcode>>19) & 0x1f] = 0; + m_r[(opcode>>19) & 0x1f] = 0; break; case 0x21: // testg - i960->icount--; - test(i960, opcode, 1); + m_icount--; + test(opcode, 1); break; case 0x22: // teste - i960->icount--; - test(i960, opcode, 2); + m_icount--; + test(opcode, 2); break; case 0x23: // testge - i960->icount--; - test(i960, opcode, 3); + m_icount--; + test(opcode, 3); break; case 0x24: // testl - i960->icount--; - test(i960, opcode, 4); + m_icount--; + test(opcode, 4); break; case 0x25: // testne - i960->icount--; - test(i960, opcode, 5); + m_icount--; + test(opcode, 5); break; case 0x26: // testle - i960->icount--; - test(i960, opcode, 6); + m_icount--; + test(opcode, 6); break; case 0x27: // testo - i960->icount--; - test(i960, opcode, 7); + m_icount--; + test(opcode, 7); break; case 0x30: // bbc - i960->icount -= 4; - t1 = get_1_ci(i960, opcode) & 0x1f; - t2 = get_2_ci(i960, opcode); + m_icount -= 4; + t1 = get_1_ci(opcode) & 0x1f; + t2 = get_2_ci(opcode); if(!(t2 & (1<AC = (i960->AC & ~7) | 2; - i960->IP += get_disp_s(i960, opcode); + m_AC = (m_AC & ~7) | 2; + m_IP += get_disp_s(opcode); } else - i960->AC &= ~7; + m_AC &= ~7; break; case 0x31: // cmp0bg - i960->icount -= 4; - t1 = get_1_ci(i960, opcode); - t2 = get_2_ci(i960, opcode); - cmp_u(i960, t1, t2); - bxx_s(i960, opcode, 1); + m_icount -= 4; + t1 = get_1_ci(opcode); + t2 = get_2_ci(opcode); + cmp_u(t1, t2); + bxx_s(opcode, 1); break; case 0x32: // cmpobe - i960->icount -= 4; - t1 = get_1_ci(i960, opcode); - t2 = get_2_ci(i960, opcode); - cmp_u(i960, t1, t2); - bxx_s(i960, opcode, 2); + m_icount -= 4; + t1 = get_1_ci(opcode); + t2 = get_2_ci(opcode); + cmp_u(t1, t2); + bxx_s(opcode, 2); break; case 0x33: // cmpobge - i960->icount -= 4; - t1 = get_1_ci(i960, opcode); - t2 = get_2_ci(i960, opcode); - cmp_u(i960, t1, t2); - bxx_s(i960, opcode, 3); + m_icount -= 4; + t1 = get_1_ci(opcode); + t2 = get_2_ci(opcode); + cmp_u(t1, t2); + bxx_s(opcode, 3); break; case 0x34: // cmpobl - i960->icount -= 4; - t1 = get_1_ci(i960, opcode); - t2 = get_2_ci(i960, opcode); - cmp_u(i960, t1, t2); - bxx_s(i960, opcode, 4); + m_icount -= 4; + t1 = get_1_ci(opcode); + t2 = get_2_ci(opcode); + cmp_u(t1, t2); + bxx_s(opcode, 4); break; case 0x35: // cmpobne - i960->icount -= 4; - t1 = get_1_ci(i960, opcode); - t2 = get_2_ci(i960, opcode); - cmp_u(i960, t1, t2); - bxx_s(i960, opcode, 5); + m_icount -= 4; + t1 = get_1_ci(opcode); + t2 = get_2_ci(opcode); + cmp_u(t1, t2); + bxx_s(opcode, 5); break; case 0x36: // cmpoble - i960->icount -= 4; - t1 = get_1_ci(i960, opcode); - t2 = get_2_ci(i960, opcode); - cmp_u(i960, t1, t2); - bxx_s(i960, opcode, 6); + m_icount -= 4; + t1 = get_1_ci(opcode); + t2 = get_2_ci(opcode); + cmp_u(t1, t2); + bxx_s(opcode, 6); break; case 0x37: // bbs - i960->icount -= 4; - t1 = get_1_ci(i960, opcode) & 0x1f; - t2 = get_2_ci(i960, opcode); + m_icount -= 4; + t1 = get_1_ci(opcode) & 0x1f; + t2 = get_2_ci(opcode); if(t2 & (1<AC = (i960->AC & ~7) | 2; - i960->IP += get_disp_s(i960, opcode); + m_AC = (m_AC & ~7) | 2; + m_IP += get_disp_s(opcode); } else - i960->AC &= ~7; + m_AC &= ~7; break; case 0x39: // cmpibg - i960->icount -= 4; - t1 = get_1_ci(i960, opcode); - t2 = get_2_ci(i960, opcode); - cmp_s(i960, t1, t2); - bxx_s(i960, opcode, 1); + m_icount -= 4; + t1 = get_1_ci(opcode); + t2 = get_2_ci(opcode); + cmp_s(t1, t2); + bxx_s(opcode, 1); break; case 0x3a: // cmpibe - i960->icount -= 4; - t1 = get_1_ci(i960, opcode); - t2 = get_2_ci(i960, opcode); - cmp_s(i960, t1, t2); - bxx_s(i960, opcode, 2); + m_icount -= 4; + t1 = get_1_ci(opcode); + t2 = get_2_ci(opcode); + cmp_s(t1, t2); + bxx_s(opcode, 2); break; case 0x3b: // cmpibge - i960->icount -= 4; - t1 = get_1_ci(i960, opcode); - t2 = get_2_ci(i960, opcode); - cmp_s(i960, t1, t2); - bxx_s(i960, opcode, 3); + m_icount -= 4; + t1 = get_1_ci(opcode); + t2 = get_2_ci(opcode); + cmp_s(t1, t2); + bxx_s(opcode, 3); break; case 0x3c: // cmpibl - i960->icount -= 4; - t1 = get_1_ci(i960, opcode); - t2 = get_2_ci(i960, opcode); - cmp_s(i960, t1, t2); - bxx_s(i960, opcode, 4); + m_icount -= 4; + t1 = get_1_ci(opcode); + t2 = get_2_ci(opcode); + cmp_s(t1, t2); + bxx_s(opcode, 4); break; case 0x3d: // cmpibne - i960->icount -= 4; - t1 = get_1_ci(i960, opcode); - t2 = get_2_ci(i960, opcode); - cmp_s(i960, t1, t2); - bxx_s(i960, opcode, 5); + m_icount -= 4; + t1 = get_1_ci(opcode); + t2 = get_2_ci(opcode); + cmp_s(t1, t2); + bxx_s(opcode, 5); break; case 0x3e: // cmpible - i960->icount -= 4; - t1 = get_1_ci(i960, opcode); - t2 = get_2_ci(i960, opcode); - cmp_s(i960, t1, t2); - bxx_s(i960, opcode, 6); + m_icount -= 4; + t1 = get_1_ci(opcode); + t2 = get_2_ci(opcode); + cmp_s(t1, t2); + bxx_s(opcode, 6); break; case 0x58: switch((opcode >> 7) & 0xf) { case 0x0: // notbit - i960->icount -= 2; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, t2 ^ (1<<(t1 & 31))); + m_icount -= 2; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, t2 ^ (1<<(t1 & 31))); break; case 0x1: // and - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, t2 & t1); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, t2 & t1); break; case 0x2: // andnot - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, t2 & ~t1); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, t2 & ~t1); break; case 0x3: // setbit - i960->icount -= 2; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, t2 | (1<<(t1 & 31))); + m_icount -= 2; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, t2 | (1<<(t1 & 31))); break; case 0x4: // notand - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, (~t2) & t1); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, (~t2) & t1); break; case 0x6: // xor - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, t2 ^ t1); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, t2 ^ t1); break; case 0x7: // or - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, t2 | t1); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, t2 | t1); break; case 0x8: // nor - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, ((~t2) & (~t1))); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, ((~t2) & (~t1))); break; case 0x9: // xnor - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, ~(t2 ^ t1)); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, ~(t2 ^ t1)); break; case 0xa: // not - i960->icount--; - t1 = get_1_ri(i960, opcode); - set_ri(i960, opcode, ~t1); + m_icount--; + t1 = get_1_ri(opcode); + set_ri(opcode, ~t1); break; case 0xb: // ornot - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, t2 | ~t1); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, t2 | ~t1); break; case 0xc: // clrbit - i960->icount -= 2; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, t2 & ~(1<<(t1 & 31))); + m_icount -= 2; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, t2 & ~(1<<(t1 & 31))); break; case 0xd: // notor - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, (~t2) | t1); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, (~t2) | t1); break; case 0xe: // nand - i960->icount -= 2; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, ~t2 | ~t1); + m_icount -= 2; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, ~t2 | ~t1); break; case 0xf: // alterbit - i960->icount -= 2; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - if(i960->AC & 2) - set_ri(i960, opcode, t2 | (1<<(t1 & 31))); + m_icount -= 2; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + if(m_AC & 2) + set_ri(opcode, t2 | (1<<(t1 & 31))); else - set_ri(i960, opcode, t2 & ~(1<<(t1 & 31))); + set_ri(opcode, t2 & ~(1<<(t1 & 31))); break; default: - fatalerror("I960: %x: Unhandled 58.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 58.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x59: switch((opcode >> 7) & 0xf) { case 0x0: // addo - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, t2+t1); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, t2+t1); break; case 0x1: // addi // #### overflow - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, t2+t1); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, t2+t1); break; case 0x2: // subo - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, t2-t1); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, t2-t1); break; case 0x3: // subi // #### overflow - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, t2-t1); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, t2-t1); break; case 0x8: // shro - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, t2>>t1); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, t2>>t1); break; case 0xa: // shrdi - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); if(((INT32)t2) < 0) { if(t2 & ((1<>t1)+1); + set_ri(opcode, (((INT32)t2)>>t1)+1); else - set_ri(i960, opcode, ((INT32)t2)>>t1); + set_ri(opcode, ((INT32)t2)>>t1); } else - set_ri(i960, opcode, t2>>t1); + set_ri(opcode, t2>>t1); break; case 0xb: // shri - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, ((INT32)t2)>>t1); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, ((INT32)t2)>>t1); break; case 0xc: // shlo - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, t2<icount--; - t1 = get_1_ri(i960, opcode) & 0x1f; - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, (t2<>(32-t1))); + m_icount--; + t1 = get_1_ri(opcode) & 0x1f; + t2 = get_2_ri(opcode); + set_ri(opcode, (t2<>(32-t1))); break; case 0xe: // shli // missing overflow - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, t2<PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 59.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x5a: switch((opcode >> 7) & 0xf) { case 0x0: // cmpo - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - cmp_u(i960, t1, t2); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + cmp_u(t1, t2); break; case 0x1: // cmpi - i960->icount--; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - cmp_s(i960, t1, t2); + m_icount--; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + cmp_s(t1, t2); break; case 0x2: // concmpo - i960->icount--; - if(!(i960->AC & 0x4)) { - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - concmp_u(i960, t1, t2); + m_icount--; + if(!(m_AC & 0x4)) { + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + concmp_u(t1, t2); } break; case 0x3: // concmpi - i960->icount--; - if(!(i960->AC & 0x4)) { - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - concmp_s(i960, t1, t2); + m_icount--; + if(!(m_AC & 0x4)) { + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + concmp_s(t1, t2); } break; case 0x4: // cmpinco - i960->icount -= 2; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - cmp_u(i960, t1, t2); - set_ri(i960, opcode, t2+1); + m_icount -= 2; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + cmp_u(t1, t2); + set_ri(opcode, t2+1); break; case 0x5: // cmpinci - i960->icount -= 2; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - cmp_s(i960, t1, t2); - set_ri(i960, opcode, t2+1); + m_icount -= 2; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + cmp_s(t1, t2); + set_ri(opcode, t2+1); break; case 0x6: // cmpdeco - i960->icount -= 2; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - cmp_u(i960, t1, t2); - set_ri(i960, opcode, t2-1); + m_icount -= 2; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + cmp_u(t1, t2); + set_ri(opcode, t2-1); break; case 0x7: // cmpdeci - i960->icount -= 2; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - cmp_s(i960, t1, t2); - set_ri(i960, opcode, t2-1); + m_icount -= 2; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + cmp_s(t1, t2); + set_ri(opcode, t2-1); break; case 0xe: // chkbit - i960->icount -= 2; - t1 = get_1_ri(i960, opcode) & 0x1f; - t2 = get_2_ri(i960, opcode); + m_icount -= 2; + t1 = get_1_ri(opcode) & 0x1f; + t2 = get_2_ri(opcode); if(t2 & (1<AC = (i960->AC & ~7) | 2; + m_AC = (m_AC & ~7) | 2; else - i960->AC &= ~7; + m_AC &= ~7; break; default: - fatalerror("I960: %x: Unhandled 5a.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 5a.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; @@ -1126,17 +1089,17 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) { UINT64 res; - i960->icount -= 2; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - res = t2+(t1+((i960->AC>>1)&1)); - set_ri(i960, opcode, res&0xffffffff); + m_icount -= 2; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + res = t2+(t1+((m_AC>>1)&1)); + set_ri(opcode, res&0xffffffff); - i960->AC &= ~0x3; // clear C and V + m_AC &= ~0x3; // clear C and V // set carry - i960->AC |= ((res) & (((UINT64)1) << 32)) ? 0x2 : 0; + m_AC |= ((res) & (((UINT64)1) << 32)) ? 0x2 : 0; // set overflow - i960->AC |= (((res) ^ (t1)) & ((res) ^ (t2)) & 0x80000000) ? 1: 0; + m_AC |= (((res) ^ (t1)) & ((res) ^ (t2)) & 0x80000000) ? 1: 0; } break; @@ -1144,120 +1107,120 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) { UINT64 res; - i960->icount -= 2; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - res = t2-(t1+((i960->AC>>1)&1)); - set_ri(i960, opcode, res&0xffffffff); + m_icount -= 2; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + res = t2-(t1+((m_AC>>1)&1)); + set_ri(opcode, res&0xffffffff); - i960->AC &= ~0x3; // clear C and V + m_AC &= ~0x3; // clear C and V // set carry - i960->AC |= ((res) & (((UINT64)1) << 32)) ? 0x2 : 0; + m_AC |= ((res) & (((UINT64)1) << 32)) ? 0x2 : 0; // set overflow - i960->AC |= (((t2) ^ (t1)) & ((t2) ^ (res)) & 0x80000000) ? 1 : 0; + m_AC |= (((t2) ^ (t1)) & ((t2) ^ (res)) & 0x80000000) ? 1 : 0; } break; default: - fatalerror("I960: %x: Unhandled 5b.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 5b.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x5c: switch((opcode >> 7) & 0xf) { case 0xc: // mov - i960->icount -= 2; - t1 = get_1_ri(i960, opcode); - set_ri(i960, opcode, t1); + m_icount -= 2; + t1 = get_1_ri(opcode); + set_ri(opcode, t1); break; default: - fatalerror("I960: %x: Unhandled 5c.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 5c.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x5d: switch((opcode >> 7) & 0xf) { case 0xc: // movl - i960->icount -= 2; + m_icount -= 2; t2 = (opcode>>19) & 0x1e; if(opcode & 0x00000800) { // litteral t1 = opcode & 0x1f; - i960->r[t2] = i960->r[t2+1] = t1; + m_r[t2] = m_r[t2+1] = t1; } else - memcpy(i960->r+t2, i960->r+(opcode & 0x1f), 2*sizeof(UINT32)); + memcpy(m_r+t2, m_r+(opcode & 0x1f), 2*sizeof(UINT32)); break; default: - fatalerror("I960: %x: Unhandled 5d.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 5d.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x5e: switch((opcode >> 7) & 0xf) { case 0xc: // movt - i960->icount -= 3; + m_icount -= 3; t2 = (opcode>>19) & 0x1c; if(opcode & 0x00000800) { // litteral t1 = opcode & 0x1f; - i960->r[t2] = i960->r[t2+1] = i960->r[t2+2]= t1; + m_r[t2] = m_r[t2+1] = m_r[t2+2]= t1; } else - memcpy(i960->r+t2, i960->r+(opcode & 0x1f), 3*sizeof(UINT32)); + memcpy(m_r+t2, m_r+(opcode & 0x1f), 3*sizeof(UINT32)); break; default: - fatalerror("I960: %x: Unhandled 5e.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 5e.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x5f: switch((opcode >> 7) & 0xf) { case 0xc: // movq - i960->icount -= 4; + m_icount -= 4; t2 = (opcode>>19) & 0x1c; if(opcode & 0x00000800) { // litteral t1 = opcode & 0x1f; - i960->r[t2] = i960->r[t2+1] = i960->r[t2+2] = i960->r[t2+3] = t1; + m_r[t2] = m_r[t2+1] = m_r[t2+2] = m_r[t2+3] = t1; } else - memcpy(i960->r+t2, i960->r+(opcode & 0x1f), 4*sizeof(UINT32)); + memcpy(m_r+t2, m_r+(opcode & 0x1f), 4*sizeof(UINT32)); break; default: - fatalerror("I960: %x: Unhandled 5f.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 5f.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x60: switch((opcode >> 7) & 0xf) { case 0x0: // synmov - i960->icount -= 6; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); + m_icount -= 6; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); // interrupt control register if(t1 == 0xff000004) - i960->ICR = i960->program->read_dword(t2); + m_ICR = m_program->read_dword(t2); else - i960->program->write_dword(t1, i960->program->read_dword(t2)); - i960->AC = (i960->AC & ~7) | 2; + m_program->write_dword(t1, m_program->read_dword(t2)); + m_AC = (m_AC & ~7) | 2; break; case 0x2: // synmovq - i960->icount -= 12; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); + m_icount -= 12; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); if(t1 == 0xff000010) - send_iac(i960, t2); + send_iac(t2); else { - i960->program->write_dword(t1, i960->program->read_dword(t2)); - i960->program->write_dword(t1+4, i960->program->read_dword(t2+4)); - i960->program->write_dword(t1+8, i960->program->read_dword(t2+8)); - i960->program->write_dword(t1+12, i960->program->read_dword(t2+12)); + m_program->write_dword(t1, m_program->read_dword(t2)); + m_program->write_dword(t1+4, m_program->read_dword(t2+4)); + m_program->write_dword(t1+8, m_program->read_dword(t2+8)); + m_program->write_dword(t1+12, m_program->read_dword(t2+12)); } - i960->AC = (i960->AC & ~7) | 2; + m_AC = (m_AC & ~7) | 2; break; default: - fatalerror("I960: %x: Unhandled 60.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 60.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; @@ -1268,22 +1231,22 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) UINT32 res = 0xffffffff; int i; - i960->icount -= 10; + m_icount -= 10; - t1 = get_1_ri(i960, opcode); - i960->AC &= ~7; + t1 = get_1_ri(opcode); + m_AC &= ~7; for (i = 31; i >= 0; i--) { if (!(t1 & (1<AC |= 2; + m_AC |= 2; res = i; break; } } - set_ri(i960, opcode, res); + set_ri(opcode, res); } break; @@ -1292,325 +1255,325 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) UINT32 res = 0xffffffff; int i; - i960->icount -= 10; + m_icount -= 10; - t1 = get_1_ri(i960, opcode); - i960->AC &= ~7; + t1 = get_1_ri(opcode); + m_AC &= ~7; for (i = 31; i >= 0; i--) { if (t1 & (1<AC |= 2; + m_AC |= 2; res = i; break; } } - set_ri(i960, opcode, res); + set_ri(opcode, res); } break; case 0x5: // modac - i960->icount -= 10; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, i960->AC); - i960->AC = (i960->AC & ~t1) | (t2 & t1); + m_icount -= 10; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, m_AC); + m_AC = (m_AC & ~t1) | (t2 & t1); break; default: - fatalerror("I960: %x: Unhandled 64.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 64.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x65: switch((opcode >> 7) & 0xf) { case 0x5: // modpc - i960->icount -= 10; - t1 = i960->PC; - t2 = get_2_ri(i960, opcode); - i960->PC = (i960->PC & ~t2) | (i960->r[(opcode>>19) & 0x1f] & t2); - set_ri(i960, opcode, t1); + m_icount -= 10; + t1 = m_PC; + t2 = get_2_ri(opcode); + m_PC = (m_PC & ~t2) | (m_r[(opcode>>19) & 0x1f] & t2); + set_ri(opcode, t1); break; default: - fatalerror("I960: %x: Unhandled 65.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 65.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x66: switch((opcode >> 7) & 0xf) { case 0xd: // flushreg - if (i960->rcache_pos > 4) + if (m_rcache_pos > 4) { - i960->rcache_pos = 4; + m_rcache_pos = 4; } - for(t1=0; t1 < i960->rcache_pos; t1++) + for(t1=0; t1 < m_rcache_pos; t1++) { int i; for (i = 0; i < 0x10; i++) { - i960->program->write_dword(i960->rcache_frame_addr[t1] + (i * sizeof(UINT32)), i960->rcache[t1][i]); + m_program->write_dword(m_rcache_frame_addr[t1] + (i * sizeof(UINT32)), m_rcache[t1][i]); } } - i960->rcache_pos = 0; + m_rcache_pos = 0; break; default: - fatalerror("I960: %x: Unhandled 66.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 66.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x67: switch((opcode >> 7) & 0xf) { case 0x0: // emul - i960->icount -= 37; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); + m_icount -= 37; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); - set_ri64(i960, opcode, (INT64)t1 * (INT64)t2); + set_ri64(opcode, (INT64)t1 * (INT64)t2); break; case 0x1: // ediv - i960->icount -= 37; + m_icount -= 37; { UINT64 src1, src2; - src1 = get_1_ri(i960, opcode); - src2 = get_2_ri64(i960, opcode); + src1 = get_1_ri(opcode); + src2 = get_2_ri64(opcode); - set_ri2(i960, opcode, src2 % src1, src2 / src1); + set_ri2(opcode, src2 % src1, src2 / src1); } break; case 0x4: // cvtir - i960->icount -= 30; - t1 = get_1_ri(i960, opcode); - set_rif(i960, opcode, (double)(INT32)t1); + m_icount -= 30; + t1 = get_1_ri(opcode); + set_rif(opcode, (double)(INT32)t1); break; case 0x5: // cvtilr - i960->icount -= 30; - t1 = get_1_ri(i960, opcode); - set_rifl(i960, opcode, (double)(INT32)t1); + m_icount -= 30; + t1 = get_1_ri(opcode); + set_rifl(opcode, (double)(INT32)t1); break; case 0x6: // scalerl - i960->icount -= 30; - t1 = get_1_ri(i960, opcode); - t2f = get_2_rifl(i960, opcode); - set_rifl(i960, opcode, t2f * pow(2.0, (double)(INT32)t1)); + m_icount -= 30; + t1 = get_1_ri(opcode); + t2f = get_2_rifl(opcode); + set_rifl(opcode, t2f * pow(2.0, (double)(INT32)t1)); break; case 0x7: // scaler - i960->icount -= 30; - t1 = get_1_ri(i960, opcode); - t2f = get_2_rif(i960, opcode); - set_rif(i960, opcode, t2f * pow(2.0, (double)(INT32)t1)); + m_icount -= 30; + t1 = get_1_ri(opcode); + t2f = get_2_rif(opcode); + set_rif(opcode, t2f * pow(2.0, (double)(INT32)t1)); break; default: - fatalerror("I960: %x: Unhandled 67.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 67.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x68: switch((opcode >> 7) & 0xf) { case 0x0: // atanr - i960->icount -= 267; - t1f = get_1_rif(i960, opcode); - t2f = get_2_rif(i960, opcode); - set_rif(i960, opcode, atan2(t2f, t1f)); + m_icount -= 267; + t1f = get_1_rif(opcode); + t2f = get_2_rif(opcode); + set_rif(opcode, atan2(t2f, t1f)); break; case 0x1: // logepr - i960->icount -= 400; - t1f = get_1_rif(i960, opcode); - t2f = get_2_rif(i960, opcode); - set_rif(i960, opcode, t2f*log(t1f+1.0)/log(2.0)); + m_icount -= 400; + t1f = get_1_rif(opcode); + t2f = get_2_rif(opcode); + set_rif(opcode, t2f*log(t1f+1.0)/log(2.0)); break; case 0x3: // remr - i960->icount -= 67; // (67 to 75878 depending on opcodes!!!) - t1f = get_1_rif(i960, opcode); - t2f = get_2_rif(i960, opcode); - set_rif(i960, opcode, fmod(t2f, t1f)); + m_icount -= 67; // (67 to 75878 depending on opcodes!!!) + t1f = get_1_rif(opcode); + t2f = get_2_rif(opcode); + set_rif(opcode, fmod(t2f, t1f)); break; case 0x5: // cmpr - i960->icount -= 10; - t1f = get_1_rif(i960, opcode); - t2f = get_2_rif(i960, opcode); - cmp_d(i960, t1f, t2f); + m_icount -= 10; + t1f = get_1_rif(opcode); + t2f = get_2_rif(opcode); + cmp_d(t1f, t2f); break; case 0x8: // sqrtr - i960->icount -= 104; - t1f = get_1_rif(i960, opcode); - set_rif(i960, opcode, sqrt(t1f)); + m_icount -= 104; + t1f = get_1_rif(opcode); + set_rif(opcode, sqrt(t1f)); break; case 0xa: // logbnr - i960->icount -= 37; - t1f = get_1_rif(i960, opcode); - set_rif(i960, opcode, logb(t1f)); + m_icount -= 37; + t1f = get_1_rif(opcode); + set_rif(opcode, logb(t1f)); break; case 0xb: // roundr { - INT32 st1 = get_1_rif(i960, opcode); - i960->icount -= 69; - set_rif(i960, opcode, (double)st1); + INT32 st1 = get_1_rif(opcode); + m_icount -= 69; + set_rif(opcode, (double)st1); } break; case 0xc: // sinr - i960->icount -= 406; - t1f = get_1_rif(i960, opcode); - set_rif(i960, opcode, sin(t1f)); + m_icount -= 406; + t1f = get_1_rif(opcode); + set_rif(opcode, sin(t1f)); break; case 0xd: // cosr - i960->icount -= 406; - t1f = get_1_rif(i960, opcode); - set_rif(i960, opcode, sin(t1f)); + m_icount -= 406; + t1f = get_1_rif(opcode); + set_rif(opcode, sin(t1f)); break; case 0xe: // tanr - i960->icount -= 293; - t1f = get_1_rif(i960, opcode); - set_rif(i960, opcode, tan(t1f)); + m_icount -= 293; + t1f = get_1_rif(opcode); + set_rif(opcode, tan(t1f)); break; default: - fatalerror("I960: %x: Unhandled 68.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 68.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x69: switch((opcode >> 7) & 0xf) { case 0x0: // atanrl - i960->icount -= 350; - t1f = get_1_rifl(i960, opcode); - t2f = get_2_rifl(i960, opcode); - set_rifl(i960, opcode, atan2(t2f, t1f)); + m_icount -= 350; + t1f = get_1_rifl(opcode); + t2f = get_2_rifl(opcode); + set_rifl(opcode, atan2(t2f, t1f)); break; case 0x2: // logrl - i960->icount -= 438; - t1f = get_1_rifl(i960, opcode); - set_rifl(i960, opcode, log(t1f)); + m_icount -= 438; + t1f = get_1_rifl(opcode); + set_rifl(opcode, log(t1f)); break; case 0x5: // cmprl - i960->icount -= 12; - t1f = get_1_rifl(i960, opcode); - t2f = get_2_rifl(i960, opcode); - cmp_d(i960, t1f, t2f); + m_icount -= 12; + t1f = get_1_rifl(opcode); + t2f = get_2_rifl(opcode); + cmp_d(t1f, t2f); break; case 0x8: // sqrtrl - i960->icount -= 104; - t1f = get_1_rifl(i960, opcode); - set_rifl(i960, opcode, sqrt(t1f)); + m_icount -= 104; + t1f = get_1_rifl(opcode); + set_rifl(opcode, sqrt(t1f)); break; case 0x9: // exprl - i960->icount -= 334; - t1f = get_1_rifl(i960, opcode); - set_rifl(i960, opcode, pow(2.0, t1f)-1.0); + m_icount -= 334; + t1f = get_1_rifl(opcode); + set_rifl(opcode, pow(2.0, t1f)-1.0); break; case 0xa: // logbnrl - i960->icount -= 37; - t1f = get_1_rifl(i960, opcode); - set_rifl(i960, opcode, logb(t1f)); + m_icount -= 37; + t1f = get_1_rifl(opcode); + set_rifl(opcode, logb(t1f)); break; case 0xb: // roundrl { - INT32 st1 = get_1_rifl(i960, opcode); - i960->icount -= 70; - set_rifl(i960, opcode, (double)st1); + INT32 st1 = get_1_rifl(opcode); + m_icount -= 70; + set_rifl(opcode, (double)st1); } break; case 0xc: // sinrl - i960->icount -= 441; - t1f = get_1_rifl(i960, opcode); - set_rifl(i960, opcode, sin(t1f)); + m_icount -= 441; + t1f = get_1_rifl(opcode); + set_rifl(opcode, sin(t1f)); break; case 0xd: // cosrl - i960->icount -= 441; - t1f = get_1_rifl(i960, opcode); - set_rifl(i960, opcode, cos(t1f)); + m_icount -= 441; + t1f = get_1_rifl(opcode); + set_rifl(opcode, cos(t1f)); break; case 0xe: // tanrl - i960->icount -= 323; - t1f = get_1_rifl(i960, opcode); - set_rifl(i960, opcode, tan(t1f)); + m_icount -= 323; + t1f = get_1_rifl(opcode); + set_rifl(opcode, tan(t1f)); break; default: - fatalerror("I960: %x: Unhandled 69.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 69.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x6c: switch((opcode >> 7) & 0xf) { case 0x0: // cvtri - i960->icount -= 33; - t1f = get_1_rif(i960, opcode); + m_icount -= 33; + t1f = get_1_rif(opcode); // apply rounding mode // we do this a little indirectly to avoid some odd GCC warnings t2f = 0.0; - switch((i960->AC>>30)&3) + switch((m_AC>>30)&3) { case 0: t2f = floor(t1f+0.5); break; case 1: t2f = floor(t1f); break; case 2: t2f = ceil(t1f); break; case 3: t2f = t1f; break; } - set_ri(i960, opcode, (INT32)t2f); + set_ri(opcode, (INT32)t2f); break; case 0x2: // cvtzri - i960->icount -= 43; - t1f = get_1_rif(i960, opcode); - set_ri(i960, opcode, (INT32)t1f); + m_icount -= 43; + t1f = get_1_rif(opcode); + set_ri(opcode, (INT32)t1f); break; case 0x3: // cvtzril - i960->icount -= 44; - t1f = get_1_rif(i960, opcode); - set_ri64(i960, opcode, (INT64)t1f); + m_icount -= 44; + t1f = get_1_rif(opcode); + set_ri64(opcode, (INT64)t1f); break; case 0x9: // movr - i960->icount -= 5; - t1f = get_1_rif(i960, opcode); - set_rif(i960, opcode, t1f); + m_icount -= 5; + t1f = get_1_rif(opcode); + set_rif(opcode, t1f); break; default: - fatalerror("I960: %x: Unhandled 6c.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 6c.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x6d: switch((opcode >> 7) & 0xf) { case 0x9: // movrl - i960->icount -= 6; - t1f = get_1_rifl(i960, opcode); - set_rifl(i960, opcode, t1f); + m_icount -= 6; + t1f = get_1_rifl(opcode); + set_rifl(opcode, t1f); break; default: - fatalerror("I960: %x: Unhandled 6d.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 6d.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; @@ -1620,20 +1583,20 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) { UINT32 *src=0, *dst=0; - i960->icount -= 8; + m_icount -= 8; if(!(opcode & 0x00000800)) { - src = (UINT32 *)&i960->r[opcode & 0x1e]; + src = (UINT32 *)&m_r[opcode & 0x1e]; } else { int idx = opcode & 0x1f; if(idx < 4) - src = (UINT32 *)&i960->fp[idx]; + src = (UINT32 *)&m_fp[idx]; } if(!(opcode & 0x00002000)) { - dst = (UINT32 *)&i960->r[(opcode>>19) & 0x1e]; + dst = (UINT32 *)&m_r[(opcode>>19) & 0x1e]; } else if(!(opcode & 0x00e00000)) - dst = (UINT32 *)&i960->fp[(opcode>>19) & 3]; + dst = (UINT32 *)&m_fp[(opcode>>19) & 3]; dst[0] = src[0]; dst[1] = src[1]; @@ -1641,222 +1604,222 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) } break; case 0x2: // cpysre - i960->icount -= 8; - t1f = get_1_rifl(i960, opcode); - t2f = get_2_rifl(i960, opcode); + m_icount -= 8; + t1f = get_1_rifl(opcode); + t2f = get_2_rifl(opcode); if (t2f >= 0.0) - set_rifl(i960, opcode, fabs(t1f)); + set_rifl(opcode, fabs(t1f)); else - set_rifl(i960, opcode, -fabs(t1f)); + set_rifl(opcode, -fabs(t1f)); break; default: - fatalerror("I960: %x: Unhandled 6e.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 6e.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x70: switch((opcode >> 7) & 0xf) { case 0x1: // mulo - i960->icount -= 18; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, t2*t1); + m_icount -= 18; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, t2*t1); break; case 0x8: // remo - i960->icount -= 37; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, t2%t1); + m_icount -= 37; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, t2%t1); break; case 0xb: // divo - i960->icount -= 37; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); + m_icount -= 37; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); if (t1 == 0) // HACK! - set_ri(i960, opcode, 0); + set_ri(opcode, 0); else - set_ri(i960, opcode, t2/t1); + set_ri(opcode, t2/t1); break; default: - fatalerror("I960: %x: Unhandled 70.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 70.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x74: switch((opcode >> 7) & 0xf) { case 0x1: // muli - i960->icount -= 18; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, ((INT32)t2)*((INT32)t1)); + m_icount -= 18; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, ((INT32)t2)*((INT32)t1)); break; case 0x8: // remi - i960->icount -= 37; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, ((INT32)t2)%((INT32)t1)); + m_icount -= 37; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, ((INT32)t2)%((INT32)t1)); break; case 0x9:{// modi INT32 src1, src2, dst; - i960->icount -= 37; - src1 = (INT32)get_1_ri(i960, opcode); - src2 = (INT32)get_2_ri(i960, opcode); + m_icount -= 37; + src1 = (INT32)get_1_ri(opcode); + src2 = (INT32)get_2_ri(opcode); dst = src2 - ((src2/src1)*src1); if(((src2*src1) < 0) && (dst != 0)) dst += src1; - set_ri(i960, opcode, dst); + set_ri(opcode, dst); break; } case 0xb: // divi - i960->icount -= 37; - t1 = get_1_ri(i960, opcode); - t2 = get_2_ri(i960, opcode); - set_ri(i960, opcode, ((INT32)t2)/((INT32)t1)); + m_icount -= 37; + t1 = get_1_ri(opcode); + t2 = get_2_ri(opcode); + set_ri(opcode, ((INT32)t2)/((INT32)t1)); break; default: - fatalerror("I960: %x: Unhandled 74.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 74.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x78: switch((opcode >> 7) & 0xf) { case 0xb: // divr - i960->icount -= 35; - t1f = get_1_rif(i960, opcode); - t2f = get_2_rif(i960, opcode); - set_rif(i960, opcode, t2f/t1f); + m_icount -= 35; + t1f = get_1_rif(opcode); + t2f = get_2_rif(opcode); + set_rif(opcode, t2f/t1f); break; case 0xc: // mulr - i960->icount -= 18; - t1f = get_1_rif(i960, opcode); - t2f = get_2_rif(i960, opcode); - set_rif(i960, opcode, t2f*t1f); + m_icount -= 18; + t1f = get_1_rif(opcode); + t2f = get_2_rif(opcode); + set_rif(opcode, t2f*t1f); break; case 0xd: // subr - i960->icount -= 10; - t1f = get_1_rif(i960, opcode); - t2f = get_2_rif(i960, opcode); - set_rif(i960, opcode, t2f-t1f); + m_icount -= 10; + t1f = get_1_rif(opcode); + t2f = get_2_rif(opcode); + set_rif(opcode, t2f-t1f); break; case 0xf: // addr - i960->icount -= 10; - t1f = get_1_rif(i960, opcode); - t2f = get_2_rif(i960, opcode); - set_rif(i960, opcode, t2f+t1f); + m_icount -= 10; + t1f = get_1_rif(opcode); + t2f = get_2_rif(opcode); + set_rif(opcode, t2f+t1f); break; default: - fatalerror("I960: %x: Unhandled 78.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 78.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x79: switch((opcode >> 7) & 0xf) { case 0xb: // divrl - i960->icount -= 77; - t1f = get_1_rifl(i960, opcode); - t2f = get_2_rifl(i960, opcode); - set_rifl(i960, opcode, t2f/t1f); + m_icount -= 77; + t1f = get_1_rifl(opcode); + t2f = get_2_rifl(opcode); + set_rifl(opcode, t2f/t1f); break; case 0xc: // mulrl - i960->icount -= 36; - t1f = get_1_rifl(i960, opcode); - t2f = get_2_rifl(i960, opcode); - set_rifl(i960, opcode, t2f*t1f); + m_icount -= 36; + t1f = get_1_rifl(opcode); + t2f = get_2_rifl(opcode); + set_rifl(opcode, t2f*t1f); break; case 0xd: // subrl - i960->icount -= 13; - t1f = get_1_rifl(i960, opcode); - t2f = get_2_rifl(i960, opcode); - set_rifl(i960, opcode, t2f-t1f); + m_icount -= 13; + t1f = get_1_rifl(opcode); + t2f = get_2_rifl(opcode); + set_rifl(opcode, t2f-t1f); break; case 0xf: // addrl - i960->icount -= 13; - t1f = get_1_rifl(i960, opcode); - t2f = get_2_rifl(i960, opcode); - set_rifl(i960, opcode, t2f+t1f); + m_icount -= 13; + t1f = get_1_rifl(opcode); + t2f = get_2_rifl(opcode); + set_rifl(opcode, t2f+t1f); break; default: - fatalerror("I960: %x: Unhandled 79.%x\n", i960->PIP, (opcode >> 7) & 0xf); + fatalerror("I960: %x: Unhandled 79.%x\n", m_PIP, (opcode >> 7) & 0xf); } break; case 0x80: // ldob - i960->icount -= 4; - i960->r[(opcode>>19)&0x1f] = i960->program->read_byte(get_ea(i960, opcode)); + m_icount -= 4; + m_r[(opcode>>19)&0x1f] = m_program->read_byte(get_ea(opcode)); break; case 0x82: // stob - i960->icount -= 2; - i960->program->write_byte(get_ea(i960, opcode), i960->r[(opcode>>19)&0x1f]); + m_icount -= 2; + m_program->write_byte(get_ea(opcode), m_r[(opcode>>19)&0x1f]); break; case 0x84: // bx - i960->icount -= 3; - i960->IP = get_ea(i960, opcode); + m_icount -= 3; + m_IP = get_ea(opcode); break; case 0x85: // balx - i960->icount -= 5; - t1 = get_ea(i960, opcode); - i960->r[(opcode>>19)&0x1f] = i960->IP; - i960->IP = t1; + m_icount -= 5; + t1 = get_ea(opcode); + m_r[(opcode>>19)&0x1f] = m_IP; + m_IP = t1; break; case 0x86: // callx - t1 = get_ea(i960, opcode); - do_call(i960, t1, 0, i960->r[I960_SP]); + t1 = get_ea(opcode); + do_call(t1, 0, m_r[I960_SP]); break; case 0x88: // ldos - i960->icount -= 4; - i960->r[(opcode>>19)&0x1f] = i960_read_word_unaligned(i960, get_ea(i960, opcode)); + m_icount -= 4; + m_r[(opcode>>19)&0x1f] = i960_read_word_unaligned(get_ea(opcode)); break; case 0x8a: // stos - i960->icount -= 2; - i960_write_word_unaligned(i960, get_ea(i960, opcode), i960->r[(opcode>>19)&0x1f]); + m_icount -= 2; + i960_write_word_unaligned(get_ea(opcode), m_r[(opcode>>19)&0x1f]); break; case 0x8c: // lda - i960->icount--; - i960->r[(opcode>>19)&0x1f] = get_ea(i960, opcode); + m_icount--; + m_r[(opcode>>19)&0x1f] = get_ea(opcode); break; case 0x90: // ld - i960->icount -= 4; - i960->r[(opcode>>19)&0x1f] = i960_read_dword_unaligned(i960, get_ea(i960, opcode)); + m_icount -= 4; + m_r[(opcode>>19)&0x1f] = i960_read_dword_unaligned(get_ea(opcode)); break; case 0x92: // st - i960->icount -= 2; - i960_write_dword_unaligned(i960, get_ea(i960, opcode), i960->r[(opcode>>19)&0x1f]); + m_icount -= 2; + i960_write_dword_unaligned(get_ea(opcode), m_r[(opcode>>19)&0x1f]); break; case 0x98:{// ldl int i; - i960->icount -= 5; - t1 = get_ea(i960, opcode); + m_icount -= 5; + t1 = get_ea(opcode); t2 = (opcode>>19)&0x1e; - i960->bursting = 1; + m_bursting = 1; for(i=0; i<2; i++) { - i960->r[t2+i] = i960_read_dword_unaligned(i960, t1); - if(i960->bursting) + m_r[t2+i] = i960_read_dword_unaligned(t1); + if(m_bursting) t1 += 4; } break; @@ -1864,13 +1827,13 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) case 0x9a:{// stl int i; - i960->icount -= 3; - t1 = get_ea(i960, opcode); + m_icount -= 3; + t1 = get_ea(opcode); t2 = (opcode>>19)&0x1e; - i960->bursting = 1; + m_bursting = 1; for(i=0; i<2; i++) { - i960_write_dword_unaligned(i960, t1, i960->r[t2+i]); - if(i960->bursting) + i960_write_dword_unaligned(t1, m_r[t2+i]); + if(m_bursting) t1 += 4; } break; @@ -1878,13 +1841,13 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) case 0xa0:{// ldt int i; - i960->icount -= 6; - t1 = get_ea(i960, opcode); + m_icount -= 6; + t1 = get_ea(opcode); t2 = (opcode>>19)&0x1c; - i960->bursting = 1; + m_bursting = 1; for(i=0; i<3; i++) { - i960->r[t2+i] = i960_read_dword_unaligned(i960, t1); - if(i960->bursting) + m_r[t2+i] = i960_read_dword_unaligned(t1); + if(m_bursting) t1 += 4; } break; @@ -1892,13 +1855,13 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) case 0xa2:{// stt int i; - i960->icount -= 4; - t1 = get_ea(i960, opcode); + m_icount -= 4; + t1 = get_ea(opcode); t2 = (opcode>>19)&0x1c; - i960->bursting = 1; + m_bursting = 1; for(i=0; i<3; i++) { - i960_write_dword_unaligned(i960, t1, i960->r[t2+i]); - if(i960->bursting) + i960_write_dword_unaligned(t1, m_r[t2+i]); + if(m_bursting) t1 += 4; } break; @@ -1906,13 +1869,13 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) case 0xb0:{// ldq int i; - i960->icount -= 7; - t1 = get_ea(i960, opcode); + m_icount -= 7; + t1 = get_ea(opcode); t2 = (opcode>>19)&0x1c; - i960->bursting = 1; + m_bursting = 1; for(i=0; i<4; i++) { - i960->r[t2+i] = i960_read_dword_unaligned(i960, t1); - if(i960->bursting) + m_r[t2+i] = i960_read_dword_unaligned(t1); + if(m_bursting) t1 += 4; } break; @@ -1920,67 +1883,66 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode) case 0xb2:{// stq int i; - i960->icount -= 5; - t1 = get_ea(i960, opcode); + m_icount -= 5; + t1 = get_ea(opcode); t2 = (opcode>>19)&0x1c; - i960->bursting = 1; + m_bursting = 1; for(i=0; i<4; i++) { - i960_write_dword_unaligned(i960, t1, i960->r[t2+i]); - if(i960->bursting) + i960_write_dword_unaligned(t1, m_r[t2+i]); + if(m_bursting) t1 += 4; } break; } case 0xc0: // ldib - i960->icount -= 4; - i960->r[(opcode>>19)&0x1f] = (INT8)i960->program->read_byte(get_ea(i960, opcode)); + m_icount -= 4; + m_r[(opcode>>19)&0x1f] = (INT8)m_program->read_byte(get_ea(opcode)); break; case 0xc2: // stib - i960->icount -= 2; - i960->program->write_byte(get_ea(i960, opcode), i960->r[(opcode>>19)&0x1f]); + m_icount -= 2; + m_program->write_byte(get_ea(opcode), m_r[(opcode>>19)&0x1f]); break; case 0xc8: // ldis - i960->icount -= 4; - i960->r[(opcode>>19)&0x1f] = (INT16)i960_read_word_unaligned(i960, get_ea(i960, opcode)); + m_icount -= 4; + m_r[(opcode>>19)&0x1f] = (INT16)i960_read_word_unaligned(get_ea(opcode)); break; case 0xca: // stis - i960->icount -= 2; - i960_write_word_unaligned(i960, get_ea(i960, opcode), i960->r[(opcode>>19)&0x1f]); + m_icount -= 2; + i960_write_word_unaligned(get_ea(opcode), m_r[(opcode>>19)&0x1f]); break; default: - fatalerror("I960: %x: Unhandled %02x\n", i960->PIP, opcode >> 24); + fatalerror("I960: %x: Unhandled %02x\n", m_PIP, opcode >> 24); } } -static CPU_EXECUTE( i960 ) +void i960_cpu_device::execute_run() { - i960_state_t *i960 = get_safe_token(device); UINT32 opcode; - check_irqs(i960); - while(i960->icount > 0) { - i960->PIP = i960->IP; - debugger_instruction_hook(device, i960->IP); + check_irqs(); + while(m_icount > 0) { + m_PIP = m_IP; + debugger_instruction_hook(this, m_IP); - i960->bursting = 0; + m_bursting = 0; - opcode = i960->direct->read_decrypted_dword(i960->IP); - i960->IP += 4; + opcode = m_direct->read_decrypted_dword(m_IP); + m_IP += 4; - execute_op(i960, opcode); + execute_op(opcode); } } -static void set_irq_line(i960_state_t *i960, int irqline, int state) +void i960_cpu_device::execute_set_input(int irqline, int state) { - int int_tab = i960->program->read_dword(i960->PRCB+20); // interrupt table - int cpu_pri = (i960->PC>>16)&0x1f; + int int_tab = m_program->read_dword(m_PRCB+20); // interrupt table + int cpu_pri = (m_PC>>16)&0x1f; int vector =0; int priority; UINT32 pend, word, wordofs; @@ -1992,19 +1954,19 @@ static void set_irq_line(i960_state_t *i960, int irqline, int state) switch (irqline) { case I960_IRQ0: - vector = i960->ICR & 0xff; + vector = m_ICR & 0xff; break; case I960_IRQ1: - vector = (i960->ICR>>8)&0xff; + vector = (m_ICR>>8)&0xff; break; case I960_IRQ2: - vector = (i960->ICR>>16)&0xff; + vector = (m_ICR>>16)&0xff; break; case I960_IRQ3: - vector = (i960->ICR>>24)&0xff; + vector = (m_ICR>>24)&0xff; break; } @@ -2019,219 +1981,139 @@ static void set_irq_line(i960_state_t *i960, int irqline, int state) if(state) { // check if we can take this "right now" - if (((cpu_pri < priority) || (priority == 31)) && (i960->immediate_irq == 0)) + if (((cpu_pri < priority) || (priority == 31)) && (m_immediate_irq == 0)) { - i960->immediate_irq = 1; - i960->immediate_vector = vector; - i960->immediate_pri = priority; + m_immediate_irq = 1; + m_immediate_vector = vector; + m_immediate_pri = priority; } else { // store the interrupt in the "pending" table - pend = i960->program->read_dword(int_tab); + pend = m_program->read_dword(int_tab); pend |= (1 << priority); - i960->program->write_dword(int_tab, pend); + m_program->write_dword(int_tab, pend); // now bitfield-ize the vector word = ((vector / 32) * 4) + 4; wordofs = vector % 32; - pend = i960->program->read_dword(int_tab + word); + pend = m_program->read_dword(int_tab + word); pend |= (1 << wordofs); - i960->program->write_dword(int_tab + word, pend); + m_program->write_dword(int_tab + word, pend); } // and ack it to the core now that it's queued - (*i960->irq_cb)(i960->device, irqline); + standard_irq_callback(irqline); } } -static CPU_SET_INFO( i960 ) + +void i960_cpu_device::device_start() { - i960_state_t *i960 = get_safe_token(device); + m_program = &space(AS_PROGRAM); + m_direct = &m_program->direct(); - if(state >= CPUINFO_INT_REGISTER+I960_R0 && state <= CPUINFO_INT_REGISTER + I960_G15) { - i960->r[state - (CPUINFO_INT_REGISTER + I960_R0)] = info->i; - return; - } + save_item(NAME(m_PIP)); + save_item(NAME(m_SAT)); + save_item(NAME(m_PRCB)); + save_item(NAME(m_PC)); + save_item(NAME(m_AC)); + save_item(NAME(m_ICR)); + save_item(NAME(m_r)); + save_item(NAME(m_fp)); + save_item(NAME(m_rcache)); + save_item(NAME(m_rcache_frame_addr)); - switch(state) { - // Interfacing - case CPUINFO_INT_REGISTER + I960_IP: i960->IP = info->i; break; - case CPUINFO_INT_INPUT_STATE + I960_IRQ0: set_irq_line(i960, I960_IRQ0, info->i); break; - case CPUINFO_INT_INPUT_STATE + I960_IRQ1: set_irq_line(i960, I960_IRQ1, info->i); break; - case CPUINFO_INT_INPUT_STATE + I960_IRQ2: set_irq_line(i960, I960_IRQ2, info->i); break; - case CPUINFO_INT_INPUT_STATE + I960_IRQ3: set_irq_line(i960, I960_IRQ3, info->i); break; + state_add( I960_SAT, "sat", m_SAT).formatstr("%08X"); + state_add( I960_PRCB, "prcb", m_PRCB).formatstr("%08X"); + state_add( I960_PC, "pc", m_PC).formatstr("%08X"); + state_add( I960_AC, "ac", m_AC).formatstr("%08X"); + state_add( I960_IP, "ip", m_IP).formatstr("%08X"); + state_add( I960_PIP, "pip", m_PIP).formatstr("%08X"); + state_add( I960_R0, "pfp", m_r[ 0]).formatstr("%08X"); + state_add( I960_R1, "sp", m_r[ 1]).formatstr("%08X"); + state_add( I960_R2, "rip", m_r[ 2]).formatstr("%08X"); + state_add( I960_R3, "r3", m_r[ 3]).formatstr("%08X"); + state_add( I960_R4, "r4", m_r[ 4]).formatstr("%08X"); + state_add( I960_R5, "r5", m_r[ 5]).formatstr("%08X"); + state_add( I960_R6, "r6", m_r[ 6]).formatstr("%08X"); + state_add( I960_R7, "r7", m_r[ 7]).formatstr("%08X"); + state_add( I960_R8, "r8", m_r[ 8]).formatstr("%08X"); + state_add( I960_R9, "r9", m_r[ 9]).formatstr("%08X"); + state_add( I960_R10, "r10", m_r[10]).formatstr("%08X"); + state_add( I960_R11, "r11", m_r[11]).formatstr("%08X"); + state_add( I960_R12, "r12", m_r[12]).formatstr("%08X"); + state_add( I960_R13, "r13", m_r[13]).formatstr("%08X"); + state_add( I960_R14, "r14", m_r[14]).formatstr("%08X"); + state_add( I960_R15, "r15", m_r[15]).formatstr("%08X"); + state_add( I960_G0, "g0", m_r[16]).formatstr("%08X"); + state_add( I960_G1, "g1", m_r[17]).formatstr("%08X"); + state_add( I960_G2, "g2", m_r[18]).formatstr("%08X"); + state_add( I960_G3, "g3", m_r[19]).formatstr("%08X"); + state_add( I960_G4, "g4", m_r[20]).formatstr("%08X"); + state_add( I960_G5, "g5", m_r[21]).formatstr("%08X"); + state_add( I960_G6, "g6", m_r[22]).formatstr("%08X"); + state_add( I960_G7, "g7", m_r[23]).formatstr("%08X"); + state_add( I960_G8, "g8", m_r[24]).formatstr("%08X"); + state_add( I960_G9, "g9", m_r[25]).formatstr("%08X"); + state_add( I960_G10, "g10", m_r[26]).formatstr("%08X"); + state_add( I960_G11, "g11", m_r[27]).formatstr("%08X"); + state_add( I960_G12, "g12", m_r[28]).formatstr("%08X"); + state_add( I960_G13, "g13", m_r[29]).formatstr("%08X"); + state_add( I960_G14, "g14", m_r[30]).formatstr("%08X"); + state_add( I960_G15, "fp", m_r[31]).formatstr("%08X"); - default: - fatalerror("i960_set_info %x\n", state); + state_add( STATE_GENPC, "GENPC", m_IP).noshow(); + state_add( STATE_GENFLAGS, "GENFLAGS", m_AC).noshow().formatstr("%2s"); + + m_immediate_vector = 0; + m_immediate_pri = 0; + memset(m_rcache_frame_addr, 0, sizeof(m_rcache_frame_addr)); + memset(m_fp, 0, sizeof(m_fp)); + m_PIP = 0; + + m_icountptr = &m_icount; +} + +void i960_cpu_device::state_string_export(const device_state_entry &entry, astring &string) +{ + + static const char *const conditions[8] = + { + "no", "g", "e", "ge", "l", "ne", "le", "o" + }; + + switch (entry.index()) + { + case STATE_GENFLAGS: + string.printf("%s", conditions[m_AC & 7]); + break; } } -static CPU_INIT( i960 ) +void i960_cpu_device::device_reset() { - i960_state_t *i960 = get_safe_token(device); + m_SAT = m_program->read_dword(0); + m_PRCB = m_program->read_dword(4); + m_IP = m_program->read_dword(12); + m_PC = 0x001f2002; + m_AC = 0; + m_ICR = 0xff000000; + m_bursting = 0; + m_immediate_irq = 0; - i960->irq_cb = irqcallback; - i960->device = device; - i960->program = &device->space(AS_PROGRAM); - i960->direct = &i960->program->direct(); + memset(m_r, 0, sizeof(m_r)); + memset(m_rcache, 0, sizeof(m_rcache)); - device->save_item(NAME(i960->PIP)); - device->save_item(NAME(i960->SAT)); - device->save_item(NAME(i960->PRCB)); - device->save_item(NAME(i960->PC)); - device->save_item(NAME(i960->AC)); - device->save_item(NAME(i960->ICR)); - device->save_item(NAME(i960->r)); - device->save_item(NAME(i960->fp)); - device->save_item(NAME(i960->rcache)); - device->save_item(NAME(i960->rcache_frame_addr)); + m_r[I960_FP] = m_program->read_dword(m_PRCB+24); + m_r[I960_SP] = m_r[I960_FP] + 64; + m_rcache_pos = 0; } -static CPU_RESET( i960 ) + +offs_t i960_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { - i960_state_t *i960 = get_safe_token(device); - - i960->SAT = i960->program->read_dword(0); - i960->PRCB = i960->program->read_dword(4); - i960->IP = i960->program->read_dword(12); - i960->PC = 0x001f2002; - i960->AC = 0; - i960->ICR = 0xff000000; - i960->bursting = 0; - i960->immediate_irq = 0; - - memset(i960->r, 0, sizeof(i960->r)); - memset(i960->rcache, 0, sizeof(i960->rcache)); - - i960->r[I960_FP] = i960->program->read_dword(i960->PRCB+24); - i960->r[I960_SP] = i960->r[I960_FP] + 64; - i960->rcache_pos = 0; + extern CPU_DISASSEMBLE( i960 ); + return CPU_DISASSEMBLE_NAME(i960)(this, buffer, pc, oprom, opram, options); } -CPU_GET_INFO( i960 ) -{ - i960_state_t *i960 = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - - if(state >= CPUINFO_INT_REGISTER+I960_R0 && state <= CPUINFO_INT_REGISTER + I960_G15) { - info->i = i960->r[state - (CPUINFO_INT_REGISTER + I960_R0)]; - return; - } - - switch(state) { - // Interface functions and variables - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(i960); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i960); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(i960); break; - case CPUINFO_FCT_EXIT: info->exit = 0; break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(i960); break; - case CPUINFO_FCT_BURN: info->burn = 0; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i960); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &i960->icount; break; - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(i960_state_t); break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 8; break; - - // Bus sizes - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_LOGADDR_WIDTH_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_LOGADDR_WIDTH_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - case CPUINFO_INT_LOGADDR_WIDTH_IO: info->i = 0; break; - - // Internal maps - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map32 = NULL;break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map32 = NULL;break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_IO: info->internal_map32 = NULL;break; - - // CPU misc parameters - case CPUINFO_STR_NAME: strcpy(info->s, "i960KB"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_FLAGS: strcpy(info->s, i960_get_strflags(i960)); break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - case CPUINFO_INT_INPUT_LINES: info->i = 4; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = -1; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - - // CPU main state - case CPUINFO_INT_PC: info->i = i960->IP; break; - case CPUINFO_INT_SP: info->i = i960->r[I960_SP]; break; - case CPUINFO_INT_PREVIOUSPC: info->i = i960->PIP; break; - - case CPUINFO_INT_REGISTER + I960_SAT: info->i = i960->SAT; break; - case CPUINFO_INT_REGISTER + I960_PRCB: info->i = i960->PRCB; break; - case CPUINFO_INT_REGISTER + I960_PC: info->i = i960->PC; break; - case CPUINFO_INT_REGISTER + I960_AC: info->i = i960->AC; break; - case CPUINFO_INT_REGISTER + I960_IP: info->i = i960->IP; break; - case CPUINFO_INT_REGISTER + I960_PIP: info->i = i960->PIP; break; - - // CPU debug stuff - case CPUINFO_STR_REGISTER + I960_SAT: sprintf(info->s, "sat :%08x", i960->SAT); break; - case CPUINFO_STR_REGISTER + I960_PRCB: sprintf(info->s, "prcb :%08x", i960->PRCB); break; - case CPUINFO_STR_REGISTER + I960_PC: sprintf(info->s, "pc :%08x", i960->PC); break; - case CPUINFO_STR_REGISTER + I960_AC: sprintf(info->s, "ac :%08x", i960->AC); break; - case CPUINFO_STR_REGISTER + I960_IP: sprintf(info->s, "ip :%08x", i960->IP); break; - case CPUINFO_STR_REGISTER + I960_PIP: sprintf(info->s, "pip :%08x", i960->PIP); break; - - case CPUINFO_STR_REGISTER + I960_R0: sprintf(info->s, "pfp :%08x", i960->r[ 0]); break; - case CPUINFO_STR_REGISTER + I960_R1: sprintf(info->s, "sp :%08x", i960->r[ 1]); break; - case CPUINFO_STR_REGISTER + I960_R2: sprintf(info->s, "rip :%08x", i960->r[ 2]); break; - case CPUINFO_STR_REGISTER + I960_R3: sprintf(info->s, "r3 :%08x", i960->r[ 3]); break; - case CPUINFO_STR_REGISTER + I960_R4: sprintf(info->s, "r4 :%08x", i960->r[ 4]); break; - case CPUINFO_STR_REGISTER + I960_R5: sprintf(info->s, "r5 :%08x", i960->r[ 5]); break; - case CPUINFO_STR_REGISTER + I960_R6: sprintf(info->s, "r6 :%08x", i960->r[ 6]); break; - case CPUINFO_STR_REGISTER + I960_R7: sprintf(info->s, "r7 :%08x", i960->r[ 7]); break; - case CPUINFO_STR_REGISTER + I960_R8: sprintf(info->s, "r8 :%08x", i960->r[ 8]); break; - case CPUINFO_STR_REGISTER + I960_R9: sprintf(info->s, "r9 :%08x", i960->r[ 9]); break; - case CPUINFO_STR_REGISTER + I960_R10: sprintf(info->s, "r10 :%08x", i960->r[10]); break; - case CPUINFO_STR_REGISTER + I960_R11: sprintf(info->s, "r11 :%08x", i960->r[11]); break; - case CPUINFO_STR_REGISTER + I960_R12: sprintf(info->s, "r12 :%08x", i960->r[12]); break; - case CPUINFO_STR_REGISTER + I960_R13: sprintf(info->s, "r13 :%08x", i960->r[13]); break; - case CPUINFO_STR_REGISTER + I960_R14: sprintf(info->s, "r14 :%08x", i960->r[14]); break; - case CPUINFO_STR_REGISTER + I960_R15: sprintf(info->s, "r15 :%08x", i960->r[15]); break; - - case CPUINFO_STR_REGISTER + I960_G0: sprintf(info->s, "g0 :%08x", i960->r[16]); break; - case CPUINFO_STR_REGISTER + I960_G1: sprintf(info->s, "g1 :%08x", i960->r[17]); break; - case CPUINFO_STR_REGISTER + I960_G2: sprintf(info->s, "g2 :%08x", i960->r[18]); break; - case CPUINFO_STR_REGISTER + I960_G3: sprintf(info->s, "g3 :%08x", i960->r[19]); break; - case CPUINFO_STR_REGISTER + I960_G4: sprintf(info->s, "g4 :%08x", i960->r[20]); break; - case CPUINFO_STR_REGISTER + I960_G5: sprintf(info->s, "g5 :%08x", i960->r[21]); break; - case CPUINFO_STR_REGISTER + I960_G6: sprintf(info->s, "g6 :%08x", i960->r[22]); break; - case CPUINFO_STR_REGISTER + I960_G7: sprintf(info->s, "g7 :%08x", i960->r[23]); break; - case CPUINFO_STR_REGISTER + I960_G8: sprintf(info->s, "g8 :%08x", i960->r[24]); break; - case CPUINFO_STR_REGISTER + I960_G9: sprintf(info->s, "g9 :%08x", i960->r[25]); break; - case CPUINFO_STR_REGISTER + I960_G10: sprintf(info->s, "g10 :%08x", i960->r[26]); break; - case CPUINFO_STR_REGISTER + I960_G11: sprintf(info->s, "g11 :%08x", i960->r[27]); break; - case CPUINFO_STR_REGISTER + I960_G12: sprintf(info->s, "g12 :%08x", i960->r[28]); break; - case CPUINFO_STR_REGISTER + I960_G13: sprintf(info->s, "g13 :%08x", i960->r[29]); break; - case CPUINFO_STR_REGISTER + I960_G14: sprintf(info->s, "g14 :%08x", i960->r[30]); break; - case CPUINFO_STR_REGISTER + I960_G15: sprintf(info->s, "fp :%08x", i960->r[31]); break; - -// default: -// fatalerror("i960_get_info %x \n", state); - } -} - -// call from any read/write handler for a memory area that can't be bursted -// on the real hardware (e.g. Model 2's interrupt control registers) -void i960_noburst(device_t *device) -{ - i960_state_t *i960 = get_safe_token(device); - i960->bursting = 0; -} - -void i960_stall(device_t *device) -{ - i960_state_t *i960 = get_safe_token(device); - i960->IP = i960->PIP; -} - -DEFINE_LEGACY_CPU_DEVICE(I960, i960); diff --git a/src/emu/cpu/i960/i960.h b/src/emu/cpu/i960/i960.h index 0a93665a395..f968fbecd00 100644 --- a/src/emu/cpu/i960/i960.h +++ b/src/emu/cpu/i960/i960.h @@ -60,9 +60,116 @@ enum I960_IRQ3 = 3 }; -DECLARE_LEGACY_CPU_DEVICE(I960, i960); -void i960_noburst(device_t *device); -void i960_stall(device_t *device); +enum { I960_RCACHE_SIZE = 4 }; + + +class i960_cpu_device : public cpu_device +{ +public: + // construction/destruction + i960_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + + // call from any read/write handler for a memory area that can't be bursted + // on the real hardware (e.g. Model 2's interrupt control registers) + void i960_noburst() { m_bursting = 0; } + + void i960_stall() { m_IP = m_PIP; } + +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const { return 1; } /* ???? TODO: Exact timing unknown */ + virtual UINT32 execute_max_cycles() const { return 1; } /* ???? TODO: Exact timing unknown */ + virtual UINT32 execute_input_lines() const { return 4; } + virtual UINT32 execute_default_irq_vector() const { return 0xffffffff; } + virtual void execute_run(); + virtual void execute_set_input(int inputnum, int state); + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; } + + // device_state_interface overrides + void state_string_export(const device_state_entry &entry, astring &string); + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const { return 4; } + virtual UINT32 disasm_max_opcode_bytes() const { return 8; } + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + +private: + address_space_config m_program_config; + + UINT32 m_r[0x20]; + UINT32 m_rcache[I960_RCACHE_SIZE][0x10]; + UINT32 m_rcache_frame_addr[I960_RCACHE_SIZE]; + // rcache_pos = how deep in the stack we are. 0-(I960_RCACHE_SIZE-1) means in-cache. + // I960_RCACHE_SIZE or greater means out of cache, must save to memory. + INT32 m_rcache_pos; + + double m_fp[4]; + + UINT32 m_SAT; + UINT32 m_PRCB; + UINT32 m_PC; + UINT32 m_AC; + UINT32 m_IP; + UINT32 m_PIP; + UINT32 m_ICR; + int m_bursting; + + int m_immediate_irq; + int m_immediate_vector; + int m_immediate_pri; + + address_space *m_program; + direct_read_data *m_direct; + + int m_icount; + + UINT32 i960_read_dword_unaligned(UINT32 address); + UINT16 i960_read_word_unaligned(UINT32 address); + void i960_write_dword_unaligned(UINT32 address, UINT32 data); + void i960_write_word_unaligned(UINT32 address, UINT16 data); + void send_iac(UINT32 adr); + UINT32 get_ea(UINT32 opcode); + UINT32 get_1_ri(UINT32 opcode); + UINT32 get_2_ri(UINT32 opcode); + UINT64 get_2_ri64(UINT32 opcode); + void set_ri(UINT32 opcode, UINT32 val); + void set_ri2(UINT32 opcode, UINT32 val, UINT32 val2); + void set_ri64(UINT32 opcode, UINT64 val); + double get_1_rif(UINT32 opcode); + double get_2_rif(UINT32 opcode); + void set_rif(UINT32 opcode, double val); + double get_1_rifl(UINT32 opcode); + double get_2_rifl(UINT32 opcode); + void set_rifl(UINT32 opcode, double val); + UINT32 get_1_ci(UINT32 opcode); + UINT32 get_2_ci(UINT32 opcode); + UINT32 get_disp(UINT32 opcode); + UINT32 get_disp_s(UINT32 opcode); + void cmp_s(INT32 v1, INT32 v2); + void cmp_u(UINT32 v1, UINT32 v2); + void concmp_s(INT32 v1, INT32 v2); + void concmp_u(UINT32 v1, UINT32 v2); + void cmp_d(double v1, double v2); + void bxx(UINT32 opcode, int mask); + void bxx_s(UINT32 opcode, int mask); + void test(UINT32 opcode, int mask); + void execute_op(UINT32 opcode); + void take_interrupt(int vector, int lvl); + void check_irqs(); + void do_call(UINT32 adr, int type, UINT32 stack); + void do_ret_0(); + void do_ret(); +}; + + +extern const device_type I960; + #endif /* __I960_H__ */ diff --git a/src/mame/drivers/model2.c b/src/mame/drivers/model2.c index c52c42b4731..b33e719b5e5 100644 --- a/src/mame/drivers/model2.c +++ b/src/mame/drivers/model2.c @@ -183,7 +183,7 @@ static UINT32 copro_fifoout_pop(address_space &space) if (state->m_copro_fifoout_num == 0) { /* Reading from empty FIFO causes the i960 to enter wait state */ - i960_stall(&space.device()); + downcast(space.device()).i960_stall(); /* spin the main cpu and let the TGP catch up */ space.device().execute().spin_until_time(attotime::from_usec(100)); @@ -259,7 +259,7 @@ static void copro_fifoout_push(device_t *device, UINT32 data) /* Timers - these count down at 25 MHz and pull IRQ2 when they hit 0 */ READ32_MEMBER(model2_state::timers_r) { - i960_noburst(&space.device()); + m_maincpu->i960_noburst(); // if timer is running, calculate current value if (m_timerrun[offset]) @@ -278,7 +278,7 @@ WRITE32_MEMBER(model2_state::timers_w) { attotime period; - i960_noburst(&space.device()); + m_maincpu->i960_noburst(); COMBINE_DATA(&m_timervals[offset]); m_timerorig[offset] = m_timervals[offset]; @@ -935,7 +935,7 @@ READ32_MEMBER(model2_state::desert_unk_r) READ32_MEMBER(model2_state::model2_irq_r) { - i960_noburst(&space.device()); + m_maincpu->i960_noburst(); if (offset) { @@ -947,7 +947,7 @@ READ32_MEMBER(model2_state::model2_irq_r) WRITE32_MEMBER(model2_state::model2_irq_w) { - i960_noburst(&space.device()); + m_maincpu->i960_noburst(); if (offset) { diff --git a/src/mame/includes/model2.h b/src/mame/includes/model2.h index 1c4d25d3445..8a5437753f8 100644 --- a/src/mame/includes/model2.h +++ b/src/mame/includes/model2.h @@ -41,7 +41,7 @@ public: optional_shared_ptr m_soundram; optional_shared_ptr m_tgp_program; - required_device m_maincpu; + required_device m_maincpu; optional_device m_dsbz80; // Z80-based MPEG Digital Sound Board required_device m_audiocpu; optional_device m_multipcm_1;