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removed old kludge
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@ -217,16 +217,8 @@ void sn76496_base_device::write(UINT8 data)
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m_sound->update();
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// set number of cycles until READY is active; this is always one
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// 'sample', i.e. it equals the clock divider exactly; until the
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// clock divider is fully supported, we delay until one sample has
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// played. The fact that this below is '2' and not '1' is because
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// of a ?race condition? in the mess crvision driver, where after
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// any sample is played at all, no matter what, the cycles_to_ready
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// ends up never being not ready, unless this value is greater than
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// 1. Once the full clock divider stuff is written, this should no
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// longer be an issue.
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m_cycles_to_ready = 2;
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// 'sample', i.e. it equals the clock divider exactly
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m_cycles_to_ready = 1;
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if (data & 0x80)
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{
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