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Implemented save support to HC11 core [Angelo Salese]

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This commit is contained in:
Angelo Salese 2011-09-11 17:28:41 +00:00
parent 76b994c1bd
commit 1b386426cc
2 changed files with 36 additions and 4 deletions
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32
src/emu/cpu/mc68hc11/mc68hc11.c
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@ -5,6 +5,7 @@
TODO: TODO:
- Interrupts handling is really bare-bones, just to make Hit Poker happy; - Interrupts handling is really bare-bones, just to make Hit Poker happy;
- Timers are really sketchy as per now, only TOC1 is emulated so far;
- Complete opcodes hook-up; - Complete opcodes hook-up;
- Emulate the MC68HC12 (same as HC11 with a bunch of new opcodes); - Emulate the MC68HC12 (same as HC11 with a bunch of new opcodes);
@ -449,6 +450,34 @@ static CPU_INIT( hc11 )
cpustate->program = device->space(AS_PROGRAM); cpustate->program = device->space(AS_PROGRAM);
cpustate->direct = &cpustate->program->direct(); cpustate->direct = &cpustate->program->direct();
cpustate->io = device->space(AS_IO); cpustate->io = device->space(AS_IO);
device->save_item(NAME(cpustate->pc));
device->save_item(NAME(cpustate->ix));
device->save_item(NAME(cpustate->iy));
device->save_item(NAME(cpustate->sp));
device->save_item(NAME(cpustate->ppc));
device->save_item(NAME(cpustate->ccr));
device->save_item(NAME(cpustate->d.d8.a));
device->save_item(NAME(cpustate->d.d8.b));
device->save_item(NAME(cpustate->adctl));
device->save_item(NAME(cpustate->ad_channel));
device->save_item(NAME(cpustate->ram_position));
device->save_item(NAME(cpustate->reg_position));
device->save_item(NAME(cpustate->irq_state));
device->save_item(NAME(cpustate->icount));
device->save_item(NAME(cpustate->has_extended_io));
device->save_item(NAME(cpustate->internal_ram_size));
device->save_item(NAME(cpustate->init_value));
device->save_pointer(NAME(cpustate->internal_ram),cpustate->internal_ram_size);
device->save_item(NAME(cpustate->wait_state));
device->save_item(NAME(cpustate->stop_state));
device->save_item(NAME(cpustate->tflg1));
device->save_item(NAME(cpustate->tmsk1));
device->save_item(NAME(cpustate->toc1));
device->save_item(NAME(cpustate->tcnt));
// device->save_item(NAME(cpustate->por));
device->save_item(NAME(cpustate->pr));
device->save_item(NAME(cpustate->frc_base));
} }
static CPU_RESET( hc11 ) static CPU_RESET( hc11 )
@ -631,7 +660,7 @@ CPU_GET_INFO( mc68hc11 )
case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
case CPUINFO_INT_MAX_CYCLES: info->i = 41; break; case CPUINFO_INT_MAX_CYCLES: info->i = 41; break;
case DEVINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break; case DEVINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 8; break;
case DEVINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break; case DEVINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break;
case DEVINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; case DEVINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
case DEVINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; case DEVINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
@ -642,6 +671,7 @@ CPU_GET_INFO( mc68hc11 )
case DEVINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; case DEVINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
case CPUINFO_INT_INPUT_STATE + MC68HC11_IRQ_LINE: info->i = cpustate->irq_state[MC68HC11_IRQ_LINE]; break; case CPUINFO_INT_INPUT_STATE + MC68HC11_IRQ_LINE: info->i = cpustate->irq_state[MC68HC11_IRQ_LINE]; break;
case CPUINFO_INT_INPUT_STATE + MC68HC11_TOC1_LINE: info->i = cpustate->irq_state[MC68HC11_TOC1_LINE]; break;
case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break; case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break;

8
src/mame/drivers/30test.c
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@ -230,7 +230,10 @@ INPUT_PORTS_END
static MACHINE_START( 30test ) static MACHINE_START( 30test )
{ {
namco_30test_state *state = machine.driver_data<namco_30test_state>();
state->save_item(NAME(state->m_mux_data));
state->save_item(NAME(state->m_oki_bank));
} }
static MACHINE_RESET( 30test ) static MACHINE_RESET( 30test )
@ -253,7 +256,6 @@ static MACHINE_CONFIG_START( 30test, namco_30test_state )
MCFG_CPU_PROGRAM_MAP(namco_30test_map) MCFG_CPU_PROGRAM_MAP(namco_30test_map)
MCFG_CPU_IO_MAP(namco_30test_io) MCFG_CPU_IO_MAP(namco_30test_io)
MCFG_CPU_CONFIG(namco_30test_config) MCFG_CPU_CONFIG(namco_30test_config)
// MCFG_CPU_PERIODIC_INT(irq0_line_hold,4*60) // unknown timing
MCFG_MACHINE_START(30test) MCFG_MACHINE_START(30test)
MCFG_MACHINE_RESET(30test) MCFG_MACHINE_RESET(30test)
@ -269,7 +271,7 @@ static MACHINE_CONFIG_START( 30test, namco_30test_state )
MCFG_SCREEN_UPDATE(30test) MCFG_SCREEN_UPDATE(30test)
// MCFG_PALETTE_INIT(30test) // MCFG_PALETTE_INIT(30test)
MCFG_PALETTE_LENGTH(8) MCFG_PALETTE_LENGTH(2)
MCFG_VIDEO_START(30test) MCFG_VIDEO_START(30test)
@ -294,4 +296,4 @@ ROM_START( 30test )
ROM_LOAD( "tt1-voi0.7p", 0x0000, 0x80000, CRC(b4fc5921) SHA1(92a88d5adb50dae48715847f12e88a35e37ef78c) ) ROM_LOAD( "tt1-voi0.7p", 0x0000, 0x80000, CRC(b4fc5921) SHA1(92a88d5adb50dae48715847f12e88a35e37ef78c) )
ROM_END ROM_END
GAMEL( 1997, 30test, 0, 30test, 30test, 0, ROT0, "Namco", "30 Test (Remake)", 0, layout_30test ) GAMEL( 1997, 30test, 0, 30test, 30test, 0, ROT0, "Namco", "30 Test (Remake)", GAME_SUPPORTS_SAVE, layout_30test )