From 1b75c5e87fed92a59088186a4582b598a4e1a9b8 Mon Sep 17 00:00:00 2001 From: Lord-Nightmare Date: Sun, 3 Sep 2017 14:21:57 -0400 Subject: [PATCH] upd7725: dpl bits of the instruction field are ignored if dp is the destination register of the current opcode. similarly, rpdcr bit is ignored if rp is the destination register of the current opcode. [Jonas Quinn] --- src/devices/cpu/upd7725/upd7725.cpp | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/src/devices/cpu/upd7725/upd7725.cpp b/src/devices/cpu/upd7725/upd7725.cpp index f010acc8b0f..7ef876613db 100644 --- a/src/devices/cpu/upd7725/upd7725.cpp +++ b/src/devices/cpu/upd7725/upd7725.cpp @@ -508,15 +508,17 @@ void necdsp_device::exec_op(uint32_t opcode) { exec_ld((regs.idb << 6) + dst); - switch(dpl) { - case 1: regs.dp = (regs.dp & 0xf0) + ((regs.dp + 1) & 0x0f); break; //DPINC - case 2: regs.dp = (regs.dp & 0xf0) + ((regs.dp - 1) & 0x0f); break; //DPDEC - case 3: regs.dp = (regs.dp & 0xf0); break; //DPCLR + if (dst != 4) { + switch(dpl) { + case 1: regs.dp = (regs.dp & 0xf0) + ((regs.dp + 1) & 0x0f); break; //DPINC + case 2: regs.dp = (regs.dp & 0xf0) + ((regs.dp - 1) & 0x0f); break; //DPDEC + case 3: regs.dp = (regs.dp & 0xf0); break; //DPCLR + } + + regs.dp ^= dphm << 4; } - regs.dp ^= dphm << 4; - - if(rpdcr) regs.rp--; + if(rpdcr && (dst != 5)) regs.rp--; } void necdsp_device::exec_rt(uint32_t opcode) {