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Oops.
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Aaron Giles
parent
e6e7a3804d
commit
1c386d0958
@ -18,9 +18,9 @@
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* - This entire notice must remain in the source code.
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*
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* Changes in 3.8 [Miodrag Milanovic]
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* - Added z80->MEMPTR register (according to informations provided
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* - Added MEMPTR register (according to informations provided
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* by Vladimir Kladov
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* - BIT n,(z80->HL) now return valid values due to use of z80->MEMPTR
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* - BIT n,(HL) now return valid values due to use of MEMPTR
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* - Fixed BIT 6,(XY+o) undocumented instructions
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* Changes in 3.7 [Aaron Giles]
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* - Changed NMI handling. NMIs are now latched in set_irq_state
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@ -52,14 +52,14 @@
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* Changes in 3.1
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* - removed the REPEAT_AT_ONCE execution of LDIR/CPIR etc. opcodes
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* for readabilities sake and because the implementation was buggy
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* (and z80->i was not able to find the difference)
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* (and i was not able to find the difference)
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* Changes in 3.0
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* - 'finished' switch to dynamically overrideable cycle count tables
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* Changes in 2.9:
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* - added methods to access and override the cycle count tables
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* - fixed handling and timing of multiple DD/FD prefixed opcodes
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* Changes in 2.8:
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* - OUTI/OUTD/OTIR/OTDR also pre-decrement the z80->B register now.
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* - OUTI/OUTD/OTIR/OTDR also pre-decrement the B register now.
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* This was wrong because of a bug fix on the wrong side
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* (astrocade sound driver).
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* Changes in 2.7:
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@ -71,25 +71,25 @@
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* Thanks to Sean Young for finding this nasty bug.
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* Changes in 2.5:
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* - Burning cycles always adjusts the ICount by a multiple of 4.
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* - In REPEAT_AT_ONCE cases the z80->r register wasn't incremented twice
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* - In REPEAT_AT_ONCE cases the r register wasn't incremented twice
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* per repetition as it should have been. Those repeated opcodes
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* could also underflow the ICount.
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* - Simplified TIME_LOOP_HACKS for z80->BC and added two more for z80->DE + z80->HL
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* timing loops. z80->i think those hacks weren't endian safe before too.
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* - Simplified TIME_LOOP_HACKS for BC and added two more for DE + HL
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* timing loops. i think those hacks weren't endian safe before too.
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* Changes in 2.4:
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* - z80_reset zaps the entire context, sets z80->IX and z80->IY to 0xffff(!) and
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* - z80_reset zaps the entire context, sets IX and IY to 0xffff(!) and
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* sets the Z flag. With these changes the Tehkan World Cup driver
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* _seems_ to work again.
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* Changes in 2.3:
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* - External termination of the execution loop calls z80_burn() and
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* z80_vm_burn() to burn an amount of cycles (z80->r adjustment)
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* z80_vm_burn() to burn an amount of cycles (r adjustment)
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* - Shortcuts which burn CPU cycles (BUSY_LOOP_HACKS and TIME_LOOP_HACKS)
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* now also adjust the z80->r register depending on the skipped opcodes.
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* now also adjust the r register depending on the skipped opcodes.
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* Changes in 2.2:
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* - Fixed bugs in CPL, SCF and CCF instructions flag handling.
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* - Changed variable z80->ea and ARG16() function to UINT32; this
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* - Changed variable ea and ARG16() function to UINT32; this
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* produces slightly more efficient code.
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* - The DD/FD XY CB opcodes where XY is 40-7F and Y is not 6/z80->E
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* - The DD/FD XY CB opcodes where XY is 40-7F and Y is not 6/E
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* are changed to calls to the X6/XE opcodes to reduce object size.
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* They're hardly ever used so this should not yield a speed penalty.
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* New in 2.0:
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@ -115,7 +115,7 @@
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/****************************************************************************/
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/* The Z80 registers. halt is set to 1 when the CPU is halted, the refresh */
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/* register is calculated as follows: refresh=(z80->r&127)|(z80->r2&128) */
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/* register is calculated as follows: refresh=(r&127)|(r2&128) */
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/****************************************************************************/
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typedef struct _z80_state z80_state;
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struct _z80_state
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@ -559,12 +559,12 @@ INLINE void BURNODD(z80_state *z80, int cycles, int opcodes, int cyclesum)
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} while (0)
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/***************************************************************
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* Input a byte from given z80->i/O port
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* Input a byte from given I/O port
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***************************************************************/
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#define IN(Z,port) memory_read_byte_8le((Z)->io, port)
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/***************************************************************
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* Output a byte to given z80->i/O port
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* Output a byte to given I/O port
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***************************************************************/
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#define OUT(Z,port,value) memory_write_byte_8le((Z)->io, port, value)
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@ -598,7 +598,7 @@ INLINE void WM16(z80_state *z80, UINT32 addr, PAIR *r)
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/***************************************************************
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* ROP() is identical to RM() except it is used for
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* reading opcodes. In case of system with memory mapped z80->i/O,
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* reading opcodes. In case of system with memory mapped I/O,
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* this function can be used to greatly speed up emulation
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***************************************************************/
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INLINE UINT8 ROP(z80_state *z80)
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@ -629,8 +629,8 @@ INLINE UINT32 ARG16(z80_state *z80)
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}
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/***************************************************************
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* Calculate the effective address z80->ea of an opcode using
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* z80->IX+offset resp. z80->IY+offset addressing.
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* Calculate the effective address EA of an opcode using
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* IX+offset resp. IY+offset addressing.
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***************************************************************/
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#define EAX(Z) do { (Z)->ea = (UINT32)(UINT16)((Z)->IX + (INT8)ARG(Z)); (Z)->MEMPTR = (Z)->ea; } while (0)
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#define EAY(Z) do { (Z)->ea = (UINT32)(UINT16)((Z)->IY + (INT8)ARG(Z)); (Z)->MEMPTR = (Z)->ea; } while (0)
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@ -1729,7 +1729,7 @@ OP(cb,ff) { z80->A = SET(7, z80->A); } /* SET 7,A */
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/**********************************************************
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* opcodes with DD/FD CB prefix
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* rotate, shift and bit operations with (z80->IX+o)
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* rotate, shift and bit operations with (IX+o)
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**********************************************************/
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OP(xycb,00) { z80->B = RLC(z80, RM(z80, z80->ea)); WM(z80, z80->ea,z80->B); } /* RLC B=(XY+o) */
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OP(xycb,01) { z80->C = RLC(z80, RM(z80, z80->ea)); WM(z80, z80->ea,z80->C); } /* RLC C=(XY+o) */
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@ -2025,7 +2025,7 @@ OP(illegal,1) {
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}
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/**********************************************************
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* z80->IX register related opcodes (DD prefix)
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* IX register related opcodes (DD prefix)
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**********************************************************/
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OP(dd,00) { illegal_1(z80); op_00(z80); } /* DB DD */
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OP(dd,01) { illegal_1(z80); op_01(z80); } /* DB DD */
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@ -2316,7 +2316,7 @@ OP(dd,fe) { illegal_1(z80); op_fe(z80); } /* DB DD */
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OP(dd,ff) { illegal_1(z80); op_ff(z80); } /* DB DD */
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/**********************************************************
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* z80->IY register related opcodes (FD prefix)
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* IY register related opcodes (FD prefix)
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**********************************************************/
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OP(fd,00) { illegal_1(z80); op_00(z80); } /* DB FD */
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OP(fd,01) { illegal_1(z80); op_01(z80); } /* DB FD */
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