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MC6800 LSR/ROR/ASR instructions set overflow flag to N XOR C (MT #6624)

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This commit is contained in:
AJR 2017-07-14 14:13:33 -04:00
parent ba64f47578
commit 1dc8a90131
2 changed files with 29 additions and 15 deletions
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42
src/devices/cpu/m6800/6800ops.hxx
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@ -59,8 +59,10 @@ OP_HANDLER( nop )
OP_HANDLER( lsrd )
{
uint16_t t;
CLR_NZC; t = D; CC|=(t&0x0001);
t>>=1; SET_Z16(t); D=t;
CLR_NZVC; t = D; CC|=(t&0x0001);
t>>=1; SET_Z16(t);
if (NXORC) SEV;
D=t;
}
/* $05 ASLD inherent ?**** */
@ -497,8 +499,9 @@ OP_HANDLER( coma )
/* $44 LSRA inherent -0*-* */
OP_HANDLER( lsra )
{
CLR_NZC; CC|=(A&0x01);
CLR_NZVC; CC|=(A&0x01);
A>>=1; SET_Z8(A);
if (NXORC) SEV;
}
/* $45 ILLEGAL */
@ -508,17 +511,19 @@ OP_HANDLER( rora )
{
uint8_t r;
r=(CC&0x01)<<7;
CLR_NZC; CC|=(A&0x01);
CLR_NZVC; CC|=(A&0x01);
r |= A>>1; SET_NZ8(r);
if (NXORC) SEV;
A=r;
}
/* $47 ASRA inherent ?**-* */
OP_HANDLER( asra )
{
CLR_NZC; CC|=(A&0x01);
CLR_NZVC; CC|=(A&0x01);
A>>=1; A|=((A&0x40)<<1);
SET_NZ8(A);
if (NXORC) SEV;
}
/* $48 ASLA inherent ?**** */
@ -593,8 +598,9 @@ OP_HANDLER( comb )
/* $54 LSRB inherent -0*-* */
OP_HANDLER( lsrb )
{
CLR_NZC; CC|=(B&0x01);
CLR_NZVC; CC|=(B&0x01);
B>>=1; SET_Z8(B);
if (NXORC) SEV;
}
/* $55 ILLEGAL */
@ -604,17 +610,19 @@ OP_HANDLER( rorb )
{
uint8_t r;
r=(CC&0x01)<<7;
CLR_NZC; CC|=(B&0x01);
CLR_NZVC; CC|=(B&0x01);
r |= B>>1; SET_NZ8(r);
if (NXORC) SEV;
B=r;
}
/* $57 ASRB inherent ?**-* */
OP_HANDLER( asrb )
{
CLR_NZC; CC|=(B&0x01);
CLR_NZVC; CC|=(B&0x01);
B>>=1; B|=((B&0x40)<<1);
SET_NZ8(B);
if (NXORC) SEV;
}
/* $58 ASLB inherent ?**** */
@ -710,8 +718,9 @@ OP_HANDLER( com_ix )
OP_HANDLER( lsr_ix )
{
uint8_t t;
IDXBYTE(t); CLR_NZC; CC|=(t&0x01);
IDXBYTE(t); CLR_NZVC; CC|=(t&0x01);
t>>=1; SET_Z8(t);
if (NXORC) SEV;
WM(EAD,t);
}
@ -731,8 +740,9 @@ OP_HANDLER( ror_ix )
{
uint8_t t,r;
IDXBYTE(t); r=(CC&0x01)<<7;
CLR_NZC; CC|=(t&0x01);
CLR_NZVC; CC|=(t&0x01);
r |= t>>1; SET_NZ8(r);
if (NXORC) SEV;
WM(EAD,r);
}
@ -740,9 +750,10 @@ OP_HANDLER( ror_ix )
OP_HANDLER( asr_ix )
{
uint8_t t;
IDXBYTE(t); CLR_NZC; CC|=(t&0x01);
IDXBYTE(t); CLR_NZVC; CC|=(t&0x01);
t>>=1; t|=((t&0x40)<<1);
SET_NZ8(t);
if (NXORC) SEV;
WM(EAD,t);
}
@ -857,10 +868,11 @@ OP_HANDLER( lsr_ex )
{
uint8_t t;
EXTBYTE(t);
CLR_NZC;
CLR_NZVC;
CC|=(t&0x01);
t>>=1;
SET_Z8(t);
if (NXORC) SEV;
WM(EAD,t);
}
@ -880,8 +892,9 @@ OP_HANDLER( ror_ex )
{
uint8_t t,r;
EXTBYTE(t); r=(CC&0x01)<<7;
CLR_NZC; CC|=(t&0x01);
CLR_NZVC; CC|=(t&0x01);
r |= t>>1; SET_NZ8(r);
if (NXORC) SEV;
WM(EAD,r);
}
@ -889,9 +902,10 @@ OP_HANDLER( ror_ex )
OP_HANDLER( asr_ex )
{
uint8_t t;
EXTBYTE(t); CLR_NZC; CC|=(t&0x01);
EXTBYTE(t); CLR_NZVC; CC|=(t&0x01);
t>>=1; t|=((t&0x40)<<1);
SET_NZ8(t);
if (NXORC) SEV;
WM(EAD,t);
}

2
src/devices/cpu/m6800/m6800.cpp
View File

@ -169,7 +169,6 @@ TODO:
#define CLR_HNZC CC&=0xd2
#define CLR_NZVC CC&=0xf0
#define CLR_Z CC&=0xfb
#define CLR_NZC CC&=0xf2
#define CLR_ZC CC&=0xfa
#define CLR_C CC&=0xfe
@ -274,6 +273,7 @@ const uint8_t m6800_cpu_device::flags8d[256]= /* decrement */
/* Macros for branch instructions */
#define BRANCH(f) {IMMBYTE(t);if(f){PC+=SIGNED(t);}}
#define NXORV ((CC&0x08)^((CC&0x02)<<2))
#define NXORC ((CC&0x08)^((CC&0x01)<<3))
/* Note: don't use 0 cycles here for invalid opcodes so that we don't */
/* hang in an infinite loop if we hit one */