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m6502/m4510.cpp: CPU I/O port support (backport from M6510 core)
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angelosa
parent
1853ece4b7
commit
1e3ee8b40d
@ -20,7 +20,10 @@ DEFINE_DEVICE_TYPE(M4510, m4510_device, "m4510", "CSG 4510")
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m4510_device::m4510_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
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m65ce02_device(mconfig, M4510, tag, owner, clock),
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map_enable(0),
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nomap(false)
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nomap(false),
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read_port(*this, 0),
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write_port(*this),
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dir(0), port(0), drive(0)
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{
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program_config.m_addr_width = 20;
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program_config.m_logaddr_width = 16;
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@ -28,6 +31,14 @@ m4510_device::m4510_device(const machine_config &mconfig, const char *tag, devic
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sprogram_config.m_addr_width = 20;
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sprogram_config.m_logaddr_width = 16;
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sprogram_config.m_page_shift = 13;
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pullup = 0x00;
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floating = 0x00;
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}
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void m4510_device::set_pulls(uint8_t _pullup, uint8_t _floating)
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{
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pullup = _pullup;
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floating = _floating;
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}
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std::unique_ptr<util::disasm_interface> m4510_device::create_disassembler()
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@ -35,11 +46,21 @@ std::unique_ptr<util::disasm_interface> m4510_device::create_disassembler()
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return std::make_unique<m4510_disassembler>();
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}
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void m4510_device::init_port()
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{
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save_item(NAME(pullup));
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save_item(NAME(floating));
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save_item(NAME(dir));
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save_item(NAME(port));
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save_item(NAME(drive));
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}
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void m4510_device::device_start()
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{
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mintf = std::make_unique<mi_4510>(this);
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m65ce02_device::init();
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init_port();
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save_item(NAME(map_offset));
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save_item(NAME(map_enable));
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@ -51,10 +72,44 @@ void m4510_device::device_reset()
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map_enable = 0;
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nomap = true;
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// Wild guess, this setting makes the cpu start executing some code in the c65 driver
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//map_offset[1] = 0x2e000;
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//map_enable = 0x80;
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m65ce02_device::device_reset();
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dir = 0x00;
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port = 0x00;
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drive = 0x00;
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update_port();
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}
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void m4510_device::update_port()
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{
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drive = (port & dir) | (drive & ~dir);
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write_port((port & dir) | (pullup & ~dir));
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}
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uint8_t m4510_device::get_port()
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{
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return (port & dir) | (pullup & ~dir);
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}
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uint8_t m4510_device::dir_r()
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{
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return dir;
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}
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uint8_t m4510_device::port_r()
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{
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return ((read_port() | (floating & drive)) & ~dir) | (port & dir);
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}
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void m4510_device::dir_w(uint8_t data)
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{
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dir = data;
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update_port();
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}
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void m4510_device::port_w(uint8_t data)
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{
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port = data;
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update_port();
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}
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bool m4510_device::memory_translate(int spacenum, int intention, offs_t &address, address_space *&target_space)
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@ -75,22 +130,41 @@ m4510_device::mi_4510::mi_4510(m4510_device *_base)
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uint8_t m4510_device::mi_4510::read(uint16_t adr)
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{
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return program.read_byte(base->map(adr));
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uint8_t res = program.read_byte(base->map(adr));
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if(adr == 0x0000)
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res = base->dir_r();
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else if(adr == 0x0001)
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res = base->port_r();
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return res;
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}
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uint8_t m4510_device::mi_4510::read_sync(uint16_t adr)
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{
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return csprogram.read_byte(base->map(adr));
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uint8_t res = csprogram.read_byte(base->map(adr));
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if(adr == 0x0000)
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res = base->dir_r();
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else if(adr == 0x0001)
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res = base->port_r();
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return res;
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}
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uint8_t m4510_device::mi_4510::read_arg(uint16_t adr)
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{
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return cprogram.read_byte(base->map(adr));
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uint8_t res = cprogram.read_byte(base->map(adr));
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if(adr == 0x0000)
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res = base->dir_r();
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else if(adr == 0x0001)
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res = base->port_r();
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return res;
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}
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void m4510_device::mi_4510::write(uint16_t adr, uint8_t val)
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{
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program.write_byte(base->map(adr), val);
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if(adr == 0x0000)
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base->dir_w(val);
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else if(adr == 0x0001)
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base->port_w(val);
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}
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#include "cpu/m6502/m4510.hxx"
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@ -26,6 +26,12 @@ public:
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bool get_nomap() const { return nomap; }
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uint8_t get_port();
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void set_pulls(uint8_t pullup, uint8_t pulldown);
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auto read_callback() { return read_port.bind(); }
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auto write_callback() { return write_port.bind(); }
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protected:
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uint32_t map_offset[2];
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uint8_t map_enable;
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@ -43,6 +49,11 @@ protected:
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virtual void write(uint16_t adr, uint8_t val) override;
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};
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devcb_read8 read_port;
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devcb_write8 write_port;
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uint8_t pullup, floating, dir, port, drive;
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virtual void device_start() override;
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virtual void device_reset() override;
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virtual bool memory_translate(int spacenum, int intention, offs_t &address, address_space *&target_space) override;
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@ -56,6 +67,14 @@ protected:
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return adr;
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}
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uint8_t dir_r();
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void dir_w(uint8_t data);
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uint8_t port_r();
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void port_w(uint8_t data);
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void init_port();
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void update_port();
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#define O(o) void o ## _full(); void o ## _partial()
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// 4510 opcodes
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@ -300,6 +300,9 @@ public:
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//, m_roma_view(*this, "roma_view")
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, m_romc_view(*this, "romc_view")
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//, m_rome_view(*this, "rome_view")
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//, m_loram_view(*this, "loram_view")
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//, m_hiram_view(*this, "hiram_view")
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, m_charen_view(*this, "charen_view")
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, m_screen(*this, "screen")
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, m_palette(*this, "palette")
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, m_workram(*this, "work_ram", 0x20000, ENDIANNESS_LITTLE)
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@ -334,6 +337,10 @@ private:
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//memory_view m_roma_view;
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memory_view m_romc_view;
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//memory_view m_rome_view;
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//memory_view m_loram_view;
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//memory_view m_hiram_view;
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memory_view m_charen_view;
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required_device<screen_device> m_screen;
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required_device<palette_device> m_palette;
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memory_share_creator<uint8_t> m_workram;
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@ -359,6 +366,8 @@ private:
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uint8_t cia0_portb_r();
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void cia0_portb_w(uint8_t data);
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void cia1_porta_w(uint8_t data);
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uint8_t cpu_r();
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void cpu_w(uint8_t data);
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uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
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void palette_init(palette_device &palette);
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@ -994,23 +1003,25 @@ void c65_state::c65_map(address_map &map)
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map(0x0c000, 0x0cfff).view(m_romc_view);
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m_romc_view[0](0x0c000, 0x0cfff).rw(FUNC(c65_state::ram_r<0x0c000>), FUNC(c65_state::ram_w<0x0c000>));
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m_romc_view[1](0x0c000, 0x0cfff).rom().region("ipl", 0x0c000);
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map(0x0d000, 0x0d07f).m(*this, FUNC(c65_state::vic4567_map));
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map(0x0d000, 0x0dfff).view(m_charen_view);
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m_charen_view[0](0x0d000, 0x0dfff).rom().region("ipl", 0x0d000);
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m_charen_view[1](0x0d000, 0x0d07f).m(*this, FUNC(c65_state::vic4567_map));
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// 0x0d080, 0x0d09f FDC
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map(0x0d080, 0x0d09f).lr8(NAME([] (offs_t offset) { return 0; }));
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m_charen_view[1](0x0d080, 0x0d09f).lr8(NAME([] (offs_t offset) { return 0; }));
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// 0x0d0a0, 0x0d0ff Ram Expansion Control (REC)
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map(0x0d100, 0x0d1ff).ram().w(FUNC(c65_state::palette_red_w)).share("redpal");
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map(0x0d200, 0x0d2ff).ram().w(FUNC(c65_state::palette_green_w)).share("greenpal");
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map(0x0d300, 0x0d3ff).ram().w(FUNC(c65_state::palette_blue_w)).share("bluepal");
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m_charen_view[1](0x0d100, 0x0d1ff).ram().w(FUNC(c65_state::palette_red_w)).share("redpal");
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m_charen_view[1](0x0d200, 0x0d2ff).ram().w(FUNC(c65_state::palette_green_w)).share("greenpal");
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m_charen_view[1](0x0d300, 0x0d3ff).ram().w(FUNC(c65_state::palette_blue_w)).share("bluepal");
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// 0x0d400, 0x0d4*f Right SID
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// keyboard hold left shift will read to $d484 (?)
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map(0x0d400, 0x0d41f).mirror(0x80).rw(m_sid[1], FUNC(mos6581_device::read), FUNC(mos6581_device::write));
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m_charen_view[1](0x0d400, 0x0d41f).mirror(0x80).rw(m_sid[1], FUNC(mos6581_device::read), FUNC(mos6581_device::write));
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// 0x0d440, 0x0d4*f Left SID
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map(0x0d440, 0x0d45f).mirror(0x80).rw(m_sid[0], FUNC(mos6581_device::read), FUNC(mos6581_device::write));
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map(0x0d600, 0x0d6ff).rw(FUNC(c65_state::uart_r), FUNC(c65_state::uart_w));
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m_charen_view[1](0x0d440, 0x0d45f).mirror(0x80).rw(m_sid[0], FUNC(mos6581_device::read), FUNC(mos6581_device::write));
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m_charen_view[1](0x0d600, 0x0d6ff).rw(FUNC(c65_state::uart_r), FUNC(c65_state::uart_w));
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// 0x0d700, 0x0d7** DMAgic
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map(0x0d700, 0x0d703).m(m_dma, FUNC(dmagic_f018_device::map));
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m_charen_view[1](0x0d700, 0x0d703).m(m_dma, FUNC(dmagic_f018_device::map));
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// 0x0d800, 0x0d8** Color matrix
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map(0x0d800, 0x0dfff).view(m_cram_view);
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m_charen_view[1](0x0d800, 0x0dfff).view(m_cram_view);
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// maps lower 1024 bytes regardless of the setting (essentially touches $dc00 as overlay)
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m_cram_view[0](0x0d800, 0x0dbff).lrw8(
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NAME([this] (offs_t offset) { return m_cram[offset]; }),
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@ -1211,11 +1222,27 @@ void c65_state::irq_check(uint8_t irq_cause)
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m_irqs->in_w<1>(m_irq_mask & m_irq_pending);
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}
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uint8_t c65_state::cpu_r()
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{
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return 0x07;
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}
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void c65_state::cpu_w(uint8_t data)
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{
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// m_loram = BIT(data, 0);
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// m_hiram = BIT(data, 1);
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m_charen_view.select(BIT(data, 2));
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}
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void c65_state::c65(machine_config &config)
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{
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/* basic machine hardware */
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M4510(config, m_maincpu, MAIN_C65_CLOCK);
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m_maincpu->set_addrmap(AS_PROGRAM, &c65_state::c65_map);
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m_maincpu->read_callback().set(FUNC(c65_state::cpu_r));
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m_maincpu->write_callback().set(FUNC(c65_state::cpu_w));
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m_maincpu->set_pulls(0x07, 0xc0);
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// TODO: multiply by x8 because with a more canonical x1 no transfer will complete in time.
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// is this thing a mixed burst/cycle steal really?
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@ -1266,9 +1293,8 @@ void c65_state::c65(machine_config &config)
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//m_sid->poty().set(FUNC(c64_state::sid_poty_r));
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m_sid[1]->add_route(ALL_OUTPUTS, "rspeaker", 0.50);
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// software list
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SOFTWARE_LIST(config, "flop_list").set_original("c65_flop");
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// SOFTWARE_LIST(config, "cart_list").set_compatible("c64_cart");
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}
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