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https://github.com/holub/mame
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video/mga2064w.cpp: initial experiments with drawing engine
This commit is contained in:
angelosa
parent
5d4b71f4b6
commit
1ea6071031
@ -1,11 +1,13 @@
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// license:BSD-3-Clause
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// copyright-holders:Olivier Galibert, Angelo Salese
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#include "emu.h"
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#include "mga2064w.h"
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#define LOG_WARN (1U << 1)
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#define LOG_ALIAS (1U << 2) // log mgabase1 index setups thru the back door
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#define LOG_DRAW (1U << 3) // log drawing engine accesses
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#define LOG_PIXELXFER (1U << 4) // log drawing pixel writes
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#define VERBOSE (LOG_GENERAL | LOG_WARN | LOG_DRAW)
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//#define LOG_OUTPUT_FUNC osd_printf_info
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@ -14,6 +16,7 @@
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#define LOGWARN(...) LOGMASKED(LOG_WARN, __VA_ARGS__)
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#define LOGALIAS(...) LOGMASKED(LOG_ALIAS, __VA_ARGS__)
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#define LOGDRAW(...) LOGMASKED(LOG_DRAW, __VA_ARGS__)
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#define LOGPIXELXFER(...) LOGMASKED(LOG_PIXELXFER, __VA_ARGS__)
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DEFINE_DEVICE_TYPE(MGA2064W, mga2064w_device, "mga2064w", "Matrox Millennium \"IS-STORM / MGA-2064W\"")
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@ -76,6 +79,7 @@ void mga2064w_device::device_reset()
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// INTA#
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intr_pin = 1;
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m_mgabase1_real_index = 0;
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m_dwgreg.state = DRAW_IDLE;
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}
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device_memory_interface::space_config_vector mga2064w_device::memory_space_config() const
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@ -95,7 +99,7 @@ void mga2064w_device::config_map(address_map &map)
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void mga2064w_device::mgabase1_map(address_map &map)
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{
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// map(0x0000, 0x1bff).rw(FUNC(mga2064w_device::dmawin_idump_r), FUNC(mga2064w_device::dmawin_iload_w));
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map(0x0000, 0x1bff).rw(FUNC(mga2064w_device::dmawin_idump_r), FUNC(mga2064w_device::dmawin_iload_w));
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map(0x1c00, 0x1dff).m(FUNC(mga2064w_device::dwgreg_map));
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// map(0x1e00, 0x1eff) HSTREG Host registers
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map(0x1e10, 0x1e13).r(FUNC(mga2064w_device::fifo_status_r));
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@ -224,9 +228,9 @@ void mga2064w_device::dwgreg_map(address_map &map)
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})
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);
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// AR0-6
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// TODO: documentation for each reg
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map(0x0060, 0x007b).lw32(
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NAME([this] (offs_t offset, u32 data, u32 mem_mask) {
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// FIXME: signed 18-bit
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LOGDRAW("dwgreg: AR[%01d] -> %08x & %08x\n", offset, data, mem_mask);
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COMBINE_DATA(&m_dwgreg.ar[offset]);
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})
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@ -253,7 +257,7 @@ void mga2064w_device::dwgreg_map(address_map &map)
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, m_dwgreg.fxleft, m_dwgreg.fxright
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);
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if (BIT(offset, 6))
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LOGDRAW("\tstart trigger\n");
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draw_trigger();
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})
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);
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// YDSTLEN
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@ -262,13 +266,13 @@ void mga2064w_device::dwgreg_map(address_map &map)
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// alternative way to access YDST (bits 31-16) and LEN (15-0) with a single dword
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m_dwgreg.len = data & 0xffff;
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// TODO: YDST bits 31-16 with signed conversion
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// ...
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m_dwgreg.ydst = util::sext(data >> 16, 15);
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LOGDRAW("dwgreg: YDSTLEN %08x & %08x (YDST %d|LEN %d)\n"
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, data, mem_mask
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, data >> 16, m_dwgreg.len
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);
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if (BIT(offset, 6))
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LOGDRAW("\tstart trigger\n");
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draw_trigger();
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})
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);
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// PITCH
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@ -393,7 +397,7 @@ void mga2064w_device::dwgreg_map(address_map &map)
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void mga2064w_device::dwgctl_w(offs_t offset, u32 data, u32 mem_mask)
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{
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COMBINE_DATA(&m_dwgreg.dwgctl);
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LOGDRAW("dwgreg: DWGCTRL -> %08x & %08x\n", data, mem_mask);
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LOGDRAW("dwgreg: DWGCTL -> %08x & %08x\n", data, mem_mask);
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const char *const opcode_mnemonics[16] = {
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"LINE_OPEN", "AUTOLINE_OPEN", "LINE_CLOSE", "AUTOLINE_CLOSE",
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"TRAP", "TEXTURE_TRAP", "<reserved>", "<reserved>",
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@ -483,6 +487,175 @@ u32 mga2064w_device::status_r()
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return m_svga->vsync_status() << 3;
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}
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void mga2064w_device::draw_trigger()
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{
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LOGDRAW("\tstart trigger\n");
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const u8 opcod = m_dwgreg.dwgctl & 0xf;
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const u8 bop = (m_dwgreg.dwgctl >> 16) & 0xf;
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const u8 bltmod = (m_dwgreg.dwgctl >> 25) & 0xf;
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if (bop != 0xc)
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return;
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const s32 ystart = m_dwgreg.ydst;
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const s32 yend = ystart + m_dwgreg.len;
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const s32 xstart = m_dwgreg.fxleft;
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const s32 xend = m_dwgreg.fxright;
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if (m_dwgreg.state != DRAW_IDLE)
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LOGWARN("\t(in-flight! %d)\n", m_dwgreg.state);
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m_dwgreg.state = DRAW_IDLE;
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switch(opcod)
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{
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// TRAP / RECT
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case 4:
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{
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if (BIT(m_dwgreg.dwgctl, 7))
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{
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LOGWARN("\tTRAP in linear mode (unemulated)\n");
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return;
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}
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for (int y = ystart; y < yend; y++)
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{
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for (int x = xstart; x < xend; x++)
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{
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m_svga->write_memory(x + (y * m_dwgreg.pitch), m_dwgreg.fcol & 0xff);
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}
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}
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break;
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}
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// BITBLT
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case 8:
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{
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if (BIT(m_dwgreg.dwgctl, 7))
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{
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// BMONOLEF only for now
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if (bltmod)
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return;
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const u32 source_base = m_dwgreg.ar[3] & 0xffffff;
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const s32 source_pitch = util::sext(m_dwgreg.ar[5], 17);
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int src_x = 0;
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int src_y = 0;
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for (int y = ystart; y < yend; y ++, src_y ++)
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{
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for (int x = xstart; x < xend; x+=8, src_x ++)
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{
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const u32 char_position = (src_x + src_y * source_pitch);
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const u8 char_data = m_svga->read_memory(source_base + char_position);
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for (int xi = 0; xi < 8; xi ++)
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{
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const u8 pen_dot = (char_data >> (7-xi)) & 1;
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u8 color_pen = (pen_dot ? m_dwgreg.fcol : m_dwgreg.bcol) & 0xff;
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m_svga->write_memory((x + xi) + m_dwgreg.pitch * y, color_pen);
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}
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}
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}
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}
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else
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{
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const u32 source_base = m_dwgreg.ar[3] & 0xffffff;
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const s32 source_pitch = util::sext(m_dwgreg.ar[5], 17);
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int src_x = 0;
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int src_y = 0;
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for (int y = ystart; y < yend; y++, src_y++)
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{
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for (int x = xstart; x < xend; x++, src_x++)
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{
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u8 color_pen = m_svga->read_memory(source_base + (source_pitch * src_y) + src_x);
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m_svga->write_memory(x + y * m_dwgreg.pitch, color_pen);
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}
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}
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}
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break;
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}
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// ILOAD
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case 9:
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m_dwgreg.state = DRAW_ILOAD;
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m_dwgreg.current_x = 0;
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m_dwgreg.current_y = 0;
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break;
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// IDUMP
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case 0xa:
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m_dwgreg.state = DRAW_IDUMP;
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m_dwgreg.current_x = 0;
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m_dwgreg.current_y = 0;
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break;
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}
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LOGDRAW("\n");
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}
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u32 mga2064w_device::dmawin_idump_r(offs_t offset, u32 mem_mask)
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{
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u32 res = 0;
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LOGPIXELXFER("dmawin_idump_r [%08x] & %08x %d %d (state %d)\n", offset * 4, mem_mask, m_dwgreg.current_x, m_dwgreg.current_y, m_dwgreg.state);
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switch(m_dwgreg.state)
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{
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case DRAW_IDUMP:
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{
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const u32 y_base = m_dwgreg.pitch * (m_dwgreg.current_y + m_dwgreg.ydst);
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const u32 x_base = m_dwgreg.current_x + m_dwgreg.fxleft;
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for (int xi = 0; xi < 4; xi ++)
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res |= m_svga->read_memory((y_base) + (x_base + xi)) << (xi * 8);
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m_dwgreg.current_x += 4;
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if (m_dwgreg.current_x > m_dwgreg.ar[0])
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{
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m_dwgreg.current_x = 0;
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m_dwgreg.current_y ++;
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if (m_dwgreg.current_y > m_dwgreg.len)
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m_dwgreg.state = DRAW_IDLE;
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}
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return res;
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}
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default:
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LOGWARN("Unemulated IDUMP read state [%08x] mem_mask %08x\n", offset * 4, mem_mask);
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res = 0xdeadbeef;
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break;
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}
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return res;
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}
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void mga2064w_device::dmawin_iload_w(offs_t offset, u32 data, u32 mem_mask)
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{
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// assume dword accesses unless something dull proves otherwise
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LOGPIXELXFER("dmawin_iload_w [%08x] %08x & %08x %d %d (state %d)\n", offset * 4, data, mem_mask, m_dwgreg.current_x, m_dwgreg.current_y, m_dwgreg.state);
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switch(m_dwgreg.state)
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{
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case DRAW_ILOAD:
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{
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const u32 y_base = m_dwgreg.pitch * (m_dwgreg.current_y + m_dwgreg.ydst);
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const u32 x_base = m_dwgreg.current_x + m_dwgreg.fxleft;
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for (int xi = 0; xi < 4; xi++)
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{
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u8 color_pen = (data >> (8 * xi)) & 0xff;
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m_svga->write_memory((y_base) + (x_base + xi), color_pen);
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}
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m_dwgreg.current_x += 4;
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if (m_dwgreg.current_x > m_dwgreg.ar[0])
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{
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m_dwgreg.current_x = 0;
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m_dwgreg.current_y ++;
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// Note: this is unnecessary, really changes with OPMODE
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if (m_dwgreg.current_y > m_dwgreg.len)
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m_dwgreg.state = DRAW_IDLE;
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}
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break;
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}
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default:
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LOGWARN("Unemulated ILOAD write state [%08x] %08x & %08x\n", offset * 4, data, mem_mask);
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break;
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}
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}
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// TODO: this should really be a subclass of VGA
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void mga2064w_device::legacy_memory_map(address_map &map)
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{
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@ -33,6 +33,9 @@ protected:
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void dwgreg_map(address_map &map);
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u32 dmawin_idump_r(offs_t offset, u32 mem_mask = ~0);
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void dmawin_iload_w(offs_t offset, u32 data, u32 mem_mask = ~0);
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required_device<matrox_vga_device> m_svga;
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required_memory_region m_vga_rom;
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private:
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@ -52,6 +55,12 @@ private:
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// DWGREG section
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void dwgctl_w(offs_t offset, u32 data, u32 mem_mask = ~0);
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void maccess_w(offs_t offset, u32 data, u32 mem_mask = ~0);
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enum drawing_state_t {
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DRAW_IDLE,
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DRAW_ILOAD,
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DRAW_IDUMP
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};
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struct {
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u32 src[4]{};
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u32 dr[16]{};
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@ -69,12 +78,16 @@ private:
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s16 fxleft = 0;
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s16 fxright = 0;
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s16 xdst = 0;
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int32_t ydst = 0;
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s32 ydst = 0;
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u32 ydstorg = 0;
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u32 bcol = 0;
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u32 fcol = 0;
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u8 sellin = 0;
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drawing_state_t state;
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s32 current_x, current_y;
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} m_dwgreg;
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void draw_trigger();
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};
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DECLARE_DEVICE_TYPE(MGA2064W, mga2064w_device);
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