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mcs51.cpp: Consolidate internal address maps; remove P0 from ROMless versions since it conflicts with external accesses on hardware (nw)

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AJR 2018-06-13 14:53:36 -04:00
parent a69902b460
commit 1f1c60cbe8
2 changed files with 13 additions and 24 deletions
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30
src/devices/cpu/mcs51/mcs51.cpp
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@ -242,25 +242,15 @@ DEFINE_DEVICE_TYPE(DS5002FP, ds5002fp_device, "ds5002fp", "Dallas DS5002FP")
ADDRESS MAPS ADDRESS MAPS
***************************************************************************/ ***************************************************************************/
void mcs51_cpu_device::program_12bit(address_map &map) void mcs51_cpu_device::program_internal(address_map &map)
{ {
map(0x00, 0x0fff).rom(); if (m_rom_size > 0)
map(0, m_rom_size - 1).rom().region(DEVICE_SELF, 0);
} }
void mcs51_cpu_device::program_13bit(address_map &map) void mcs51_cpu_device::data_internal(address_map &map)
{ {
map(0x00, 0x1fff).rom(); map(0x0000, m_ram_mask).ram().share("scratchpad");
}
void mcs51_cpu_device::data_7bit(address_map &map)
{
map(0x0000, 0x007f).ram().share("scratchpad");
map(0x0100, 0x01ff).ram().share("sfr_ram"); /* SFR */
}
void mcs51_cpu_device::data_8bit(address_map &map)
{
map(0x0000, 0x00ff).ram().share("scratchpad");
map(0x0100, 0x01ff).ram().share("sfr_ram"); /* SFR */ map(0x0100, 0x01ff).ram().share("sfr_ram"); /* SFR */
} }
@ -268,13 +258,12 @@ void mcs51_cpu_device::data_8bit(address_map &map)
mcs51_cpu_device::mcs51_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int program_width, int data_width, uint8_t features) mcs51_cpu_device::mcs51_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int program_width, int data_width, uint8_t features)
: cpu_device(mconfig, type, tag, owner, clock) : cpu_device(mconfig, type, tag, owner, clock)
, m_program_config("program", ENDIANNESS_LITTLE, 8, 16, 0, , m_program_config("program", ENDIANNESS_LITTLE, 8, 16, 0, address_map_constructor(FUNC(mcs51_cpu_device::program_internal), this))
(program_width == 12) ? address_map_constructor(FUNC(mcs51_cpu_device::program_12bit), this) : (program_width == 13) ? address_map_constructor(FUNC(mcs51_cpu_device::program_13bit), this) : address_map_constructor()) , m_data_config("data", ENDIANNESS_LITTLE, 8, 9, 0, address_map_constructor(FUNC(mcs51_cpu_device::data_internal), this))
, m_data_config("data", ENDIANNESS_LITTLE, 8, 9, 0,
(data_width == 7) ? address_map_constructor(FUNC(mcs51_cpu_device::data_7bit), this) : (data_width == 8) ? address_map_constructor(FUNC(mcs51_cpu_device::data_8bit), this) : address_map_constructor())
, m_io_config("io", ENDIANNESS_LITTLE, 8, (features & FEATURE_DS5002FP) ? 17 : 16, 0) , m_io_config("io", ENDIANNESS_LITTLE, 8, (features & FEATURE_DS5002FP) ? 17 : 16, 0)
, m_pc(0) , m_pc(0)
, m_features(features) , m_features(features)
, m_rom_size(program_width > 0 ? 1 << program_width : 0)
, m_ram_mask( (data_width == 8) ? 0xFF : 0x7F ) , m_ram_mask( (data_width == 8) ? 0xFF : 0x7F )
, m_num_interrupts(5) , m_num_interrupts(5)
, m_sfr_ram(*this, "sfr_ram") , m_sfr_ram(*this, "sfr_ram")
@ -2149,7 +2138,8 @@ void mcs51_cpu_device::device_start()
state_add( MCS51_DPL, "DPL", DPL).noshow(); state_add( MCS51_DPL, "DPL", DPL).noshow();
state_add( MCS51_IE, "IE", IE).formatstr("%02X"); state_add( MCS51_IE, "IE", IE).formatstr("%02X");
state_add( MCS51_IP, "IP", IP).formatstr("%02X"); state_add( MCS51_IP, "IP", IP).formatstr("%02X");
state_add<uint8_t>( MCS51_P0, "P0", [this](){ return P0; }, [this](uint8_t p){ SET_P0(p); }).formatstr("%02X"); if (m_rom_size > 0)
state_add<uint8_t>( MCS51_P0, "P0", [this](){ return P0; }, [this](uint8_t p){ SET_P0(p); }).formatstr("%02X");
state_add<uint8_t>( MCS51_P1, "P1", [this](){ return P1; }, [this](uint8_t p){ SET_P1(p); }).formatstr("%02X"); state_add<uint8_t>( MCS51_P1, "P1", [this](){ return P1; }, [this](uint8_t p){ SET_P1(p); }).formatstr("%02X");
state_add<uint8_t>( MCS51_P2, "P2", [this](){ return P2; }, [this](uint8_t p){ SET_P2(p); }).formatstr("%02X"); state_add<uint8_t>( MCS51_P2, "P2", [this](){ return P2; }, [this](uint8_t p){ SET_P2(p); }).formatstr("%02X");
state_add<uint8_t>( MCS51_P3, "P3", [this](){ return P3; }, [this](uint8_t p){ SET_P3(p); }).formatstr("%02X"); state_add<uint8_t>( MCS51_P3, "P3", [this](){ return P3; }, [this](uint8_t p){ SET_P3(p); }).formatstr("%02X");

7
src/devices/cpu/mcs51/mcs51.h
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@ -101,10 +101,8 @@ public:
template<class Object> devcb_base &set_serial_rx_cb(Object &&cb) { return m_serial_rx_cb.set_callback(std::forward<Object>(cb)); } template<class Object> devcb_base &set_serial_rx_cb(Object &&cb) { return m_serial_rx_cb.set_callback(std::forward<Object>(cb)); }
template<class Object> devcb_base &set_serial_tx_cb(Object &&cb) { return m_serial_tx_cb.set_callback(std::forward<Object>(cb)); } template<class Object> devcb_base &set_serial_tx_cb(Object &&cb) { return m_serial_tx_cb.set_callback(std::forward<Object>(cb)); }
void data_7bit(address_map &map); void program_internal(address_map &map);
void data_8bit(address_map &map); void data_internal(address_map &map);
void program_12bit(address_map &map);
void program_13bit(address_map &map);
protected: protected:
// construction/destruction // construction/destruction
mcs51_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int program_width, int data_width, uint8_t features = 0); mcs51_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int program_width, int data_width, uint8_t features = 0);
@ -143,6 +141,7 @@ protected:
uint8_t m_rwm; //Signals that the current instruction is a read/write/modify instruction uint8_t m_rwm; //Signals that the current instruction is a read/write/modify instruction
int m_inst_cycles; /* cycles for the current instruction */ int m_inst_cycles; /* cycles for the current instruction */
const uint32_t m_rom_size; /* size (in bytes) of internal program ROM/EPROM */
int m_ram_mask; /* second ram bank for indirect access available ? */ int m_ram_mask; /* second ram bank for indirect access available ? */
int m_num_interrupts; /* number of interrupts supported */ int m_num_interrupts; /* number of interrupts supported */
int m_recalc_parity; /* recalculate parity before next instruction */ int m_recalc_parity; /* recalculate parity before next instruction */