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https://github.com/holub/mame
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wtl3132: new device
This commit is contained in:
Patrick Mackinlay
parent
e2863920b5
commit
1f9fd834af
@ -4082,3 +4082,15 @@ if (MACHINES["EDLC"]~=null) then
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MAME_DIR .. "src/devices/machine/edlc.h",
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}
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end
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---------------------------------------------------
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--
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--@src/devices/machine/wtl3132.h,MACHINES["WTL3132"] = true
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---------------------------------------------------
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if (MACHINES["WTL3132"]~=null) then
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files {
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MAME_DIR .. "src/devices/machine/wtl3132.cpp",
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MAME_DIR .. "src/devices/machine/wtl3132.h",
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}
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end
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521
src/devices/machine/wtl3132.cpp
Normal file
521
src/devices/machine/wtl3132.cpp
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@ -0,0 +1,521 @@
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// license:BSD-3-Clause
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// copyright-holders:Patrick Mackinlay
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/*
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* An emulation of the Weitek 3132 floating point data path.
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*
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* Sources:
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* - http://www.bitsavers.org/components/weitek/dataSheets/WTL-3132_3332_XL-3132_32-Bit_Floating_Point_Data_Path_Oct88.pdf
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*
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* TODO:
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* - reciprocal via lookup table
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* - fully analyze reversed C bus case
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* - testing/logging undefined cases
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*/
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#include "emu.h"
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#include "wtl3132.h"
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#define LOG_GENERAL (1U << 0)
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#define LOG_REGS (1U << 1)
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#define LOG_IO (1U << 2)
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#define LOG_BYPASS (1U << 3)
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#define VERBOSE (LOG_GENERAL|LOG_REGS|LOG_IO|LOG_BYPASS)
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#include "logmacro.h"
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ALLOW_SAVE_TYPE(float32_t);
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// helper for extracting opcode fields
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#define OPF(c, x) ((c & M_##x) >> S_##x)
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DEFINE_DEVICE_TYPE(WTL3132, wtl3132_device, "wtl3132", "Weitek 3132")
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wtl3132_device::wtl3132_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
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: device_t(mconfig, WTL3132, tag, owner, clock)
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, m_fpcn_cb(*this)
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, m_fpex_cb(*this)
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, m_zero_cb(*this)
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{
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}
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void wtl3132_device::device_start()
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{
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m_fpcn_cb.resolve_safe();
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m_fpex_cb.resolve_safe();
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m_zero_cb.resolve_safe();
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save_item(NAME(m_fpcn_state));
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save_item(NAME(m_fpex_state));
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save_item(NAME(m_zero_state));
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save_item(NAME(m_c_port));
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save_item(NAME(m_x_port));
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save_item(NAME(m_x_in));
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save_item(NAME(m_x_out));
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save_item(NAME(m_slot));
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save_item(NAME(m_head));
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save_item(NAME(m_mode));
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save_item(NAME(m_f));
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save_item(NAME(m_t1));
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save_item(NAME(m_t2));
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save_item(NAME(m_t3));
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save_item(NAME(m_cr));
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save_item(NAME(m_sr));
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save_item(NAME(m_zr));
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save_item(NAME(m_c_bus_data));
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save_item(NAME(m_c_bus_addr));
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save_item(NAME(m_c_bus_cwen));
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save_item(NAME(m_ma_in));
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save_item(NAME(m_mb_in));
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save_item(NAME(m_m_out));
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save_item(NAME(m_aa_in));
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save_item(NAME(m_ab_in));
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save_item(NAME(m_a_out));
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}
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void wtl3132_device::device_reset()
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{
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m_abort = 1;
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m_neut = 1;
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m_stall = 1;
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m_fpcn_state = 1;
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m_fpex_state = 1;
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m_zero_state = 1;
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// initialize pipeline with fnop to minimize logging noise
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for (u64 &slot : m_slot)
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slot = (F_FSUB << S_F) | M_CWEN | M_ABIN | M_ADST;
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m_head = 0;
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m_mode = 0;
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}
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void wtl3132_device::clk_w(int state)
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{
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// ignore falling edges for now
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if (!state)
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return;
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// precompute pipeline slot indixes
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unsigned const index0 = (m_head + 4) & 3;
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unsigned const index1 = (m_head + 3) & 3;
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unsigned const index2 = (m_head + 2) & 3;
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unsigned const index3 = (m_head + 1) & 3;
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LOG("code 0x%09x slot %d %s\n", m_c_port, index0, disassemble(m_c_port));
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// store the next instruction in the pipeline
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m_slot[index0] = m_c_port;
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// STALL- and ABORT- prevent all processing of the next instruction
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if (!m_stall || !m_abort)
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{
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LOG("slot %d stage instruction %s\n", index0, !m_stall ? "stalled" : "aborted");
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m_slot[index0] |= M_CANCEL;
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}
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// retire pipeline stages in fifo order simplifying dependency forwarding
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if (!(m_slot[index3] & M_CANCEL))
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stage4(index3);
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if (!(m_slot[index2] & M_CANCEL))
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stage3(index2);
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if (!(m_slot[index1] & M_CANCEL))
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stage2(index1);
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if (!(m_slot[index0] & M_CANCEL))
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stage1(index0);
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// write to the register file after the first pipeline stage has completed
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// to ensure the effective 4 cycle delay for non-bypassed register access
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if (!m_c_bus_cwen && !(m_slot[index3] & M_CANCEL))
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{
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m_f[m_c_bus_addr] = m_c_bus_data;
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LOGMASKED(LOG_REGS, "slot %d stage 4 f%d = %f\n", index3, m_c_bus_addr, u2f(m_c_bus_data.v));
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}
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// NEUT- and ABORT- prevent writeback of the previous instruction, but
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// allow i/o to complete normally
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if (!m_neut || !m_abort)
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{
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LOG("slot %d stage instruction %s\n", index1, !m_neut ? "neutralized" : "aborted");
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m_slot[index1] |= M_CANCEL;
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}
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m_head = index3;
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}
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void wtl3132_device::stage1(unsigned const index)
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{
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u64 const code = m_slot[index];
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// A and B buses are loaded from registers by default
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float32_t a_bus = m_f[OPF(code, AADD)];
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float32_t b_bus = m_f[OPF(code, BADD)];
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// C-to-A bus internal bypass
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if (((m_mode & MODE_IBA) && !m_c_bus_cwen && OPF(code, AADD) == m_c_bus_addr))
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{
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a_bus = m_c_bus_data;
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LOGMASKED(LOG_BYPASS, "slot %d stage 1 C-to-A internal bypass %f\n", index, u2f(m_c_bus_data.v));
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}
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// C-to-B bus internal bypass
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if (((m_mode & MODE_IBB) && !m_c_bus_cwen && OPF(code, BADD) == m_c_bus_addr))
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{
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b_bus = m_c_bus_data;
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LOGMASKED(LOG_BYPASS, "slot %d stage 1 C-to-B internal bypass %f\n", index, u2f(m_c_bus_data.v));
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}
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// perform i/o
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switch (OPF(code, IOCT))
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{
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case 1: // floadrc
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m_f[OPF(code, DADD)] = m_x_port;
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// FIXME: floadrc uses c bus, preventing result writeback except for flut
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m_x_in = m_x_port;
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LOGMASKED(LOG_IO, "slot %d stage 1 floadrc f%d = %f\n", index, OPF(code, DADD), u2f(m_x_port.v));
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break;
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case 2: // fstore
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// C-to-X output bypass
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if ((m_mode & MODE_OBP) && !m_c_bus_cwen && OPF(code, DADD) == m_c_bus_addr)
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{
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m_x_out = m_c_bus_data;
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LOGMASKED(LOG_BYPASS, "slot %d stage 1 C-to-X output bypass %f\n", index, u2f(m_c_bus_data.v));
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}
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else
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m_x_out = m_f[OPF(code, DADD)];
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break;
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case 3: // fload
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m_f[OPF(code, DADD)] = m_x_port;
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LOGMASKED(LOG_IO, "slot %d stage 1 fload f%d = %f\n", index, OPF(code, DADD), u2f(m_x_port.v));
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// X-to-A bus input bypass
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if ((m_mode & MODE_IBP) && OPF(code, AADD) == OPF(code, DADD))
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{
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a_bus = m_x_port;
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LOGMASKED(LOG_BYPASS, "slot %d stage 1 X-to-A input bypass %f\n", index, u2f(m_x_port.v));
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}
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break;
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}
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// perform status and mode register operations
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switch (OPF(code, F))
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{
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case F_MISC:
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switch (OPF(code, BADD))
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{
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case MF_FCLSR:
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m_sr = false;
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break;
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case MF_FSTSR:
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m_x_port.v = m_sr;
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break;
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case MF_FMODE:
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{
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// check polarity inversion
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bool const polarity = bool(m_mode & MODE_FXH) ^ bool((OPF(code, CADD) << 5) & MODE_FXH);
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// update mode
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m_mode = (OPF(code, ABIN) << 10) | (OPF(code, CADD) << 5) | OPF(code, AADD);
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if (!(m_mode & MODE_FXO))
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m_sr = false;
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// force line update
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if (polarity)
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m_fpex_state = !m_sr;
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}
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break;
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}
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}
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// select and load multiplier inputs
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m_ma_in = a_bus;
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m_mb_in = OPF(code, MBIN) ? m_x_in : b_bus;
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// buffer accumulator inputs
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m_aa_in[0] = a_bus;
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m_ab_in[0] = b_bus;
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}
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void wtl3132_device::stage2(unsigned const index)
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{
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u64 const code = m_slot[index];
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// load AAin from multiplier output or buffered A bus
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m_aa_in[1] = (OPF(code, F) & 4) ? m_m_out : m_aa_in[0];
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// load ABin from source specified by ABIN opcode field
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switch (OPF(code, ABIN))
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{
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case 0: m_ab_in[1] = m_x_in; break;
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case 1: m_ab_in[1] = m_ab_in[0]; break;
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case 2: m_ab_in[1] = m_t2; break;
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case 3: m_ab_in[1] = m_t1; break;
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case 4: m_ab_in[1] = m_t3; break;
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case 6: m_ab_in[1] = i32_to_f32(2); break;
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case 7: m_ab_in[1] = i32_to_f32(0); break;
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}
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// execute multiply and optional negate
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switch (OPF(code, F))
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{
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case F_FMNA:
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case F_FMNS:
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// multiply and negate
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m_m_out = f32_mul(f32_mul(m_ma_in, m_mb_in), i32_to_f32(-1));
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LOG("slot %d stage 2 -(%f * %f) == %f\n", index, u2f(m_ma_in.v), u2f(m_mb_in.v), u2f(m_m_out.v));
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break;
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case F_FMAC:
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// multiply
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m_m_out = f32_mul(m_ma_in, m_mb_in);
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LOG("slot %d stage 2 %f * %f == %f\n", index, u2f(m_ma_in.v), u2f(m_mb_in.v), u2f(m_m_out.v));
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break;
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}
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// complete fstore
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if (OPF(code, IOCT) == 2)
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{
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m_x_port = m_x_out;
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LOGMASKED(LOG_IO, "slot %d stage 2 fstore %f\n", index, u2f(m_x_out.v));
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}
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}
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void wtl3132_device::stage3(unsigned const index)
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{
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u64 const code = m_slot[index];
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softfloat_exceptionFlags = 0;
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// execute accumulator operation
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switch (OPF(code, F))
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{
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case F_MISC:
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switch (OPF(code, BADD))
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{
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case MF_FABS:
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if (f32_lt(m_aa_in[1], i32_to_f32(0)))
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m_a_out = f32_mul(m_aa_in[1], i32_to_f32(-1));
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else
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m_a_out = m_aa_in[1];
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if (m_mode & MODE_RTN)
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m_cr = f32_eq(m_a_out, i32_to_f32(0));
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LOG("slot %d stage 3 fabs %f == %f\n", index, u2f(m_aa_in[1].v), u2f(m_a_out.v));
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break;
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case MF_FLOAT:
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if ((m_mode & MODE_RTN) && OPF(code, ENCN) == 1)
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m_cr = (m_aa_in[1].v & 0xff000000) && (~m_aa_in[1].v & 0xff000000);
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m_a_out = i32_to_f32(m_aa_in[1].v);
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LOG("slot %d stage 3 float 0x%08x == %f\n", index, m_aa_in[1].v, u2f(m_a_out.v));
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break;
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case MF_FIX:
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if ((m_mode & MODE_RTN) && OPF(code, ENCN) == 1)
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m_cr = f32_lt(m_aa_in[1], i32_to_f32(-4194304)) || f32_lt(i32_to_f32(4194304), m_aa_in[1]);
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m_a_out.v = (f32_to_i32(m_aa_in[1], (m_mode & MODE_RTN) ?
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softfloat_round_near_even : softfloat_round_min, false) << 8) >> 8;
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LOG("slot %d stage 3 fix %f == 0x%08x\n", index, u2f(m_aa_in[1].v), m_a_out.v);
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break;
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case MF_FLUT:
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// TODO: replace with lookup table
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m_a_out = f32_div(i32_to_f32(1), m_aa_in[1]);
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LOG("slot %d stage 3 flut %f == %f\n", index, u2f(m_aa_in[1].v), u2f(m_a_out.v));
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break;
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}
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break;
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case F_FSUBR:
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m_a_out = f32_sub(m_ab_in[1], m_aa_in[1]);
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LOG("slot %d stage 3 fsubr %f - %f == %f\n", index, u2f(m_ab_in[1].v), u2f(m_aa_in[1].v), u2f(m_a_out.v));
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break;
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case F_FSUB:
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m_a_out = f32_sub(m_aa_in[1], m_ab_in[1]);
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LOG("slot %d stage 3 fsub %f - %f == %f\n", index, u2f(m_aa_in[1].v), u2f(m_ab_in[1].v), u2f(m_a_out.v));
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break;
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case F_FADD:
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m_a_out = f32_add(m_aa_in[1], m_ab_in[1]);
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LOG("slot %d stage 3 fadd %f + %f == %f\n", index, u2f(m_aa_in[1].v), u2f(m_ab_in[1].v), u2f(m_a_out.v));
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break;
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case F_FMNA:
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m_a_out = f32_add(m_m_out, m_ab_in[1]);
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LOG("slot %d stage 3 fmna %f + %f == %f\n", index, u2f(m_m_out.v), u2f(m_ab_in[1].v), u2f(m_a_out.v));
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break;
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case F_FMNS:
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m_a_out = f32_sub(m_m_out, m_ab_in[1]);
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LOG("slot %d stage 3 fmns %f - %f == %f\n", index, u2f(m_m_out.v), u2f(m_ab_in[1].v), u2f(m_a_out.v));
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break;
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case F_FMAC:
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m_a_out = f32_add(m_m_out, m_ab_in[1]);
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LOG("slot %d stage 3 fmac %f + %f == %f\n", index, u2f(m_m_out.v), u2f(m_ab_in[1].v), u2f(m_a_out.v));
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break;
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}
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// update condition, zero and status registers
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if (OPF(code, F))
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{
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switch (OPF(code, ENCN))
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{
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case 1:
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m_cr = f32_le(m_a_out, i32_to_f32(0));
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m_zr = f32_eq(m_a_out, i32_to_f32(0));
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break;
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case 2:
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m_cr = f32_lt(m_a_out, i32_to_f32(0));
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m_zr = f32_eq(m_a_out, i32_to_f32(0));
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break;
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case 3:
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m_cr = f32_eq(m_a_out, i32_to_f32(0));
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m_zr = f32_eq(m_a_out, i32_to_f32(0));
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break;
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}
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if ((m_mode & MODE_FXH) || !m_sr)
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m_sr = softfloat_exceptionFlags & softfloat_flag_overflow;
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}
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}
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|
||||
void wtl3132_device::stage4(unsigned const index)
|
||||
{
|
||||
u64 const code = m_slot[index];
|
||||
|
||||
// update C bus
|
||||
m_c_bus_data = m_a_out;
|
||||
m_c_bus_addr = OPF(code, CADD);
|
||||
m_c_bus_cwen = OPF(code, CWEN);
|
||||
|
||||
// update temporary registers
|
||||
switch (OPF(code, ADST))
|
||||
{
|
||||
case 0: m_t3 = m_a_out; LOGMASKED(LOG_REGS, "slot %d stage 4 t3 = %f\n", index, u2f(m_t3.v)); break;
|
||||
case 1: m_t2 = m_a_out; LOGMASKED(LOG_REGS, "slot %d stage 4 t2 = %f\n", index, u2f(m_t2.v)); break;
|
||||
case 2: m_t1 = m_a_out; LOGMASKED(LOG_REGS, "slot %d stage 4 t1 = %f\n", index, u2f(m_t1.v)); break;
|
||||
}
|
||||
|
||||
// update output lines
|
||||
if (m_cr ^ m_fpcn_state)
|
||||
{
|
||||
m_fpcn_state = m_cr;
|
||||
m_fpcn_cb(m_fpcn_state);
|
||||
}
|
||||
|
||||
if (m_sr ^ m_fpex_state)
|
||||
{
|
||||
m_fpex_state = m_sr;
|
||||
m_fpex_cb(!(m_fpex_state ^ bool(m_mode & MODE_FXH)));
|
||||
}
|
||||
|
||||
if (m_zr ^ m_zero_state)
|
||||
{
|
||||
m_zero_state = m_zr;
|
||||
m_zero_cb(m_zero_state);
|
||||
}
|
||||
}
|
||||
|
||||
std::string wtl3132_device::disassemble(u64 const code)
|
||||
{
|
||||
std::string alu = "";
|
||||
|
||||
switch (OPF(code, F))
|
||||
{
|
||||
case F_MISC:
|
||||
switch (OPF(code, BADD))
|
||||
{
|
||||
case MF_FCLSR: alu = std::string("fclsr"); break;
|
||||
case MF_FSTSR: alu = std::string("fstsr"); break;
|
||||
|
||||
case MF_FMODE: alu = util::string_format("fmode 0x%04x", (OPF(code, ABIN) << 10) | (OPF(code, CADD) << 5) | OPF(code, AADD)); break;
|
||||
case MF_FABS: alu = util::string_format("fabs %4s, %-12s", reg(OPF(code, AADD)), adst(code)); break;
|
||||
case MF_FLOAT: alu = util::string_format("float %4s, %-12s", reg(OPF(code, AADD)), adst(code)); break;
|
||||
case MF_FIX: alu = util::string_format("fix %4s, %-12s", reg(OPF(code, AADD)), adst(code)); break;
|
||||
case MF_FLUT: alu = util::string_format("flut %4s, %-4s", reg(OPF(code, AADD)), reg(OPF(code, CADD))); break;
|
||||
|
||||
}
|
||||
break;
|
||||
case F_FSUBR: alu = util::string_format("fsubr %4s, %4s, %-12s", reg(OPF(code, AADD)), abin(code), adst(code)); break;
|
||||
case F_FSUB:
|
||||
if (!OPF(code, CWEN) || OPF(code, ADST) != 3 || OPF(code, ENCN))
|
||||
alu = util::string_format("fsub %4s, %4s, %-12s", reg(OPF(code, AADD)), abin(code), adst(code));
|
||||
else
|
||||
alu = std::string("fnop");
|
||||
break;
|
||||
case F_FADD:
|
||||
if (!OPF(code, CWEN) || OPF(code, ADST) != 3 || OPF(code, ENCN) || OPF(code, ABIN) != 7)
|
||||
alu = util::string_format("fadd %4s, %4s, %-12s", reg(OPF(code, AADD)), abin(code), adst(code));
|
||||
else
|
||||
alu = std::string("fnop");
|
||||
break;
|
||||
|
||||
case F_FMNA: alu = util::string_format("fmna %4s, %4s, %4s, %-12s", reg(OPF(code, AADD)), mbin(code), abin(code), adst(code)); break;
|
||||
case F_FMNS: alu = util::string_format("fmns %4s, %4s, %4s, %-12s", reg(OPF(code, AADD)), mbin(code), abin(code), adst(code)); break;
|
||||
case F_FMAC: alu = util::string_format("fmac %4s, %4s, %4s, %-12s", reg(OPF(code, AADD)), mbin(code), abin(code), adst(code)); break;
|
||||
}
|
||||
|
||||
switch (OPF(code, IOCT))
|
||||
{
|
||||
case 1: return util::string_format("%-32s ; floadrc %4s", alu, reg(OPF(code, DADD))); break;
|
||||
case 2: return util::string_format("%-32s ; fstore %4s", alu, reg(OPF(code, DADD))); break;
|
||||
case 3: return util::string_format("%-32s ; fload %4s", alu, reg(OPF(code, DADD))); break;
|
||||
default:
|
||||
return alu;
|
||||
}
|
||||
}
|
||||
|
||||
std::string wtl3132_device::reg(unsigned const reg)
|
||||
{
|
||||
return util::string_format(".f%d", reg);
|
||||
}
|
||||
|
||||
std::string wtl3132_device::mbin(u64 const code)
|
||||
{
|
||||
switch (OPF(code, MBIN))
|
||||
{
|
||||
case 0: return util::string_format(".f%d", OPF(code, BADD));
|
||||
case 1: return util::string_format("Cbus");
|
||||
}
|
||||
|
||||
// can't happen
|
||||
return std::string();
|
||||
}
|
||||
|
||||
std::string wtl3132_device::abin(u64 const code)
|
||||
{
|
||||
switch (OPF(code, ABIN))
|
||||
{
|
||||
case 0: return util::string_format("Cbus");
|
||||
case 1: return util::string_format(".f%d", OPF(code, BADD));
|
||||
case 2: return util::string_format(".t2");
|
||||
case 3: return util::string_format(".t1");
|
||||
case 4: return util::string_format(".t3");
|
||||
|
||||
case 6: return util::string_format("2");
|
||||
case 7: return util::string_format("0");
|
||||
}
|
||||
|
||||
return std::string();
|
||||
}
|
||||
|
||||
std::string wtl3132_device::adst(u64 const code)
|
||||
{
|
||||
switch (OPF(code, ADST))
|
||||
{
|
||||
case 0: return OPF(code, CWEN) ? util::string_format(".t3") : util::string_format(".f%d and .t3", OPF(code, CADD));
|
||||
case 1: return OPF(code, CWEN) ? util::string_format(".t2") : util::string_format(".f%d and .t2", OPF(code, CADD));
|
||||
case 2: return OPF(code, CWEN) ? util::string_format(".t1") : util::string_format(".f%d and .t1", OPF(code, CADD));
|
||||
case 3: return OPF(code, CWEN) ? std::string() : util::string_format(".f%d", OPF(code, CADD));
|
||||
}
|
||||
|
||||
// can't happen
|
||||
return std::string();
|
||||
}
|
||||
171
src/devices/machine/wtl3132.h
Normal file
171
src/devices/machine/wtl3132.h
Normal file
@ -0,0 +1,171 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Patrick Mackinlay
|
||||
|
||||
#ifndef MAME_MACHINE_WTL3132_H
|
||||
#define MAME_MACHINE_WTL3132_H
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "softfloat3/source/include/softfloat.h"
|
||||
|
||||
class wtl3132_device : public device_t
|
||||
{
|
||||
public:
|
||||
wtl3132_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
|
||||
|
||||
// output lines
|
||||
auto out_fpcn() { return m_fpcn_cb.bind(); }
|
||||
auto out_fpex() { return m_fpex_cb.bind(); }
|
||||
auto out_zero() { return m_zero_cb.bind(); }
|
||||
|
||||
// code and data ports
|
||||
void c_port_w(u64 data) { m_c_port = data; }
|
||||
u32 x_port_r() { return m_x_port.v; }
|
||||
void x_port_w(u32 data) { m_x_port.v = data; }
|
||||
|
||||
// input lines
|
||||
void abort_w(int state) { m_abort = state; }
|
||||
void clk_w(int state);
|
||||
void neut_w(int state) { m_neut = state; }
|
||||
void stall_w(int state) { m_stall = state; }
|
||||
|
||||
// disassembly helpers
|
||||
static std::string disassemble(u64 const code);
|
||||
static std::string reg(unsigned const reg);
|
||||
static std::string mbin(u64 const code);
|
||||
static std::string abin(u64 const code);
|
||||
static std::string adst(u64 const code);
|
||||
|
||||
enum code_mask : u64
|
||||
{
|
||||
// opcode is 34 bits wide
|
||||
M_ENCN = 0x0'00000003, // condition output select
|
||||
M_MBIN = 0x0'00000004, // mbin input select
|
||||
M_ADST = 0x0'00000018, // alu destination select
|
||||
M_ABIN = 0x0'000000e0, // abin input select
|
||||
M_DADD = 0x0'00001f00, // d port register address
|
||||
M_IOCT = 0x0'00006000, // i/o control
|
||||
M_CWEN = 0x0'00008000, // c port write enable (active low)
|
||||
M_CADD = 0x0'001f0000, // c port register address
|
||||
M_BADD = 0x0'03e00000, // b port register address
|
||||
M_AADD = 0x0'7c000000, // a port register address
|
||||
M_F = 0x3'80000000, // function code
|
||||
|
||||
// internal pipeline control flag
|
||||
M_CANCEL = 0x80000000'00000000, // cancelled
|
||||
};
|
||||
|
||||
enum code_shift : unsigned
|
||||
{
|
||||
S_ENCN = 0, // condition output select
|
||||
S_MBIN = 2, // mbin input select
|
||||
S_ADST = 3, // alu destination select
|
||||
S_ABIN = 5, // abin input select
|
||||
S_DADD = 8, // d port register address
|
||||
S_IOCT = 13, // i/o control
|
||||
S_CWEN = 15, // c port write enable (active low)
|
||||
S_CADD = 16, // c port register address
|
||||
S_BADD = 21, // b port register address
|
||||
S_AADD = 26, // a port register address
|
||||
S_F = 31, // function code
|
||||
};
|
||||
|
||||
enum function_code : unsigned
|
||||
{
|
||||
F_MISC = 0, // miscellaneous
|
||||
F_FSUBR = 1, // negate and add
|
||||
F_FSUB = 2, // subtract
|
||||
F_FADD = 3, // add
|
||||
F_FMNA = 5, // multiply, negate and add
|
||||
F_FMNS = 6, // multiply, negate and subtract
|
||||
F_FMAC = 7, // multiply and accumulate
|
||||
};
|
||||
|
||||
enum misc_code : unsigned
|
||||
{
|
||||
MF_FCLSR = 0, // clear status register
|
||||
MF_FSTSR = 1, // read status register
|
||||
MF_FMODE = 3, // load mode register
|
||||
MF_FABS = 4, // absolute value
|
||||
MF_FLOAT = 5, // fixed-to-float
|
||||
MF_FIX = 6, // float-to-fixed
|
||||
MF_FLUT = 7, // lookup operation
|
||||
};
|
||||
|
||||
enum mode_mask : u16
|
||||
{
|
||||
MODE_IBA = 0x0001, // internal bypass A enable
|
||||
MODE_RTN = 0x0002, // round to nearest
|
||||
MODE_IBP = 0x0008, // input bypass enable
|
||||
MODE_OBP = 0x0010, // output bypass enable
|
||||
MODE_FXO = 0x0020, // fpex overflow enable
|
||||
MODE_CPL = 0x0040, // coprocessor load enable
|
||||
MODE_FXH = 0x0100, // fpex active high
|
||||
MODE_DBP = 0x0200, // double pump enable (3332 only)
|
||||
MODE_IBB = 0x0800, // internal bypass B enable
|
||||
MODE_YLI = 0x1000, // Y late input enable (3332 only)
|
||||
};
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
void stage1(unsigned const index);
|
||||
void stage2(unsigned const index);
|
||||
void stage3(unsigned const index);
|
||||
void stage4(unsigned const index);
|
||||
|
||||
private:
|
||||
devcb_write_line m_fpcn_cb;
|
||||
devcb_write_line m_fpex_cb;
|
||||
devcb_write_line m_zero_cb;
|
||||
|
||||
// output line state
|
||||
bool m_fpcn_state;
|
||||
bool m_fpex_state;
|
||||
bool m_zero_state;
|
||||
|
||||
// port state
|
||||
u64 m_c_port;
|
||||
float32_t m_x_port;
|
||||
float32_t m_x_in;
|
||||
float32_t m_x_out;
|
||||
|
||||
// input line state
|
||||
int m_abort;
|
||||
int m_neut;
|
||||
int m_stall;
|
||||
|
||||
// pipeline state
|
||||
u64 m_slot[4];
|
||||
unsigned m_head;
|
||||
|
||||
// registers
|
||||
u16 m_mode;
|
||||
float32_t m_f[32];
|
||||
float32_t m_t1;
|
||||
float32_t m_t2;
|
||||
float32_t m_t3;
|
||||
bool m_cr;
|
||||
bool m_sr;
|
||||
bool m_zr;
|
||||
|
||||
// C bus
|
||||
float32_t m_c_bus_data;
|
||||
unsigned m_c_bus_addr;
|
||||
bool m_c_bus_cwen;
|
||||
|
||||
// multiplier inputs and output
|
||||
float32_t m_ma_in;
|
||||
float32_t m_mb_in;
|
||||
float32_t m_m_out;
|
||||
|
||||
// accumulator buffers, inputs and output
|
||||
float32_t m_aa_in[2];
|
||||
float32_t m_ab_in[2];
|
||||
float32_t m_a_out;
|
||||
};
|
||||
|
||||
DECLARE_DEVICE_TYPE(WTL3132, wtl3132_device)
|
||||
|
||||
#endif // MAME_MACHINE_WTL3132_H
|
||||
Loading…
Reference in New Issue
Block a user