M680x0 updates [Hans Ostermeyer]
- Instruction cache emulated on '020 and later - Fixed interaction between MMU and bfextu/bfexts/bfins - Added fsgldiv, fsglmul, and fscc FPU instructions - Fixed fault address in stack frame - Fixed supervisor violation bit in MMU status register - Add fmovem modes 1 and 3 - Various other MMU fixes
This commit is contained in:
R. Belmont
parent
18aca550f0
commit
1fcc151bc9
@ -2634,17 +2634,20 @@ M68KMAKE_OP(bfexts, 32, ., .)
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if(BIT_5(word2))
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width = REG_D[width&7];
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/* Offset is signed so we have to use ugly math =( */
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ea += offset / 8;
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offset %= 8;
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if(offset < 0)
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if(BIT_B(word2))
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{
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offset += 8;
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ea--;
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/* Offset is signed so we have to use ugly math =( */
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ea += offset / 8;
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offset %= 8;
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if(offset < 0)
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{
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offset += 8;
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ea--;
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}
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}
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width = ((width-1) & 31) + 1;
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data = m68ki_read_32(m68k, ea);
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data = (offset+width) < 16 ? (m68ki_read_16(m68k, ea) << 16) : m68ki_read_32(m68k, ea);
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data = MASK_OUT_ABOVE_32(data<<offset);
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@ -2716,17 +2719,20 @@ M68KMAKE_OP(bfextu, 32, ., .)
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if(BIT_5(word2))
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width = REG_D[width&7];
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/* Offset is signed so we have to use ugly math =( */
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ea += offset / 8;
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offset %= 8;
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if(offset < 0)
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if(BIT_B(word2))
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{
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offset += 8;
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ea--;
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/* Offset is signed so we have to use ugly math =( */
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ea += offset / 8;
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offset %= 8;
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if(offset < 0)
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{
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offset += 8;
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ea--;
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}
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}
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width = ((width-1) & 31) + 1;
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data = m68ki_read_32(m68k, ea);
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data = (offset+width) < 16 ? (m68ki_read_16(m68k, ea) << 16) : m68ki_read_32(m68k, ea);
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data = MASK_OUT_ABOVE_32(data<<offset);
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if((offset+width) > 32)
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@ -2813,7 +2819,7 @@ M68KMAKE_OP(bfffo, 32, ., .)
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}
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width = ((width-1) & 31) + 1;
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data = m68ki_read_32(m68k, ea);
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data = (offset+width) < 16 ? (m68ki_read_16(m68k, ea) << 16) : m68ki_read_32(m68k, ea);
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data = MASK_OUT_ABOVE_32(data<<local_offset);
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if((local_offset+width) > 32)
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@ -2902,13 +2908,16 @@ M68KMAKE_OP(bfins, 32, ., .)
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if(BIT_5(word2))
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width = REG_D[width&7];
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/* Offset is signed so we have to use ugly math =( */
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ea += offset / 8;
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offset %= 8;
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if(offset < 0)
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if(BIT_B(word2))
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{
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offset += 8;
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ea--;
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/* Offset is signed so we have to use ugly math =( */
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ea += offset / 8;
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offset %= 8;
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if(offset < 0)
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{
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offset += 8;
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ea--;
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}
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}
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width = ((width-1) & 31) + 1;
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@ -2920,11 +2929,18 @@ M68KMAKE_OP(bfins, 32, ., .)
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m68k->not_z_flag = insert_base;
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insert_long = insert_base >> offset;
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data_long = m68ki_read_32(m68k, ea);
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data_long = (offset+width) < 16 ? (m68ki_read_16(m68k, ea) << 16) : m68ki_read_32(m68k, ea);
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m68k->v_flag = VFLAG_CLEAR;
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m68k->c_flag = CFLAG_CLEAR;
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m68ki_write_32(m68k, ea, (data_long & ~mask_long) | insert_long);
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if((width + offset) < 16)
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{
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m68ki_write_16(m68k, ea, ((data_long & ~mask_long) | insert_long) >> 16);
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}
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else
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{
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m68ki_write_32(m68k, ea, (data_long & ~mask_long) | insert_long);
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}
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if((width + offset) > 32)
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{
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@ -6684,6 +6700,12 @@ M68KMAKE_OP(movec, 32, rc, .)
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{
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m68k->cacr = REG_DA[(word2 >> 12) & 15] & 0x0f;
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}
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// logerror("movec to cacr=%04x\n", m68k->cacr);
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if (m68k->cacr & (M68K_CACR_CI | M68K_CACR_CEI))
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{
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m68ki_ic_clear(m68k);
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}
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return;
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}
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m68ki_exception_illegal(m68k);
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@ -632,9 +632,9 @@ static CPU_EXECUTE( m68k )
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/* Call external hook to peek at CPU */
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debugger_instruction_hook(device, REG_PC);
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// FIXME: remove this
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// void apollo_debug_instruction(device_t *device);
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// apollo_debug_instruction(device);
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/* call external instruction hook (independent of debug mode) */
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if (m68k->instruction_hook != NULL)
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m68k->instruction_hook(device, REG_PC);
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/* Record previous program counter */
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REG_PPC = REG_PC;
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@ -672,13 +672,6 @@ static CPU_EXECUTE( m68k )
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{
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UINT32 sr;
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// const char * disassemble(m68ki_cpu_core *m68k, offs_t pc);
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// logerror(
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// "PMMU: pc=%08x sp=%08x va=%08x bus error: %s\n",
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// REG_PPC, REG_A[7], m68k->mmu_tmp_buserror_address,
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// (m68k->mmu_tmp_buserror_address == REG_PPC) ? "-"
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// : disassemble(m68k, REG_PPC));
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m68k->mmu_tmp_buserror_occurred = 0;
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// restore cpu address registers to value at start of instruction
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@ -821,6 +814,15 @@ static CPU_RESET( m68k )
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/* flush the MMU's cache */
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pmmu_atc_flush(m68k);
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if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type))
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{
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// clear instruction cache
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m68ki_ic_clear(m68k);
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}
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// disable instruction hook
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m68k->instruction_hook = NULL;
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}
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static CPU_DISASSEMBLE( m68k )
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@ -103,6 +103,15 @@ typedef struct _m68ki_cpu_core m68ki_cpu_core;
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/* MMU constants */
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#define MMU_ATC_ENTRIES (22) // 68851 has 64, 030 has 22
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/* instruction cache constants */
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#define M68K_IC_SIZE 128
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#define M68K_CACR_IBE 0x10 // Instruction Burst Enable
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#define M68K_CACR_CI 0x08 // Clear Instruction Cache
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#define M68K_CACR_CEI 0x04 // Clear Entry in Instruction Cache
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#define M68K_CACR_FI 0x02 // Freeze Instruction Cache
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#define M68K_CACR_EI 0x01 // Enable Instruction Cache
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/* ======================================================================== */
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/* ================================ MACROS ================================ */
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/* ======================================================================== */
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@ -706,6 +715,13 @@ struct _m68ki_cpu_core
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UINT16 mmu_tmp_rw; /* temporary hack: read/write (1/0) for the mmu */
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UINT32 mmu_tmp_buserror_address; /* temporary hack: (first) bus error address */
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UINT16 mmu_tmp_buserror_occurred; /* temporary hack: flag that bus error has occurred from mmu */
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UINT32 ic_address[M68K_IC_SIZE]; /* instruction cache address data */
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UINT16 ic_data[M68K_IC_SIZE]; /* instruction cache content data */
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/* external instruction hook (does not depend on debug mode) */
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typedef int (*instruction_hook_t)(device_t *device, offs_t curpc);
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instruction_hook_t instruction_hook;
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};
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@ -882,6 +898,43 @@ INLINE void m68kx_write_memory_32_pd(m68ki_cpu_core *m68k, unsigned int address,
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/* ---------------------------- Read Immediate ---------------------------- */
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// clear the instruction cache
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INLINE void m68ki_ic_clear(m68ki_cpu_core *m68k)
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{
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int i;
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for (i=0; i< M68K_IC_SIZE; i++) {
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m68k->ic_address[i] = ~0;
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}
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}
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// read immediate word using the instruction cache
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INLINE UINT32 m68ki_ic_readimm16(m68ki_cpu_core *m68k, UINT32 address)
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{
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if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type) && (m68k->cacr & M68K_CACR_EI))
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{
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UINT32 ic_offset = (address >> 1) % M68K_IC_SIZE;
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if (m68k->ic_address[ic_offset] == address)
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{
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return m68k->ic_data[ic_offset];
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}
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else
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{
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UINT32 data = m68k->memory.readimm16(address);
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if (!m68k->mmu_tmp_buserror_occurred)
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{
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m68k->ic_data[ic_offset] = data;
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m68k->ic_address[ic_offset] = address;
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}
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return data;
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}
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}
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else
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{
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return m68k->memory.readimm16(address);
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}
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}
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/* Handles all immediate reads, does address error check, function code setting,
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* and prefetching if they are enabled in m68kconf.h
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*/
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@ -896,14 +949,14 @@ INLINE UINT32 m68ki_read_imm_16(m68ki_cpu_core *m68k)
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if(REG_PC != m68k->pref_addr)
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{
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m68k->pref_data = m68k->memory.readimm16(REG_PC);
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m68k->pref_data = m68ki_ic_readimm16(m68k, REG_PC);
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m68k->pref_addr = m68k->mmu_tmp_buserror_occurred ? ~0 : REG_PC;
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}
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result = MASK_OUT_ABOVE_16(m68k->pref_data);
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REG_PC += 2;
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if (!m68k->mmu_tmp_buserror_occurred) {
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// prefetch only if no bus error occurred in opcode fetch
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m68k->pref_data = m68k->memory.readimm16(REG_PC);
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m68k->pref_data = m68ki_ic_readimm16(m68k, REG_PC);
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m68k->pref_addr = m68k->mmu_tmp_buserror_occurred ? ~0 : REG_PC;
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// ignore bus error on prefetch
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m68k->mmu_tmp_buserror_occurred = 0;
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@ -924,16 +977,16 @@ INLINE UINT32 m68ki_read_imm_32(m68ki_cpu_core *m68k)
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if(REG_PC != m68k->pref_addr)
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{
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m68k->pref_addr = REG_PC;
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m68k->pref_data = m68k->memory.readimm16(m68k->pref_addr);
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m68k->pref_data = m68ki_ic_readimm16(m68k, m68k->pref_addr);
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}
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temp_val = MASK_OUT_ABOVE_16(m68k->pref_data);
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REG_PC += 2;
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m68k->pref_addr = REG_PC;
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m68k->pref_data = m68k->memory.readimm16(m68k->pref_addr);
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m68k->pref_data = m68ki_ic_readimm16(m68k, m68k->pref_addr);
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temp_val = MASK_OUT_ABOVE_32((temp_val << 16) | MASK_OUT_ABOVE_16(m68k->pref_data));
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REG_PC += 2;
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m68k->pref_data = m68k->memory.readimm16(REG_PC);
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m68k->pref_data = m68ki_ic_readimm16(m68k, REG_PC);
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m68k->pref_addr = m68k->mmu_tmp_buserror_occurred ? ~0 : REG_PC;
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return temp_val;
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@ -1543,7 +1596,9 @@ void m68ki_stack_frame_1010(m68ki_cpu_core *m68k, UINT32 sr, UINT32 vector, UINT
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m68ki_push_16(m68k, 0);
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/* SPECIAL STATUS REGISTER */
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m68ki_push_16(m68k, 0);
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// set bit for: Rerun Faulted bus Cycle, or run pending prefetch
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// set FC
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m68ki_push_16(m68k, 0x0100 | m68k->mmu_tmp_fc );
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/* INTERNAL REGISTER */
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m68ki_push_16(m68k, 0);
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@ -1590,7 +1645,7 @@ void m68ki_stack_frame_1011(m68ki_cpu_core *m68k, UINT32 sr, UINT32 vector, UINT
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m68ki_push_32(m68k, 0);
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/* STAGE B ADDRESS (2 words) */
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m68ki_push_32(m68k, fault_address);
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m68ki_push_32(m68k, 0);
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/* INTERNAL REGISTER (4 words) */
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m68ki_push_32(m68k, 0);
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@ -1606,7 +1661,7 @@ void m68ki_stack_frame_1011(m68ki_cpu_core *m68k, UINT32 sr, UINT32 vector, UINT
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m68ki_push_16(m68k, 0);
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/* DATA CYCLE FAULT ADDRESS (2 words) */
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m68ki_push_32(m68k, 0);
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m68ki_push_32(m68k, fault_address);
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/* INSTRUCTION PIPE STAGE B */
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m68ki_push_16(m68k, 0);
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@ -1615,7 +1670,7 @@ void m68ki_stack_frame_1011(m68ki_cpu_core *m68k, UINT32 sr, UINT32 vector, UINT
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m68ki_push_16(m68k, 0);
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/* SPECIAL STATUS REGISTER */
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m68ki_push_16(m68k, 0);
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m68ki_push_16(m68k, 0x0100 | m68k->mmu_tmp_fc);
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/* INTERNAL REGISTER */
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m68ki_push_16(m68k, 0);
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@ -1318,6 +1318,11 @@ static void fpgen_rm_reg(m68ki_cpu_core *m68k, UINT16 w2)
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m68k->remaining_cycles -= 109;
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break;
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}
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// case 0x0e: // FSIN
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// {
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// // TODO
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// break;
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// }
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case 0x18: // FABS
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{
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REG_FP[dst] = source;
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@ -1365,6 +1370,12 @@ static void fpgen_rm_reg(m68ki_cpu_core *m68k, UINT16 w2)
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m68k->remaining_cycles -= 11;
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break;
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}
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case 0x24: // FSGLDIV
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{
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REG_FP[dst] = floatx80_div(REG_FP[dst], source);
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m68k->remaining_cycles -= 43; // // ? (value is from FDIV)
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break;
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}
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case 0x25: // FREM
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{
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REG_FP[dst] = floatx80_rem(REG_FP[dst], source);
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@ -1372,6 +1383,13 @@ static void fpgen_rm_reg(m68ki_cpu_core *m68k, UINT16 w2)
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m68k->remaining_cycles -= 43; // guess
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break;
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}
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case 0x27: // FSGLMUL
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{
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REG_FP[dst] = floatx80_mul(REG_FP[dst], source);
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SET_CONDITION_CODES(m68k, REG_FP[dst]);
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m68k->remaining_cycles -= 11; // ? (value is from FMUL)
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break;
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}
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case 0x28: // FSUB
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{
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REG_FP[dst] = floatx80_sub(REG_FP[dst], source);
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@ -1396,7 +1414,7 @@ static void fpgen_rm_reg(m68ki_cpu_core *m68k, UINT16 w2)
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break;
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}
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default: fatalerror("fpgen_rm_reg: unimplemented opmode %02X at %08X\n", opmode, REG_PC-4);
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default: fatalerror("fpgen_rm_reg: unimplemented opmode %02X at %08X\n", opmode, REG_PPC);
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}
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}
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@ -1507,6 +1525,10 @@ static void fmovem(m68ki_cpu_core *m68k, UINT16 w2)
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{
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switch (mode)
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{
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case 1: // Dynamic register list, postincrement or control addressing mode.
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// FIXME: not really tested, but seems to work
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reglist = REG_D[(reglist >> 4) & 7];
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case 0: // Static register list, predecrement or control addressing mode
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{
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for (i=0; i < 8; i++)
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@ -1531,13 +1553,41 @@ static void fmovem(m68ki_cpu_core *m68k, UINT16 w2)
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break;
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}
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default: fatalerror("040fpu0: FMOVEM: mode %d unimplemented at %08X\n", mode, REG_PC-4);
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case 2: // Static register list, postdecrement or control addressing mode
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{
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for (i=0; i < 8; i++)
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{
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if (reglist & (1 << i))
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{
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switch (ea >> 3)
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{
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case 5: // (d16, An)
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case 6: // (An) + (Xn) + d8
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store_extended_float80(m68k, mem_addr, REG_FP[7-i]);
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mem_addr += 12;
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break;
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default:
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WRITE_EA_FPE(m68k, ea, REG_FP[7-i]);
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break;
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}
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m68k->remaining_cycles -= 2;
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}
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}
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break;
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}
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default: fatalerror("M680x0: FMOVEM: mode %d unimplemented at %08X\n", mode, REG_PC-4);
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}
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}
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else // From mem to FP regs
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{
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switch (mode)
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{
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case 3: // Dynamic register list, predecrement addressing mode.
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// FIXME: not really tested, but seems to work
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reglist = REG_D[(reglist >> 4) & 7];
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case 2: // Static register list, postincrement or control addressing mode
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{
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for (i=0; i < 8; i++)
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@ -1561,11 +1611,20 @@ static void fmovem(m68ki_cpu_core *m68k, UINT16 w2)
|
||||
break;
|
||||
}
|
||||
|
||||
default: fatalerror("040fpu0: FMOVEM: mode %d unimplemented at %08X\n", mode, REG_PC-4);
|
||||
default: fatalerror("M680x0: FMOVEM: mode %d unimplemented at %08X\n", mode, REG_PC-4);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void fscc(m68ki_cpu_core *m68k)
|
||||
{
|
||||
int ea = m68k->ir & 0x3f;
|
||||
int condition = (INT16)(OPER_I_16(m68k));
|
||||
|
||||
WRITE_EA_8(m68k, ea, TEST_CONDITION(m68k, condition) ? 0xff : 0);
|
||||
m68k->remaining_cycles -= 7; // ???
|
||||
}
|
||||
|
||||
static void fbcc16(m68ki_cpu_core *m68k)
|
||||
{
|
||||
INT32 offset;
|
||||
@ -1646,15 +1705,15 @@ void m68040_fpu_op0(m68ki_cpu_core *m68k)
|
||||
|
||||
case 1: // FBcc disp16
|
||||
{
|
||||
switch ((m68k->ir >> 3) & 0x3) {
|
||||
switch ((m68k->ir >> 3) & 0x7) {
|
||||
case 1: // FDBcc
|
||||
// TODO:
|
||||
break;
|
||||
default: // FScc (?)
|
||||
// TODO:
|
||||
break;
|
||||
fscc(m68k);
|
||||
return;
|
||||
}
|
||||
fatalerror("M68kFPU: unimplemented main op %d with mode %d\n", (m68k->ir >> 6) & 0x3, (m68k->ir >> 3) & 0x7);
|
||||
fatalerror("M68kFPU: unimplemented main op %d with mode %d at %08X\n", (m68k->ir >> 6) & 0x3, (m68k->ir >> 3) & 0x7, REG_PPC);
|
||||
}
|
||||
|
||||
case 2: // FBcc disp16
|
||||
|
||||
@ -199,13 +199,13 @@ INLINE UINT32 get_dt2_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 ptest
|
||||
return tbl_entry;
|
||||
}
|
||||
|
||||
INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 ptest)
|
||||
INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 fc, UINT8 ptest)
|
||||
{
|
||||
UINT32 tbl_entry2 = m68k->program->read_dword(tptr);
|
||||
UINT32 tbl_entry = m68k->program->read_dword(tptr + 4);
|
||||
UINT32 dt = tbl_entry2 & M68K_MMU_DF_DT;
|
||||
|
||||
m68k->mmu_tmp_sr |= tbl_entry2 & 0x0100 ? M68K_MMU_SR_SUPERVISOR_ONLY : 0;
|
||||
m68k->mmu_tmp_sr |= ((tbl_entry2 & 0x0100) && !(fc & 4)) ? M68K_MMU_SR_SUPERVISOR_ONLY : 0;
|
||||
m68k->mmu_tmp_sr |= tbl_entry2 & 0x0004 ? M68K_MMU_SR_WRITE_PROTECT : 0;
|
||||
|
||||
if (!ptest)
|
||||
@ -272,27 +272,35 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 ptest
|
||||
// first see if this is already in the ATC
|
||||
for (i = 0; i < MMU_ATC_ENTRIES; i++)
|
||||
{
|
||||
// if tag bits and function code match, we've got it
|
||||
if (m68k->mmu_atc_tag[i] == atc_tag)
|
||||
if (m68k->mmu_atc_tag[i] != atc_tag)
|
||||
{
|
||||
if (m68k->mmu_tmp_rw || !(m68k->mmu_atc_data[i] & M68K_MMU_ATC_WRITE_PR))
|
||||
{
|
||||
// read access or write access and not write protected
|
||||
if (!m68k->mmu_tmp_rw && !ptest)
|
||||
{
|
||||
// FIXME: must set modified in PMMU tables as well
|
||||
m68k->mmu_atc_data[i] |= M68K_MMU_ATC_MODIFIED;
|
||||
}
|
||||
else
|
||||
{
|
||||
// FIXME: supervisor mode?
|
||||
m68k->mmu_tmp_sr = M68K_MMU_SR_MODIFIED;
|
||||
}
|
||||
addr_out = (m68k->mmu_atc_data[i]<<8) | (addr_in & ~(~0 << ps));
|
||||
// logerror("ATC[%2d] hit: log %08x -> phys %08x pc=%08x fc=%d\n", i, addr_in, addr_out, REG_PPC, fc);
|
||||
// pmmu_atc_count++;
|
||||
return addr_out;
|
||||
}
|
||||
// tag bits and function code don't match
|
||||
}
|
||||
else if (!m68k->mmu_tmp_rw && (m68k->mmu_atc_data[i] & M68K_MMU_ATC_WRITE_PR))
|
||||
{
|
||||
// write mode, but write protected
|
||||
}
|
||||
else if (!m68k->mmu_tmp_rw && !(m68k->mmu_atc_data[i] & M68K_MMU_ATC_MODIFIED))
|
||||
{
|
||||
// first write; must set modified in PMMU tables as well
|
||||
}
|
||||
else
|
||||
{
|
||||
// read access or write access and not write protected
|
||||
if (!m68k->mmu_tmp_rw && !ptest)
|
||||
{
|
||||
// FIXME: must set modified in PMMU tables as well
|
||||
m68k->mmu_atc_data[i] |= M68K_MMU_ATC_MODIFIED;
|
||||
}
|
||||
else
|
||||
{
|
||||
// FIXME: supervisor mode?
|
||||
m68k->mmu_tmp_sr = M68K_MMU_SR_MODIFIED;
|
||||
}
|
||||
addr_out = (m68k->mmu_atc_data[i] << 8) | (addr_in & ~(~0 << ps));
|
||||
// logerror("ATC[%2d] hit: log %08x -> phys %08x pc=%08x fc=%d\n", i, addr_in, addr_out, REG_PPC, fc);
|
||||
// pmmu_atc_count++;
|
||||
return addr_out;
|
||||
}
|
||||
}
|
||||
|
||||
@ -344,7 +352,7 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 ptest
|
||||
case M68K_MMU_DF_DT3: // valid 8 byte descriptors
|
||||
tofs *= 8;
|
||||
// if (verbose) logerror("PMMU: reading table A entries at %08x\n", tofs + tptr);
|
||||
tbl_entry = get_dt3_table_entry(m68k, tofs + tptr, ptest);
|
||||
tbl_entry = get_dt3_table_entry(m68k, tofs + tptr, fc, ptest);
|
||||
tamode = tbl_entry & M68K_MMU_DF_DT;
|
||||
// if (verbose) logerror("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tamode, tofs);
|
||||
break;
|
||||
@ -377,7 +385,7 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 ptest
|
||||
case M68K_MMU_DF_DT3: // 8-byte table B descriptor
|
||||
tofs *= 8;
|
||||
// if (verbose) logerror("PMMU: reading table B entries at %08x\n", tofs + tptr);
|
||||
tbl_entry = get_dt3_table_entry(m68k, tptr + tofs, ptest);
|
||||
tbl_entry = get_dt3_table_entry(m68k, tptr + tofs, fc, ptest);
|
||||
tbmode = tbl_entry & M68K_MMU_DF_DT;
|
||||
tbl_entry &= ~M68K_MMU_DF_DT;
|
||||
// if (verbose) logerror("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tbmode, tofs);
|
||||
@ -421,7 +429,7 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 ptest
|
||||
case M68K_MMU_DF_DT3: // 8-byte table C descriptor
|
||||
tofs *= 8;
|
||||
// if (verbose) logerror("PMMU: reading table C entries at %08x\n", tofs + tptr);
|
||||
tbl_entry = get_dt3_table_entry(m68k, tptr+ tofs, ptest);
|
||||
tbl_entry = get_dt3_table_entry(m68k, tptr+ tofs, fc, ptest);
|
||||
tcmode = tbl_entry & M68K_MMU_DF_DT;
|
||||
// if (verbose) logerror("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tcmode, tofs);
|
||||
break;
|
||||
@ -470,7 +478,7 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 ptest
|
||||
m68k->mmu_tmp_buserror_address = addr_in;
|
||||
}
|
||||
}
|
||||
else if ((m68k->mmu_tmp_sr & M68K_MMU_SR_SUPERVISOR_ONLY) && !(fc & 4))
|
||||
else if (m68k->mmu_tmp_sr & M68K_MMU_SR_SUPERVISOR_ONLY)
|
||||
{
|
||||
if (++m68k->mmu_tmp_buserror_occurred == 1)
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user