diff --git a/src/emu/cpu/pic16c5x/pic16c5x.c b/src/emu/cpu/pic16c5x/pic16c5x.c
index a1489da58e0..6820bad7c74 100644
--- a/src/emu/cpu/pic16c5x/pic16c5x.c
+++ b/src/emu/cpu/pic16c5x/pic16c5x.c
@@ -110,10 +110,17 @@ pic16c5x_device::pic16c5x_device(const machine_config &mconfig, device_type type
 		, ( ( program_width == 9 ) ? ADDRESS_MAP_NAME(pic16c5x_rom_9) : ( ( program_width == 10 ) ? ADDRESS_MAP_NAME(pic16c5x_rom_10) : ADDRESS_MAP_NAME(pic16c5x_rom_11) )))
 	, m_data_config("data", ENDIANNESS_LITTLE, 8, data_width, 0
 		, ( ( data_width == 5 ) ? ADDRESS_MAP_NAME(pic16c5x_ram_5) : ADDRESS_MAP_NAME(pic16c5x_ram_7) ) )
-	, m_io_config("io", ENDIANNESS_LITTLE, 8, 5, 0)
 	, m_reset_vector((program_width == 9) ? 0x1ff : ((program_width == 10) ? 0x3ff : 0x7ff))
 	, m_picmodel(picmodel)
+	, m_temp_config(0)
 	, m_picRAMmask((data_width == 5) ? 0x1f : 0x7f)
+	, m_read_a(*this)
+	, m_read_b(*this)
+	, m_read_c(*this)
+	, m_write_a(*this)
+	, m_write_b(*this)
+	, m_write_c(*this)
+	, m_read_t0(*this)
 {
 }
 
@@ -161,17 +168,10 @@ void pic16c5x_device::update_internalram_ptr()
 #define PIC16C5x_RDOP(A)         (m_direct->read_decrypted_word((A)<<1))
 #define PIC16C5x_RAM_RDMEM(A)    ((UINT8)m_data->read_byte(A))
 #define PIC16C5x_RAM_WRMEM(A,V)  (m_data->write_byte(A,V))
-#define PIC16C5x_In(Port)        ((UINT8)m_io->read_byte((Port)))
-#define PIC16C5x_Out(Port,Value) (m_io->write_byte((Port),Value))
-/************  Read the state of the T0 Clock input signal  ************/
-#define PIC16C5x_T0_In           (m_io->read_byte(PIC16C5x_T0))
 
 #define M_RDRAM(A)      (((A) < 8) ? m_internalram[A] : PIC16C5x_RAM_RDMEM(A))
 #define M_WRTRAM(A,V)   do { if ((A) < 8) m_internalram[A] = (V); else PIC16C5x_RAM_WRMEM(A,V); } while (0)
 #define M_RDOP(A)       PIC16C5x_RDOP(A)
-#define P_IN(A)         PIC16C5x_In(A)
-#define P_OUT(A,V)      PIC16C5x_Out(A,V)
-#define S_T0_IN         PIC16C5x_T0_In
 #define ADDR_MASK       0x7ff
 
 
@@ -332,17 +332,17 @@ UINT8 pic16c5x_device::GET_REGFILE(offs_t addr) /* Read from internal memory */
 					break;
 		case 04:    data = (FSR | (UINT8)(~m_picRAMmask));
 					break;
-		case 05:    data = P_IN(0);
+		case 05:    data = m_read_a(PIC16C5x_PORTA, 0xff);
 					data &= m_TRISA;
 					data |= ((UINT8)(~m_TRISA) & PORTA);
 					data &= 0x0f;       /* 4-bit port (only lower 4 bits used) */
 					break;
-		case 06:    data = P_IN(1);
+		case 06:    data = m_read_b(PIC16C5x_PORTB, 0xff);
 					data &= m_TRISB;
 					data |= ((UINT8)(~m_TRISB) & PORTB);
 					break;
 		case 07:    if ((m_picmodel == 0x16C55) || (m_picmodel == 0x16C57)) {
-						data = P_IN(2);
+						data = m_read_c(PIC16C5x_PORTC, 0xff);
 						data &= m_TRISC;
 						data |= ((UINT8)(~m_TRISC) & PORTC);
 					}
@@ -384,12 +384,14 @@ void pic16c5x_device::STORE_REGFILE(offs_t addr, UINT8 data)    /* Write to inte
 		case 04:    FSR = (data | (UINT8)(~m_picRAMmask));
 					break;
 		case 05:    data &= 0x0f;       /* 4-bit port (only lower 4 bits used) */
-					P_OUT(0,data & (UINT8)(~m_TRISA)); PORTA = data;
+					m_write_a(PIC16C5x_PORTA, data & (UINT8)(~m_TRISA), 0xff);
+					PORTA = data;
 					break;
-		case 06:    P_OUT(1,data & (UINT8)(~m_TRISB)); PORTB = data;
+		case 06:    m_write_b(PIC16C5x_PORTB, data & (UINT8)(~m_TRISB), 0xff);
+					PORTB = data;
 					break;
 		case 07:    if ((m_picmodel == 0x16C55) || (m_picmodel == 0x16C57)) {
-						P_OUT(2,data & (UINT8)(~m_TRISC));
+						m_write_c(PIC16C5x_PORTC, data & (UINT8)(~m_TRISC), 0xff);
 						PORTC = data;
 					}
 					else {      /* PIC16C54, PIC16C56, PIC16C58 */
@@ -665,12 +667,12 @@ void pic16c5x_device::tris()
 	switch(m_opcode.b.l & 0x7)
 	{
 		case 05:    if   (m_TRISA == m_W) break;
-					else { m_TRISA = m_W | 0xf0; P_OUT(0,PORTA & (UINT8)(~m_TRISA) & 0x0f); break; }
+					else { m_TRISA = m_W | 0xf0; m_write_a(PIC16C5x_PORTA, PORTA & (UINT8)(~m_TRISA) & 0x0f, 0xff); break; }
 		case 06:    if   (m_TRISB == m_W) break;
-					else { m_TRISB = m_W; P_OUT(1,PORTB & (UINT8)(~m_TRISB)); break; }
+					else { m_TRISB = m_W; m_write_b(PIC16C5x_PORTB, PORTB & (UINT8)(~m_TRISB), 0xff); break; }
 		case 07:    if ((m_picmodel == 0x16C55) || (m_picmodel == 0x16C57)) {
 						if   (m_TRISC == m_W) break;
-						else { m_TRISC = m_W; P_OUT(2,PORTC & (UINT8)(~m_TRISC)); break; }
+						else { m_TRISC = m_W; m_write_c(PIC16C5x_PORTC, PORTC & (UINT8)(~m_TRISC), 0xff); break; }
 					}
 					else {
 						illegal(); break;
@@ -783,12 +785,28 @@ const pic16c5x_device::pic16c5x_opcode pic16c5x_device::s_opcode_00x[16]=
  *  Inits CPU emulation
  ****************************************************************************/
 
+enum
+{
+	PIC16C5x_PC=1, PIC16C5x_STK0, PIC16C5x_STK1, PIC16C5x_FSR,
+	PIC16C5x_W,    PIC16C5x_ALU,  PIC16C5x_STR,  PIC16C5x_OPT,
+	PIC16C5x_TMR0, PIC16C5x_PRTA, PIC16C5x_PRTB, PIC16C5x_PRTC,
+	PIC16C5x_WDT,  PIC16C5x_TRSA, PIC16C5x_TRSB, PIC16C5x_TRSC,
+	PIC16C5x_PSCL
+};
+
 void pic16c5x_device::device_start()
 {
 	m_program = &space(AS_PROGRAM);
 	m_direct = &m_program->direct();
 	m_data = &space(AS_DATA);
-	m_io = &space(AS_IO);
+	
+	m_read_a.resolve_safe(0);
+	m_read_b.resolve_safe(0);
+	m_read_c.resolve_safe(0);
+	m_write_a.resolve_safe();
+	m_write_b.resolve_safe();
+	m_write_c.resolve_safe();
+	m_read_t0.resolve_safe(0);
 
 	/* ensure the internal ram pointers are set before get_info is called */
 	update_internalram_ptr();
@@ -955,10 +973,10 @@ void pic16c5x_device::pic16c5x_soft_reset()
 	pic16c5x_reset_regs();
 }
 
-void pic16c5x_device::pic16c5x_set_config(int data)
+void pic16c5x_device::pic16c5x_set_config(UINT16 data)
 {
 	logerror("Writing %04x to the PIC16C5x config register\n",data);
-	m_temp_config = (data & 0xfff);
+	m_temp_config = data;
 }
 
 
@@ -1071,8 +1089,7 @@ void pic16c5x_device::execute_run()
 			}
 
 			if (T0CS) {                     /* Count mode */
-				T0_in = S_T0_IN;
-				if (T0_in) T0_in = 1;
+				T0_in = m_read_t0() ? 1 : 0;
 				if (T0SE) {                 /* Count falling edge T0 input */
 					if (FALLING_EDGE_T0) {
 						pic16c5x_update_timer(1);
diff --git a/src/emu/cpu/pic16c5x/pic16c5x.h b/src/emu/cpu/pic16c5x/pic16c5x.h
index 29fc0a00fb3..92a62d3f207 100644
--- a/src/emu/cpu/pic16c5x/pic16c5x.h
+++ b/src/emu/cpu/pic16c5x/pic16c5x.h
@@ -15,26 +15,40 @@
 #define __PIC16C5X_H__
 
 
-
-
-/**************************************************************************
- *  Internal Clock divisor
- *
- *  External Clock is divided internally by 4 for the instruction cycle
- *  times. (Each instruction cycle passes through 4 machine states). This
- *  is handled by the cpu execution engine.
- */
-
+// i/o ports
 enum
 {
-	PIC16C5x_PC=1, PIC16C5x_STK0, PIC16C5x_STK1, PIC16C5x_FSR,
-	PIC16C5x_W,    PIC16C5x_ALU,  PIC16C5x_STR,  PIC16C5x_OPT,
-	PIC16C5x_TMR0, PIC16C5x_PRTA, PIC16C5x_PRTB, PIC16C5x_PRTC,
-	PIC16C5x_WDT,  PIC16C5x_TRSA, PIC16C5x_TRSB, PIC16C5x_TRSC,
-	PIC16C5x_PSCL
+	PIC16C5x_PORTA = 0,
+	PIC16C5x_PORTB,
+	PIC16C5x_PORTC
 };
 
-#define PIC16C5x_T0     0x10
+// port a, 4 bits, 2-way
+#define MCFG_PIC16C5x_READ_A_CB(_devcb) \
+	pic16c5x_device::set_read_a_callback(*device, DEVCB_##_devcb);
+#define MCFG_PIC16C5x_WRITE_A_CB(_devcb) \
+	pic16c5x_device::set_write_a_callback(*device, DEVCB_##_devcb);
+
+// port b, 8 bits, 2-way
+#define MCFG_PIC16C5x_READ_B_CB(_devcb) \
+	pic16c5x_device::set_read_b_callback(*device, DEVCB_##_devcb);
+#define MCFG_PIC16C5x_WRITE_B_CB(_devcb) \
+	pic16c5x_device::set_write_b_callback(*device, DEVCB_##_devcb);
+
+// port c, 8 bits, 2-way
+#define MCFG_PIC16C5x_READ_C_CB(_devcb) \
+	pic16c5x_device::set_read_c_callback(*device, DEVCB_##_devcb);
+#define MCFG_PIC16C5x_WRITE_C_CB(_devcb) \
+	pic16c5x_device::set_write_c_callback(*device, DEVCB_##_devcb);
+
+// T0 pin (readline)
+#define MCFG_PIC16C5x_T0_CB(_devcb) \
+	pic16c5x_device::set_t0_callback(*device, DEVCB_##_devcb);
+
+// CONFIG register
+#define MCFG_PIC16C5x_SET_CONFIG(_data) \
+	pic16c5x_device::set_config_static(*device, _data);
+
 
 
 extern const device_type PIC16C54;
@@ -50,12 +64,26 @@ public:
 	// construction/destruction
 	pic16c5x_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, int program_width, int data_width, int picmodel);
 
+	// static configuration helpers
+	template<class _Object> static devcb_base &set_read_a_callback(device_t &device, _Object object) { return downcast<pic16c5x_device &>(device).m_read_a.set_callback(object); }
+	template<class _Object> static devcb_base &set_read_b_callback(device_t &device, _Object object) { return downcast<pic16c5x_device &>(device).m_read_b.set_callback(object); }
+	template<class _Object> static devcb_base &set_read_c_callback(device_t &device, _Object object) { return downcast<pic16c5x_device &>(device).m_read_c.set_callback(object); }
+
+	template<class _Object> static devcb_base &set_write_a_callback(device_t &device, _Object object) { return downcast<pic16c5x_device &>(device).m_write_a.set_callback(object); }
+	template<class _Object> static devcb_base &set_write_b_callback(device_t &device, _Object object) { return downcast<pic16c5x_device &>(device).m_write_b.set_callback(object); }
+	template<class _Object> static devcb_base &set_write_c_callback(device_t &device, _Object object) { return downcast<pic16c5x_device &>(device).m_write_c.set_callback(object); }
+
+	template<class _Object> static devcb_base &set_t0_callback(device_t &device, _Object object) { return downcast<pic16c5x_device &>(device).m_read_t0.set_callback(object); }
+
 	/****************************************************************************
 	 *  Function to configure the CONFIG register. This is actually hard-wired
 	 *  during ROM programming, so should be called in the driver INIT, with
 	 *  the value if known (available in HEX dumps of the ROM).
 	 */
-	void pic16c5x_set_config(int data);
+	void pic16c5x_set_config(UINT16 data);
+	
+	// or with a macro
+	static void set_config_static(device_t &device, UINT16 data) { downcast<pic16c5x_device &>(device).m_temp_config = data; }
 
 protected:
 	// device-level overrides
@@ -63,6 +91,13 @@ protected:
 	virtual void device_reset();
 
 	// device_execute_interface overrides
+	/**************************************************************************
+	 *  Internal Clock divisor
+	 *
+	 *  External Clock is divided internally by 4 for the instruction cycle
+	 *  times. (Each instruction cycle passes through 4 machine states). This
+	 *  is handled by the cpu execution engine.
+	 */
 	virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 4 - 1) / 4; }
 	virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 4); }
 	virtual UINT32 execute_min_cycles() const { return 1; }
@@ -74,7 +109,7 @@ protected:
 	// device_memory_interface overrides
 	virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const
 	{
-		return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ) );
+		return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL );
 	}
 
 	// device_state_interface overrides
@@ -90,7 +125,6 @@ protected:
 private:
 	address_space_config m_program_config;
 	address_space_config m_data_config;
-	address_space_config m_io_config;
 
 	/******************** CPU Internal Registers *******************/
 	UINT16  m_PC;
@@ -121,7 +155,15 @@ private:
 	address_space *m_program;
 	direct_read_data *m_direct;
 	address_space *m_data;
-	address_space *m_io;
+	
+	// i/o handlers
+	devcb_read8 m_read_a;
+	devcb_read8 m_read_b;
+	devcb_read8 m_read_c;
+	devcb_write8 m_write_a;
+	devcb_write8 m_write_b;
+	devcb_write8 m_write_c;
+	devcb_read_line m_read_t0;
 
 	// For debugger
 	int m_debugger_temp;
diff --git a/src/mame/drivers/bingor.c b/src/mame/drivers/bingor.c
index 184f0cd9271..09daf003a5e 100644
--- a/src/mame/drivers/bingor.c
+++ b/src/mame/drivers/bingor.c
@@ -453,8 +453,6 @@ public:
 		m_palette(*this, "palette")  { }
 
 	required_shared_ptr<UINT16> m_blit_ram;
-	DECLARE_READ16_MEMBER(test_r);
-	DECLARE_READ8_MEMBER(test8_r);
 	virtual void video_start();
 	UINT32 screen_update_bingor(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
 	INTERRUPT_GEN_MEMBER(vblank_irq);
@@ -509,12 +507,6 @@ UINT32 bingor_state::screen_update_bingor(screen_device &screen, bitmap_rgb32 &b
 	return 0;
 }
 
-#if 0
-READ16_MEMBER(bingor_state::test_r)
-{
-	return machine().rand();
-}
-#endif
 
 static ADDRESS_MAP_START( bingor_map, AS_PROGRAM, 16, bingor_state )
 	AM_RANGE(0x00000, 0x0ffff) AM_RAM
@@ -525,22 +517,10 @@ static ADDRESS_MAP_START( bingor_map, AS_PROGRAM, 16, bingor_state )
 ADDRESS_MAP_END
 
 static ADDRESS_MAP_START( bingor_io, AS_IO, 16, bingor_state )
-//  AM_RANGE(0x0000, 0x00ff) AM_READ(test_r )
 	AM_RANGE(0x0100, 0x0101) AM_DEVWRITE8("saa", saa1099_device, data_w, 0x00ff)
 	AM_RANGE(0x0102, 0x0103) AM_DEVWRITE8("saa", saa1099_device, control_w, 0x00ff)
-//  AM_RANGE(0x0200, 0x0201) AM_READ(test_r )
 ADDRESS_MAP_END
 
-READ8_MEMBER(bingor_state::test8_r)
-{
-	return machine().rand();
-}
-
-static ADDRESS_MAP_START( pic_io_map, AS_IO, 8, bingor_state )
-	AM_RANGE(0x00, 0x00) AM_WRITENOP
-	AM_RANGE(0x02, 0x02) AM_READ(test8_r)
-	AM_RANGE(0x10, 0x10) AM_READNOP
-ADDRESS_MAP_END
 
 static INPUT_PORTS_START( bingor )
 	PORT_START("IN0")
@@ -631,8 +611,6 @@ static MACHINE_CONFIG_START( bingor, bingor_state )
 	MCFG_CPU_PERIODIC_INT_DRIVER(bingor_state, unk_irq,  30)
 
 	MCFG_CPU_ADD("pic", PIC16C57, 12000000) //?? Mhz
-	MCFG_CPU_IO_MAP(pic_io_map)
-
 
 	MCFG_GFXDECODE_ADD("gfxdecode", "palette", bingor)
 	//MCFG_NVRAM_ADD_0FILL("nvram")
diff --git a/src/mame/drivers/blackt96.c b/src/mame/drivers/blackt96.c
index 6d1e8824792..25010f90bdf 100644
--- a/src/mame/drivers/blackt96.c
+++ b/src/mame/drivers/blackt96.c
@@ -117,7 +117,7 @@ public:
 	required_shared_ptr<UINT16> m_spriteram7;
 	DECLARE_WRITE16_MEMBER(blackt96_c0000_w);
 	DECLARE_WRITE16_MEMBER(blackt96_80000_w);
-	DECLARE_READ8_MEMBER(PIC16C5X_T0_clk_r);
+	DECLARE_READ_LINE_MEMBER(PIC16C5X_T0_clk_r);
 	DECLARE_WRITE8_MEMBER(blackt96_soundio_port00_w);
 	DECLARE_READ8_MEMBER(blackt96_soundio_port01_r);
 	DECLARE_WRITE8_MEMBER(blackt96_soundio_port01_w);
@@ -560,7 +560,7 @@ static GFXDECODE_START( blackt96 )
 GFXDECODE_END
 
 
-READ8_MEMBER(blackt96_state::PIC16C5X_T0_clk_r)
+READ_LINE_MEMBER(blackt96_state::PIC16C5X_T0_clk_r)
 {
 	return 0;
 }
@@ -587,13 +587,6 @@ WRITE8_MEMBER(blackt96_state::blackt96_soundio_port02_w)
 {
 }
 
-static ADDRESS_MAP_START( sound_io_map, AS_IO, 8, blackt96_state )
-	AM_RANGE(0x00, 0x00) AM_WRITE(blackt96_soundio_port00_w )
-	AM_RANGE(0x01, 0x01) AM_READWRITE(blackt96_soundio_port01_r, blackt96_soundio_port01_w )
-	AM_RANGE(0x02, 0x02) AM_READWRITE(blackt96_soundio_port02_r, blackt96_soundio_port02_w )
-	AM_RANGE(PIC16C5x_T0, PIC16C5x_T0) AM_READ(PIC16C5X_T0_clk_r)
-ADDRESS_MAP_END
-
 
 
 static MACHINE_CONFIG_START( blackt96, blackt96_state )
@@ -602,7 +595,12 @@ static MACHINE_CONFIG_START( blackt96, blackt96_state )
 	MCFG_CPU_VBLANK_INT_DRIVER("screen", blackt96_state,  irq1_line_hold)
 
 	MCFG_CPU_ADD("audiocpu", PIC16C57, 8000000) /* ? */
-	MCFG_CPU_IO_MAP(sound_io_map)
+	MCFG_PIC16C5x_WRITE_A_CB(WRITE8(blackt96_state, blackt96_soundio_port00_w))
+	MCFG_PIC16C5x_READ_B_CB(READ8(blackt96_state, blackt96_soundio_port01_r))
+	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(blackt96_state, blackt96_soundio_port01_w))
+	MCFG_PIC16C5x_READ_C_CB(READ8(blackt96_state, blackt96_soundio_port02_r))
+	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(blackt96_state, blackt96_soundio_port02_w))
+	MCFG_PIC16C5x_T0_CB(READLINE(blackt96_state, PIC16C5X_T0_clk_r))
 
 	MCFG_GFXDECODE_ADD("gfxdecode", "palette", blackt96)
 
diff --git a/src/mame/drivers/drgnmst.c b/src/mame/drivers/drgnmst.c
index 8d400107d67..7d885e2a883 100644
--- a/src/mame/drivers/drgnmst.c
+++ b/src/mame/drivers/drgnmst.c
@@ -174,7 +174,7 @@ WRITE8_MEMBER(drgnmst_state::drgnmst_snd_control_w)
 }
 
 
-READ8_MEMBER(drgnmst_state::PIC16C5X_T0_clk_r)
+READ_LINE_MEMBER(drgnmst_state::PIC16C5X_T0_clk_r)
 {
 	return 0;
 }
@@ -207,21 +207,6 @@ static ADDRESS_MAP_START( drgnmst_main_map, AS_PROGRAM, 16, drgnmst_state )
 ADDRESS_MAP_END
 
 
-
-/***************************** PIC16C55 Memory Map **************************/
-
-	/* $000 - 1FF  PIC16C55 Internal Program ROM. Note: code is 12bits wide */
-	/* $000 - 01F  PIC16C55 Internal Data RAM */
-
-static ADDRESS_MAP_START( drgnmst_sound_io_map, AS_IO, 8, drgnmst_state )
-	AM_RANGE(0x00, 0x00) AM_READWRITE(pic16c5x_port0_r, drgnmst_pcm_banksel_w)  /* 4 bit port */
-	AM_RANGE(0x01, 0x01) AM_READWRITE(drgnmst_snd_command_r, drgnmst_oki_w)
-	AM_RANGE(0x02, 0x02) AM_READWRITE(drgnmst_snd_flag_r, drgnmst_snd_control_w)
-	AM_RANGE(PIC16C5x_T0, PIC16C5x_T0) AM_READ(PIC16C5X_T0_clk_r)
-ADDRESS_MAP_END
-
-
-
 static INPUT_PORTS_START( drgnmst )
 	PORT_START("P1_P2")
 	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
@@ -396,9 +381,13 @@ static MACHINE_CONFIG_START( drgnmst, drgnmst_state )
 	MCFG_CPU_VBLANK_INT_DRIVER("screen", drgnmst_state,  irq2_line_hold)
 
 	MCFG_CPU_ADD("audiocpu", PIC16C55, 32000000/8)  /* Confirmed */
-	/* Program and Data Maps are internal to the MCU */
-	MCFG_CPU_IO_MAP(drgnmst_sound_io_map)
-
+	MCFG_PIC16C5x_READ_A_CB(READ8(drgnmst_state, pic16c5x_port0_r))
+	MCFG_PIC16C5x_WRITE_A_CB(WRITE8(drgnmst_state, drgnmst_pcm_banksel_w))
+	MCFG_PIC16C5x_READ_B_CB(READ8(drgnmst_state, drgnmst_snd_command_r))
+	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(drgnmst_state, drgnmst_oki_w))
+	MCFG_PIC16C5x_READ_C_CB(READ8(drgnmst_state, drgnmst_snd_flag_r))
+	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(drgnmst_state, drgnmst_snd_control_w))
+	MCFG_PIC16C5x_T0_CB(READLINE(drgnmst_state, PIC16C5X_T0_clk_r))
 
 	MCFG_GFXDECODE_ADD("gfxdecode", "palette", drgnmst)
 
diff --git a/src/mame/drivers/kickgoal.c b/src/mame/drivers/kickgoal.c
index 6672a10235c..0c36714fd72 100644
--- a/src/mame/drivers/kickgoal.c
+++ b/src/mame/drivers/kickgoal.c
@@ -492,19 +492,6 @@ static ADDRESS_MAP_START( kickgoal_program_map, AS_PROGRAM, 16, kickgoal_state )
 	AM_RANGE(0xff0000, 0xffffff) AM_RAM
 ADDRESS_MAP_END
 
-/***************************** PIC16C57 Memory Map **************************/
-
-	/* $000 - 7FF  PIC16C57 Internal Program ROM. Note: code is 12bits wide */
-	/* $000 - 07F  PIC16C57 Internal Data RAM */
-
-static ADDRESS_MAP_START( kickgoal_sound_io_map, AS_IO, 8, kickgoal_state )
-	/* Unknown without the PIC dump */
-ADDRESS_MAP_END
-
-static ADDRESS_MAP_START( actionhw_io_map, AS_IO, 8, kickgoal_state )
-	/* Unknown without the PIC dump */
-ADDRESS_MAP_END
-
 
 /* INPUT ports ***************************************************************/
 
@@ -646,8 +633,6 @@ static MACHINE_CONFIG_START( kickgoal, kickgoal_state )
 	MCFG_CPU_ADD("audiocpu", PIC16C57, 12000000/4)  /* 3MHz ? */
 	MCFG_DEVICE_DISABLE()   /* Disables since the internal rom isn't dumped */
 	/* Program and Data Maps are internal to the MCU */
-	MCFG_CPU_IO_MAP(kickgoal_sound_io_map)
-
 
 	MCFG_EEPROM_SERIAL_93C46_ADD("eeprom")
 	MCFG_EEPROM_SERIAL_DATA(kickgoal_default_eeprom_type1, 128)
@@ -683,8 +668,6 @@ static MACHINE_CONFIG_START( actionhw, kickgoal_state )
 	MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_12MHz/3)    /* verified on pcb */
 	MCFG_DEVICE_DISABLE() /* Disables since the internal rom isn't dumped */
 	/* Program and Data Maps are internal to the MCU */
-	MCFG_CPU_IO_MAP(actionhw_io_map)
-
 
 	MCFG_EEPROM_SERIAL_93C46_ADD("eeprom")
 	MCFG_EEPROM_SERIAL_DATA(kickgoal_default_eeprom_type1, 128)
diff --git a/src/mame/drivers/megaphx.c b/src/mame/drivers/megaphx.c
index f565d7f36d1..e83940bf838 100644
--- a/src/mame/drivers/megaphx.c
+++ b/src/mame/drivers/megaphx.c
@@ -348,14 +348,6 @@ WRITE8_MEMBER(megaphx_state::port_c_w)
 }
 
 
-static ADDRESS_MAP_START( megaphx_pic_io_map, AS_IO, 8, megaphx_state )
-//  AM_RANGE(0x00, 0x00) AM_WRITE(playmark_oki_banking_w)
-//  AM_RANGE(0x01, 0x01) AM_READWRITE(playmark_snd_command_r, playmark_oki_w)
-//  AM_RANGE(0x02, 0x02) AM_READWRITE(playmark_snd_flag_r, playmark_snd_control_w)
-//  AM_RANGE(PIC16C5x_T0, PIC16C5x_T0) AM_READ(PIC16C5X_T0_clk_r)
-ADDRESS_MAP_END
-
-
 static MACHINE_CONFIG_START( megaphx, megaphx_state )
 
 	MCFG_CPU_ADD("maincpu", M68000, 8000000) // ??  can't read xtal due to reflections, CPU is an 8Mhz part
@@ -363,7 +355,6 @@ static MACHINE_CONFIG_START( megaphx, megaphx_state )
 
 	MCFG_CPU_ADD("pic", PIC16C54, 12000000)    /* 3MHz */
 	/* Program and Data Maps are internal to the MCU */
-	MCFG_CPU_IO_MAP(megaphx_pic_io_map)
 
 	MCFG_INDER_AUDIO_ADD("inder_sb")
 
diff --git a/src/mame/drivers/midzeus.c b/src/mame/drivers/midzeus.c
index adfdc52aa46..7468267c2dd 100644
--- a/src/mame/drivers/midzeus.c
+++ b/src/mame/drivers/midzeus.c
@@ -1114,19 +1114,15 @@ static MACHINE_CONFIG_DERIVED( mk4, midzeus )
 	MCFG_MIDWAY_IOASIC_SHUFFLE_DEFAULT(1)
 MACHINE_CONFIG_END
 
-READ8_MEMBER(midzeus_state::PIC16C5X_T0_clk_r)
+READ_LINE_MEMBER(midzeus_state::PIC16C5X_T0_clk_r)
 {
 	return 0;
 }
 
-static ADDRESS_MAP_START( pic_io_map, AS_IO, 8, midzeus_state )
-	AM_RANGE(PIC16C5x_T0, PIC16C5x_T0) AM_READ(PIC16C5X_T0_clk_r)
-ADDRESS_MAP_END
-
 
 static MACHINE_CONFIG_DERIVED( invasn, midzeus )
 	MCFG_CPU_ADD("pic", PIC16C57, 8000000)  /* ? */
-	MCFG_CPU_IO_MAP(pic_io_map)
+	MCFG_PIC16C5x_T0_CB(READLINE(midzeus_state, PIC16C5X_T0_clk_r))
 
 	MCFG_DEVICE_MODIFY("ioasic")
 	MCFG_MIDWAY_IOASIC_UPPER(468/* or 488 */)
diff --git a/src/mame/drivers/playmark.c b/src/mame/drivers/playmark.c
index 531f2518ea4..ac791c1b52f 100644
--- a/src/mame/drivers/playmark.c
+++ b/src/mame/drivers/playmark.c
@@ -272,7 +272,7 @@ WRITE8_MEMBER(playmark_state::hrdtimes_snd_control_w)
 }
 
 
-READ8_MEMBER(playmark_state::PIC16C5X_T0_clk_r)
+READ_LINE_MEMBER(playmark_state::PIC16C5X_T0_clk_r)
 {
 	return 0;
 }
@@ -425,26 +425,6 @@ static ADDRESS_MAP_START( luckboomh_main_map, AS_PROGRAM, 16, playmark_state )
 ADDRESS_MAP_END
 
 
-/***************************** PIC16C57 Memory Map **************************/
-
-	/* $000 - 7FF  PIC16C57 Internal Program ROM. Note: code is 12bits wide */
-	/* $000 - 07F  PIC16C57 Internal Data RAM */
-
-static ADDRESS_MAP_START( playmark_sound_io_map, AS_IO, 8, playmark_state )
-	AM_RANGE(0x00, 0x00) AM_WRITE(playmark_oki_banking_w)
-	AM_RANGE(0x01, 0x01) AM_READWRITE(playmark_snd_command_r, playmark_oki_w)
-	AM_RANGE(0x02, 0x02) AM_READWRITE(playmark_snd_flag_r, playmark_snd_control_w)
-	AM_RANGE(PIC16C5x_T0, PIC16C5x_T0) AM_READ(PIC16C5X_T0_clk_r)
-ADDRESS_MAP_END
-
-static ADDRESS_MAP_START( hrdtimes_sound_io_map, AS_IO, 8, playmark_state )
-	AM_RANGE(0x00, 0x00) AM_NOP     /* AM_WRITE(playmark_oki_banking_w)  Banking data output but not wired. Port 2 (Port C) is wired to the OKI banking instead */
-	AM_RANGE(0x01, 0x01) AM_READWRITE(playmark_snd_command_r, playmark_oki_w)
-	AM_RANGE(0x02, 0x02) AM_READWRITE(playmark_snd_flag_r, hrdtimes_snd_control_w)
-	AM_RANGE(PIC16C5x_T0, PIC16C5x_T0) AM_READ(PIC16C5X_T0_clk_r)
-ADDRESS_MAP_END
-
-
 static INPUT_PORTS_START( bigtwin )
 	PORT_START("SYSTEM")
 	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
@@ -1231,8 +1211,12 @@ static MACHINE_CONFIG_START( bigtwin, playmark_state )
 	MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state,  irq2_line_hold)
 
 	MCFG_CPU_ADD("audiocpu", PIC16C57, 12000000)
-	/* Program and Data Maps are internal to the MCU */
-	MCFG_CPU_IO_MAP(playmark_sound_io_map)
+	MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w))
+	MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
+	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
+	MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
+	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(playmark_state, playmark_snd_control_w))
+	MCFG_PIC16C5x_T0_CB(READLINE(playmark_state, PIC16C5X_T0_clk_r))
 
 	MCFG_MACHINE_START_OVERRIDE(playmark_state,playmark)
 	MCFG_MACHINE_RESET_OVERRIDE(playmark_state,playmark)
@@ -1267,8 +1251,12 @@ static MACHINE_CONFIG_START( bigtwinb, playmark_state )
 	MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state,  irq2_line_hold)
 
 	MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2)
-	/* Program and Data Maps are internal to the MCU */
-	MCFG_CPU_IO_MAP(playmark_sound_io_map)
+	MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w))
+	MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
+	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
+	MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
+	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(playmark_state, playmark_snd_control_w))
+	MCFG_PIC16C5x_T0_CB(READLINE(playmark_state, PIC16C5X_T0_clk_r))
 
 	MCFG_MACHINE_START_OVERRIDE(playmark_state,playmark)
 	MCFG_MACHINE_RESET_OVERRIDE(playmark_state,playmark)
@@ -1303,8 +1291,12 @@ static MACHINE_CONFIG_START( wbeachvl, playmark_state )
 	MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state,  irq2_line_hold)
 
 	MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2)    /* 12MHz with internal 4x divisor */
-	/* Program and Data Maps are internal to the MCU */
-	MCFG_CPU_IO_MAP(playmark_sound_io_map)
+	MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w))
+	MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
+	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
+	MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
+	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(playmark_state, playmark_snd_control_w))
+	MCFG_PIC16C5x_T0_CB(READLINE(playmark_state, PIC16C5X_T0_clk_r))
 	MCFG_DEVICE_DISABLE()       /* Internal code is not dumped yet */
 
 	MCFG_EEPROM_SERIAL_93C46_ADD("eeprom")
@@ -1343,8 +1335,12 @@ static MACHINE_CONFIG_START( excelsr, playmark_state )
 	MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state,  irq2_line_hold)
 
 	MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2)    /* 12MHz with internal 4x divisor */
-	/* Program and Data Maps are internal to the MCU */
-	MCFG_CPU_IO_MAP(playmark_sound_io_map)
+	MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w))
+	MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
+	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
+	MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
+	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(playmark_state, playmark_snd_control_w))
+	MCFG_PIC16C5x_T0_CB(READLINE(playmark_state, PIC16C5X_T0_clk_r))
 
 	MCFG_MACHINE_START_OVERRIDE(playmark_state,playmark)
 	MCFG_MACHINE_RESET_OVERRIDE(playmark_state,playmark)
@@ -1379,8 +1375,12 @@ static MACHINE_CONFIG_START( hrdtimes, playmark_state )
 	MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state,  irq6_line_hold)
 
 	MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2)    /* verified on pcb */
-	/* Program and Data Maps are internal to the MCU */
-	MCFG_CPU_IO_MAP(hrdtimes_sound_io_map)
+//	MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
+	MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
+	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
+	MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
+	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(playmark_state, hrdtimes_snd_control_w))
+	MCFG_PIC16C5x_T0_CB(READLINE(playmark_state, PIC16C5X_T0_clk_r))
 	MCFG_DEVICE_DISABLE()       /* Internal code is not dumped yet */
 
 	MCFG_MACHINE_START_OVERRIDE(playmark_state,playmark)
@@ -1416,8 +1416,12 @@ static MACHINE_CONFIG_START( hotmind, playmark_state )
 	MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state,  irq6_line_hold) // irq 2 and 6 point to the same location on hotmind
 
 	MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2)    /* verified on pcb */
-	/* Program and Data Maps are internal to the MCU */
-	MCFG_CPU_IO_MAP(hrdtimes_sound_io_map)
+//	MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
+	MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
+	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
+	MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
+	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(playmark_state, hrdtimes_snd_control_w))
+	MCFG_PIC16C5x_T0_CB(READLINE(playmark_state, PIC16C5X_T0_clk_r))
 
 	MCFG_EEPROM_SERIAL_93C46_ADD("eeprom")
 	MCFG_EEPROM_SERIAL_DEFAULT_VALUE(0)
@@ -1458,8 +1462,12 @@ static MACHINE_CONFIG_START( luckboomh, playmark_state )
 	MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state,  irq6_line_hold)
 
 	MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2)    /* verified on pcb */
-	/* Program and Data Maps are internal to the MCU */
-	MCFG_CPU_IO_MAP(hrdtimes_sound_io_map)
+//	MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
+	MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
+	MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
+	MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
+	MCFG_PIC16C5x_WRITE_C_CB(WRITE8(playmark_state, hrdtimes_snd_control_w))
+	MCFG_PIC16C5x_T0_CB(READLINE(playmark_state, PIC16C5X_T0_clk_r))
 
 	MCFG_NVRAM_ADD_0FILL("nvram")
 
diff --git a/src/mame/includes/drgnmst.h b/src/mame/includes/drgnmst.h
index 13214c4acd0..12e01007fff 100644
--- a/src/mame/includes/drgnmst.h
+++ b/src/mame/includes/drgnmst.h
@@ -57,7 +57,7 @@ public:
 	DECLARE_WRITE8_MEMBER(drgnmst_pcm_banksel_w);
 	DECLARE_WRITE8_MEMBER(drgnmst_oki_w);
 	DECLARE_WRITE8_MEMBER(drgnmst_snd_control_w);
-	DECLARE_READ8_MEMBER(PIC16C5X_T0_clk_r);
+	DECLARE_READ_LINE_MEMBER(PIC16C5X_T0_clk_r);
 	DECLARE_WRITE16_MEMBER(drgnmst_fg_videoram_w);
 	DECLARE_WRITE16_MEMBER(drgnmst_bg_videoram_w);
 	DECLARE_WRITE16_MEMBER(drgnmst_md_videoram_w);
diff --git a/src/mame/includes/midzeus.h b/src/mame/includes/midzeus.h
index 0ef4a7f81c2..fe30b8e4db7 100644
--- a/src/mame/includes/midzeus.h
+++ b/src/mame/includes/midzeus.h
@@ -53,7 +53,7 @@ public:
 	DECLARE_WRITE32_MEMBER(analog_w);
 	DECLARE_WRITE32_MEMBER(invasn_gun_w);
 	DECLARE_READ32_MEMBER(invasn_gun_r);
-	DECLARE_READ8_MEMBER(PIC16C5X_T0_clk_r);
+	DECLARE_READ_LINE_MEMBER(PIC16C5X_T0_clk_r);
 	DECLARE_READ32_MEMBER(zeus_r);
 	DECLARE_WRITE32_MEMBER(zeus_w);
 	DECLARE_CUSTOM_INPUT_MEMBER(custom_49way_r);
diff --git a/src/mame/includes/playmark.h b/src/mame/includes/playmark.h
index 09b50f8bba2..59c787959dd 100644
--- a/src/mame/includes/playmark.h
+++ b/src/mame/includes/playmark.h
@@ -66,7 +66,7 @@ public:
 	DECLARE_WRITE8_MEMBER(playmark_oki_w);
 	DECLARE_WRITE8_MEMBER(playmark_snd_control_w);
 	DECLARE_WRITE8_MEMBER(hrdtimes_snd_control_w);
-	DECLARE_READ8_MEMBER(PIC16C5X_T0_clk_r);
+	DECLARE_READ_LINE_MEMBER(PIC16C5X_T0_clk_r);
 	DECLARE_WRITE16_MEMBER(wbeachvl_txvideoram_w);
 	DECLARE_WRITE16_MEMBER(wbeachvl_fgvideoram_w);
 	DECLARE_WRITE16_MEMBER(wbeachvl_bgvideoram_w);