(MESS) Applix: some work (nw) we now have a cursor

This commit is contained in:
Robbbert 2013-05-22 12:47:43 +00:00
parent 87a1e31c27
commit 207bb1fc28

View File

@ -23,8 +23,10 @@
#include "emu.h" #include "emu.h"
#include "cpu/m68000/m68000.h" #include "cpu/m68000/m68000.h"
#include "cpu/z80/z80.h"
#include "video/mc6845.h" #include "video/mc6845.h"
#include "machine/6522via.h" #include "machine/6522via.h"
#include "machine/wd_fdc.h"
class applix_state : public driver_device class applix_state : public driver_device
@ -35,6 +37,7 @@ public:
m_maincpu(*this, "maincpu"), m_maincpu(*this, "maincpu"),
m_crtc(*this, "crtc"), m_crtc(*this, "crtc"),
m_via(*this, "via6522"), m_via(*this, "via6522"),
// m_fdc(*this, "wd1772"),
m_base(*this, "base"), m_base(*this, "base"),
m_expansion(*this, "expansion"){ } m_expansion(*this, "expansion"){ }
@ -50,18 +53,44 @@ public:
DECLARE_WRITE8_MEMBER(applix_pa_w); DECLARE_WRITE8_MEMBER(applix_pa_w);
DECLARE_WRITE8_MEMBER(applix_pb_w); DECLARE_WRITE8_MEMBER(applix_pb_w);
DECLARE_WRITE_LINE_MEMBER(vsync_w); DECLARE_WRITE_LINE_MEMBER(vsync_w);
DECLARE_READ8_MEMBER(port00_r);
DECLARE_READ8_MEMBER(port08_r);
DECLARE_READ8_MEMBER(port10_r);
DECLARE_READ8_MEMBER(port18_r);
DECLARE_READ8_MEMBER(port20_r);
DECLARE_READ8_MEMBER(port60_r);
DECLARE_WRITE8_MEMBER(port08_w);
DECLARE_WRITE8_MEMBER(port10_w);
DECLARE_WRITE8_MEMBER(port18_w);
DECLARE_WRITE8_MEMBER(port20_w);
DECLARE_WRITE8_MEMBER(port60_w);
DECLARE_READ16_MEMBER(fdc_data_r);
DECLARE_READ16_MEMBER(fdc_stat_r);
DECLARE_WRITE16_MEMBER(fdc_data_w);
DECLARE_WRITE16_MEMBER(fdc_cmd_w);
// DECLARE_FLOPPY_FORMATS( floppy_formats );
// void fdc_intrq_w(bool state);
// void fdc_drq_w(bool state);
UINT8 m_pa; UINT8 m_pa;
UINT8 m_pb; UINT8 m_pb;
UINT8 m_analog_latch; UINT8 m_analog_latch;
UINT8 m_dac_latch; UINT8 m_dac_latch;
UINT8 m_video_latch; UINT8 m_video_latch;
UINT8 m_palette_latch[4]; UINT8 m_palette_latch[4];
UINT8 m_port08;
UINT8 m_data_to_fdc;
UINT8 m_data_from_fdc;
bool m_data;
bool m_data_or_cmd;
bool m_buffer_empty;
bool m_fdc_cmd;
virtual void machine_reset(); virtual void machine_reset();
virtual void video_start(); virtual void video_start();
virtual void palette_init(); virtual void palette_init();
required_device<cpu_device> m_maincpu; required_device<cpu_device> m_maincpu;
required_device<mc6845_device> m_crtc; required_device<mc6845_device> m_crtc;
required_device<via6522_device> m_via; required_device<via6522_device> m_via;
// required_device<wd1772_t> m_fdc;
required_shared_ptr<UINT16> m_base; required_shared_ptr<UINT16> m_base;
required_shared_ptr<UINT16> m_expansion; required_shared_ptr<UINT16> m_expansion;
}; };
@ -141,6 +170,112 @@ WRITE8_MEMBER( applix_state::applix_pb_w )
m_pb = data; m_pb = data;
} }
/*
d0 = H if 68000 sent a command
d1 = H if 68000 sent a byte
d2 = H if 68000 has read last byte
d3 = test switch
*/
READ8_MEMBER( applix_state::port00_r )
{
return m_data_or_cmd | (m_data << 1) | (m_buffer_empty << 2) | ioport("FDC")->read();
}
/*
d0 = /RDY
d1 = /DISC CHANGE
d2 = SIDE
d3 = DS0
d4 = DS1
d5 = MOTORON
d6 = BANK
d7 = MAP
*/
READ8_MEMBER( applix_state::port08_r )
{
return m_port08 | 3;
}
/*
d0 = /INUSE
d1 = /EJECT
d2-7 same as for port08_r
*/
WRITE8_MEMBER( applix_state::port08_w )
{
m_port08 = data;
}
READ8_MEMBER( applix_state::port10_r )
{
return 0;
}
WRITE8_MEMBER( applix_state::port10_w )
{
}
READ8_MEMBER( applix_state::port18_r )
{
m_data = 0;
return m_data_to_fdc;
}
WRITE8_MEMBER( applix_state::port18_w )
{
m_data_from_fdc = data;
m_buffer_empty = 0;
m_fdc_cmd = BIT(offset, 2);
}
READ8_MEMBER( applix_state::port20_r )
{
return 0;
}
WRITE8_MEMBER( applix_state::port20_w )
{
}
READ8_MEMBER( applix_state::port60_r )
{
return 0;
}
WRITE8_MEMBER( applix_state::port60_w )
{
}
READ16_MEMBER( applix_state::fdc_stat_r )
{
switch (offset)
{
case 0: return m_buffer_empty;
case 1: return m_data;
default: return m_fdc_cmd; // case 2
}
}
READ16_MEMBER( applix_state::fdc_data_r )
{
m_buffer_empty = 1;
return m_data_from_fdc;
}
WRITE16_MEMBER( applix_state::fdc_data_w )
{
m_data_to_fdc = data;
m_data = 1;
m_data_or_cmd = 0;
}
WRITE16_MEMBER( applix_state::fdc_cmd_w )
{
m_data_to_fdc = data;
m_data = 1;
m_data_or_cmd = 1;
}
static ADDRESS_MAP_START(applix_mem, AS_PROGRAM, 16, applix_state) static ADDRESS_MAP_START(applix_mem, AS_PROGRAM, 16, applix_state)
ADDRESS_MAP_UNMAP_HIGH ADDRESS_MAP_UNMAP_HIGH
ADDRESS_MAP_GLOBAL_MASK(0xffffff) ADDRESS_MAP_GLOBAL_MASK(0xffffff)
@ -156,12 +291,34 @@ static ADDRESS_MAP_START(applix_mem, AS_PROGRAM, 16, applix_state)
AM_RANGE(0x700100, 0x70011f) AM_MIRROR(0x60) AM_DEVREADWRITE8("via6522", via6522_device, read, write, 0xff00) AM_RANGE(0x700100, 0x70011f) AM_MIRROR(0x60) AM_DEVREADWRITE8("via6522", via6522_device, read, write, 0xff00)
AM_RANGE(0x700180, 0x700181) AM_MIRROR(0x7c) AM_WRITE(applix_index_w) AM_RANGE(0x700180, 0x700181) AM_MIRROR(0x7c) AM_WRITE(applix_index_w)
AM_RANGE(0x700182, 0x700183) AM_MIRROR(0x7c) AM_WRITE(applix_register_w) AM_RANGE(0x700182, 0x700183) AM_MIRROR(0x7c) AM_WRITE(applix_register_w)
AM_RANGE(0xffffc0, 0xffffc1) AM_READWRITE(fdc_data_r,fdc_data_w)
//AM_RANGE(0xffffc2, 0xffffc3) AM_READWRITE(fdc_int_r,fdc_int_w)
AM_RANGE(0xffffc8, 0xffffcd) AM_READ(fdc_stat_r)
AM_RANGE(0xffffd0, 0xffffd1) AM_WRITE(fdc_cmd_w)
//600000, 6FFFFF io ports and latches //600000, 6FFFFF io ports and latches
//700000, 7FFFFF peripheral chips and devices //700000, 7FFFFF peripheral chips and devices
//800000, FFC000 optional roms //800000, FFC000 optional roms
//FFFFC0, FFFFFF disk controller board //FFFFC0, FFFFFF disk controller board
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START( subcpu_mem, AS_PROGRAM, 8, applix_state )
AM_RANGE(0x0000, 0x5fff) AM_ROM
AM_RANGE(0x6000, 0x7fff) AM_RAM
// AM_RANGE(0x8000, 0xffff) AM_RAMBANK("bank1")
ADDRESS_MAP_END
static ADDRESS_MAP_START( subcpu_io, AS_IO, 8, applix_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x07) AM_READ(port00_r) //PORTR
AM_RANGE(0x08, 0x0f) AM_READWRITE(port08_r,port08_w) //Disk select
AM_RANGE(0x10, 0x17) AM_READWRITE(port10_r,port10_w) //IRQ
AM_RANGE(0x18, 0x1f) AM_READWRITE(port18_r,port18_w) //data&command
AM_RANGE(0x20, 0x23) AM_MIRROR(0x1c) AM_READWRITE(port20_r,port20_w) //SCSI
AM_RANGE(0x40, 0x43) AM_MIRROR(0x1c) AM_DEVREADWRITE("wd1772", wd1772_t, read, write) //FDC
AM_RANGE(0x60, 0x63) AM_MIRROR(0x1c) AM_READWRITE(port60_r,port60_w) //Z80SCC
ADDRESS_MAP_END
// io priorities: // io priorities:
// 4 cassette // 4 cassette
// 3 scc // 3 scc
@ -183,6 +340,12 @@ static INPUT_PORTS_START( applix )
PORT_DIPNAME( 0x80, 0x00, "Switch 3") PORT_DIPLOCATION("SW2:4") PORT_DIPNAME( 0x80, 0x00, "Switch 3") PORT_DIPLOCATION("SW2:4")
PORT_DIPSETTING( 0x80, DEF_STR(Off)) PORT_DIPSETTING( 0x80, DEF_STR(Off))
PORT_DIPSETTING( 0x00, DEF_STR(On)) PORT_DIPSETTING( 0x00, DEF_STR(On))
PORT_START("FDC")
PORT_BIT( 0xf7, 0, IPT_UNUSED )
PORT_DIPNAME( 0x08, 0x08, "FDC Test") PORT_DIPLOCATION("SW3:1")
PORT_DIPSETTING( 0x08, DEF_STR(Off))
PORT_DIPSETTING( 0x00, DEF_STR(On))
INPUT_PORTS_END INPUT_PORTS_END
@ -193,6 +356,14 @@ void applix_state::machine_reset()
m_maincpu->reset(); m_maincpu->reset();
} }
//FLOPPY_FORMATS_MEMBER( mirage_state::floppy_formats )
// FLOPPY_ESQ8IMG_FORMAT
//FLOPPY_FORMATS_END
//static SLOT_INTERFACE_START( ensoniq_floppies )
// SLOT_INTERFACE( "35dd", FLOPPY_35_DD )
//SLOT_INTERFACE_END
void applix_state::palette_init() void applix_state::palette_init()
{ // shades need to be verified - the names on the right are from the manual { // shades need to be verified - the names on the right are from the manual
@ -308,6 +479,9 @@ static MACHINE_CONFIG_START( applix, applix_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", M68000, 7500000) MCFG_CPU_ADD("maincpu", M68000, 7500000)
MCFG_CPU_PROGRAM_MAP(applix_mem) MCFG_CPU_PROGRAM_MAP(applix_mem)
MCFG_CPU_ADD("subcpu", Z80, XTAL_16MHz / 2) // Z80H
MCFG_CPU_PROGRAM_MAP(subcpu_mem)
MCFG_CPU_IO_MAP(subcpu_io)
/* video hardware */ /* video hardware */
MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_ADD("screen", RASTER)
@ -321,6 +495,8 @@ static MACHINE_CONFIG_START( applix, applix_state )
/* Devices */ /* Devices */
MCFG_MC6845_ADD("crtc", MC6845, 1875000, applix_crtc) // 6545 MCFG_MC6845_ADD("crtc", MC6845, 1875000, applix_crtc) // 6545
MCFG_VIA6522_ADD("via6522", 0, applix_via) MCFG_VIA6522_ADD("via6522", 0, applix_via)
MCFG_WD1772x_ADD("wd1772", XTAL_16MHz / 2) //connected to Z80H clock pin
// MCFG_FLOPPY_DRIVE_ADD("wd1772:0", applix_floppies, "35dd", 0, applix_state::floppy_formats)
MACHINE_CONFIG_END MACHINE_CONFIG_END
/* ROM definition */ /* ROM definition */
@ -333,13 +509,29 @@ ROM_START( applix )
ROMX_LOAD( "1616oshv.044", 0x00000, 0x10000, CRC(4a1a90d3) SHA1(4df504bbf6fc5dad76c29e9657bfa556500420a6), ROM_SKIP(1) | ROM_BIOS(2) ) ROMX_LOAD( "1616oshv.044", 0x00000, 0x10000, CRC(4a1a90d3) SHA1(4df504bbf6fc5dad76c29e9657bfa556500420a6), ROM_SKIP(1) | ROM_BIOS(2) )
ROMX_LOAD( "1616oslv.044", 0x00001, 0x10000, CRC(ef619994) SHA1(ff16fe9e2c99a1ffc855baf89278a97a2a2e881a), ROM_SKIP(1) | ROM_BIOS(2) ) ROMX_LOAD( "1616oslv.044", 0x00001, 0x10000, CRC(ef619994) SHA1(ff16fe9e2c99a1ffc855baf89278a97a2a2e881a), ROM_SKIP(1) | ROM_BIOS(2) )
ROM_REGION(0x10000, "subcpu", 0) ROM_REGION(0x18000, "subcpu", 0)
ROM_LOAD( "1616ssdv.022", 0x0000, 0x8000, CRC(6d8e413a) SHA1(fc27d92c34f231345a387b06670f36f8c1705856) ) ROM_LOAD( "1616ssdv.022", 0x0000, 0x8000, CRC(6d8e413a) SHA1(fc27d92c34f231345a387b06670f36f8c1705856) )
ROM_REGION(0x20000, "user1", 0) ROM_REGION(0x20000, "user1", 0)
ROM_LOAD( "1616osv.045", 0x00000, 0x20000, CRC(b9f75432) SHA1(278964e2a02b1fe26ff34f09dc040e03c1d81a6d) ) ROM_LOAD( "1616osv.045", 0x00000, 0x20000, CRC(b9f75432) SHA1(278964e2a02b1fe26ff34f09dc040e03c1d81a6d) )
ROM_END ROM_END
#if 0
DRIVER_INIT_MEMBER(applix_state, applix)
{
floppy_connector *con = machine().device<floppy_connector>("wd1772:0");
floppy_image_device *floppy = con ? con->get_device() : 0;
if (floppy)
{
m_fdc->set_floppy(floppy);
m_fdc->setup_intrq_cb(wd1772_t::line_cb(FUNC(mirage_state::fdc_intrq_w), this));
m_fdc->setup_drq_cb(wd1772_t::line_cb(FUNC(mirage_state::fdc_drq_w), this));
floppy->ss_w(0);
}
}
#endif
/* Driver */ /* Driver */
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */ /* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */