mirror of
https://github.com/holub/mame
synced 2025-05-09 15:51:48 +03:00
SegaCD compatibility improvements (MESS side) (no whatsnew)
This commit is contained in:
Scott Stone
parent
c53aac95f3
commit
209e4d8ade
@ -341,7 +341,7 @@ static UINT16* _32x_palette_lookup;
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/* SegaCD! */
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static cpu_device *_segacd_68k_cpu;
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static emu_timer *segacd_gfx_conversion_timer;
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static emu_timer *segacd_dmna_ret_timer;
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//static emu_timer *segacd_dmna_ret_timer;
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static emu_timer *segacd_irq3_timer;
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static emu_timer *segacd_hock_timer;
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static UINT8 hock_cmd;
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@ -397,6 +397,8 @@ static UINT8 segacd_font_color;
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static UINT16* segacd_font_bits;
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static UINT16 scd_rammode;
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static UINT32 scd_mode_dmna_ret_flags ;
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static void segacd_mark_tiles_dirty(running_machine* machine, int offset);
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@ -3795,15 +3797,15 @@ ADDRESS_MAP_END
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*************************************************************************************************/
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static UINT8 segacd_ram_writeprotect_bits;
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int segacd_ram_mode;
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static int segacd_ram_mode_old;
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//int segacd_ram_mode;
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//static int segacd_ram_mode_old;
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//static int segacd_maincpu_has_ram_access = 0;
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static int segacd_4meg_prgbank = 0; // which bank the MainCPU can see of the SubCPU PrgRAM
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static int segacd_memory_priority_mode = 0;
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static int segacd_stampsize;
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int segacd_dmna = 0;
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int segacd_ret = 0;
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//int segacd_dmna = 0;
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//int segacd_ret = 0;
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#define READ_MAIN (0x0200)
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#define READ_SUB (0x0300)
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@ -3939,7 +3941,7 @@ UINT16* segacd_4meg_prgram; // pointer to SubCPU PrgRAM
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UINT16* segacd_dataram;
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#define RAM_MODE_2MEG (0)
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#define RAM_MODE_1MEG (1)
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#define RAM_MODE_1MEG (2)
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// 1meg / 2meg swap should actually be an interleaved swap, not half/half of the ram?
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UINT16 segacd_1meg_mode_word_read(int offset, UINT16 mem_mask)
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@ -4498,10 +4500,10 @@ void CDC_Do_DMA(running_machine* machine, int rate)
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{
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dest = (UINT8*)segacd_dataram;
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if (segacd_ram_mode)
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if ((scd_rammode&2))
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{
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dstoffset &= 0x1ffff;
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if (!(segacd_ret & 1)) dest += 0x20000;
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if (!(scd_rammode & 1)) dest += 0x20000;
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}
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else
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{
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@ -4532,7 +4534,7 @@ void CDC_Do_DMA(running_machine* machine, int rate)
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if (destination==DMA_WRAM)
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{
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if (segacd_ram_mode==RAM_MODE_2MEG)
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if ((scd_rammode&2)==RAM_MODE_2MEG)
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segacd_mark_tiles_dirty(space->machine, dstoffset/2);
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}
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@ -4831,47 +4833,20 @@ static READ16_HANDLER( scd_a12000_halt_reset_r )
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// so probably don't change instantly...
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//
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static TIMER_CALLBACK( segacd_dmna_ret_timer_callback )
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{
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// this is the initial state, and the state after changing modes?
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if ((segacd_dmna==0) && (segacd_ret ==0))
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{
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//printf("aaa %d %d\n", segacd_dmna, segacd_ret);
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segacd_dmna = 0;
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segacd_ret = 1;
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//printf("bbb %d %d\n", segacd_dmna, segacd_ret);
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}
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else if ((segacd_dmna==1) && (segacd_ret == 1))
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{
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//printf("aaa %d %d\n", segacd_dmna, segacd_ret);
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segacd_dmna = 1;
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segacd_ret = 0;
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//printf("bbb %d %d\n", segacd_dmna, segacd_ret);
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}
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else if ((segacd_dmna==1) && (segacd_ret == 0))
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{
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//printf("aaa %d %d\n", segacd_dmna, segacd_ret);
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segacd_dmna = 0;
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segacd_ret = 1;
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//printf("bbb %d %d\n", segacd_dmna, segacd_ret);
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}
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else
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{
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printf("huh? %d %d\n", segacd_dmna, segacd_ret);
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}
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}
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static READ16_HANDLER( scd_a12002_memory_mode_r )
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{
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space->machine->scheduler().synchronize();
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int temp = scd_rammode;
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int temp2 = 0;
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temp2 |= (scd_mode_dmna_ret_flags>>(temp*4))&0x7;
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return (segacd_ram_writeprotect_bits << 8) |
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(segacd_4meg_prgbank << 6) |
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(segacd_ram_mode << 2) |
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((segacd_dmna) << 1) |
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((segacd_ret) << 0);
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temp2;
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}
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@ -4899,39 +4874,26 @@ static WRITE8_HANDLER( scd_a12002_memory_mode_w_8_15 )
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static WRITE8_HANDLER( scd_a12002_memory_mode_w_0_7 )
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{
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space->machine->scheduler().synchronize();
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//printf("scd_a12002_memory_mode_w_0_7 %04x\n",data);
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segacd_4meg_prgbank = (data&0x00c0)>>6;
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#if 1
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//if (data&0x0001) printf("ret bit set (invalid? can't set from main68k?)\n");
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if (data&0x0002)
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{
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//printf("dmna set (swap requested)\n"); // give ram to sub?
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// this should take some time?
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//segacd_ret = 1;
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//printf("main cpu dmna set dmna: %d ret: %d\n", segacd_dmna, segacd_ret);
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if (segacd_ram_mode==RAM_MODE_2MEG)
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if (scd_rammode&0x2)
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{ // ==0x2 (1 meg mode)
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if (!(data&2)) // check DMNA bit
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{
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if (!segacd_dmna_ret_timer->enabled())
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{
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if (!segacd_dmna)
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{
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//printf("main dmna\n");
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segacd_dmna = 1;
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segacd_dmna_ret_timer->adjust(attotime::from_usec(1));
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}
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}
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}
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else
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{
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printf("dmna bit in mode 1\n");
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scd_mode_dmna_ret_flags |= 0x2200;
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}
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}
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else // == 0x0 (2 meg mode)
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{
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if (data&2) // check DMNA bit
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{
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scd_rammode = 1;
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}
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}
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#endif
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}
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@ -4948,18 +4910,19 @@ static WRITE16_HANDLER( scd_a12002_memory_mode_w )
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// can't read the bank?
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static READ16_HANDLER( segacd_sub_memory_mode_r )
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{
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space->machine->scheduler().synchronize();
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int temp = scd_rammode;
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int temp2 = 0;
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temp2 |= (scd_mode_dmna_ret_flags>>(temp*4))&0x7;
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return (segacd_ram_writeprotect_bits << 8) |
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/*(segacd_4meg_prgbank << 6) | */
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(segacd_memory_priority_mode << 3) |
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(segacd_ram_mode << 2) |
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((segacd_dmna) << 1) |
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((segacd_ret) << 0);
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temp2;
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}
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@ -4968,85 +4931,65 @@ WRITE8_HANDLER( segacd_sub_memory_mode_w_8_15 )
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/* setting write protect bits from sub-cpu has no effect? */
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}
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WRITE8_HANDLER( segacd_sub_memory_mode_w_0_7 )
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{
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space->machine->scheduler().synchronize();
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segacd_memory_priority_mode = (data&0x0018)>>3;
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// If the mode bit is 0 then we're requesting a change to
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// 2Meg mode?
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#if 1
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if (data&0x0001)
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{
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//printf("ret bit set\n");
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//segacd_dmna = 0;
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//printf("segacd_sub_memory_mode_w_0_7 %04x\n",data);
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if (!(data&4)) // check ram mode bit
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{ // == 0x0 - 2 meg mode
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scd_mode_dmna_ret_flags &= 0xddff;
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//printf("sub cpu ret set dmna: %d ret: %d\n", segacd_dmna, segacd_ret);
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if (segacd_ram_mode==RAM_MODE_2MEG)
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if (data&1) // check RET
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{
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if (!segacd_dmna_ret_timer->enabled())
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{
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if (segacd_dmna)
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{
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// printf("sub ret\n");
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// segacd_ret = 1;
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// segacd_dmna = 0;
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segacd_dmna_ret_timer->adjust(attotime::from_usec(1));
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}
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}
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// If RET is set and the Mode bit in the write is set to 2M then we want to change to 2M mode
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// If we're already in 2M mode it has no effect
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scd_rammode = 0;
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}
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else
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{
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// in mode 1 this changes the word ram 1 to main cpu and word ram 0 to sub cpu?
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// but should be proceeded by a dmna request? is this only valid if dmna has been
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// set to 1 by the main CPU first?
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//printf("ret bit in mode 1\n");
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segacd_ret = 1;
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// == 0x4 - 1 meg mode
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int temp = scd_rammode;
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if (temp&2) // check ram mode
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{ // == 0x2 - 1 meg mode
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scd_mode_dmna_ret_flags &= 0xffde;
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scd_rammode = temp &1;
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}
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}
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}
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else
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{
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// in mode 1 this changes the word ram 0 to main cpu and word ram 1 to sub cpu?
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// but should be proceeded by a dmna request? is this only valid if dmna has been
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// set to 1 by the main CPU first?
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if (segacd_ram_mode==RAM_MODE_1MEG)
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{
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segacd_ret = 0;
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}
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}
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{ // == 0x4 - 1 meg mode
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data &=1;
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int temp = data;
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int scd_rammode_old = scd_rammode;
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data |=2;
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temp ^= scd_rammode_old;
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scd_rammode = data;
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//if (data&0x0002) printf("dmna set (swap requested) (invalid, can't be set from sub68k?\n");
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//if (data&0x0004)
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{
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segacd_ram_mode = (data&0x0004)>>2;
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if (segacd_ram_mode!=segacd_ram_mode_old)
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{
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printf("mode set %d", segacd_ram_mode);
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if (segacd_ram_mode == RAM_MODE_1MEG) printf("(1 meg mode)\n");
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else printf("(2 meg mode)\n");
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segacd_ram_mode_old = segacd_ram_mode;
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if (segacd_ram_mode==RAM_MODE_2MEG)
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if (scd_rammode_old & 2)
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{ // == 0x2 - already in 1 meg mode
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if (temp & 1) // ret bit
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{
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// reset it flags etc.?
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segacd_ret = 0;
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segacd_dmna = 0;
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segacd_dmna_ret_timer->adjust(attotime::from_usec(100));
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}
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else
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{
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segacd_ret = 0;
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segacd_dmna = 0;
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scd_mode_dmna_ret_flags &= 0xddff;
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}
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}
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else
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{ // == 0x0 - currently in 2 meg mode
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scd_mode_dmna_ret_flags &= 0xddff;
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}
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}
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#endif
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}
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static WRITE16_HANDLER( segacd_sub_memory_mode_w )
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@ -5233,10 +5176,10 @@ static READ16_HANDLER( segacd_cdc_data_r )
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static READ16_HANDLER( segacd_main_dataram_part1_r )
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{
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if (segacd_ram_mode==RAM_MODE_2MEG)
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if ((scd_rammode&2)==RAM_MODE_2MEG)
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{
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// is this correct?
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if (!segacd_dmna)
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if (!(scd_rammode&1))
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{
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//printf("segacd_main_dataram_part1_r in mode 0 %08x %04x\n", offset*2, segacd_dataram[offset]);
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@ -5250,7 +5193,7 @@ static READ16_HANDLER( segacd_main_dataram_part1_r )
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}
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}
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else if (segacd_ram_mode==RAM_MODE_1MEG)
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else if ((scd_rammode&2)==RAM_MODE_1MEG)
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{
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if (offset<0x20000/2)
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@ -5259,7 +5202,7 @@ static READ16_HANDLER( segacd_main_dataram_part1_r )
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//printf("Unspported: segacd_main_dataram_part1_r (word RAM) in mode 1\n");
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// ret bit set by sub cpu determines which half of WorkRAM we have access to?
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if (segacd_ret)
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if (scd_rammode&1)
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{
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return segacd_1meg_mode_word_read(offset+0x20000/2, mem_mask);
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}
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@ -5283,15 +5226,16 @@ static READ16_HANDLER( segacd_main_dataram_part1_r )
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else /* 0x3c000 - 0x3dfff and 0x3e000 - 0x3ffff */ // 512x32 bitmap (x2) -> tiles
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offset = BITSWAP24(offset,23,22,21,20,19,18,17,16,15,14,13,12,5,4,3,2,1,11,10,9,8,7,6,0);
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// do we care about the ret bit?? HOTA is missing some startup screens...
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//if (!segacd_ret)
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//{
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// return segacd_dataram[offset+0x20000/2];
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//}
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//else
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offset &=0xffff;
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// HOTA cares about this
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if (!(scd_rammode&1))
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{
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return segacd_1meg_mode_word_read(offset+0x00000/2, mem_mask);
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}
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else
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{
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return segacd_1meg_mode_word_read(offset+0x20000/2, mem_mask);
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}
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}
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}
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@ -5300,10 +5244,10 @@ static READ16_HANDLER( segacd_main_dataram_part1_r )
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static WRITE16_HANDLER( segacd_main_dataram_part1_w )
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{
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if (segacd_ram_mode==RAM_MODE_2MEG)
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if ((scd_rammode&2)==RAM_MODE_2MEG)
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{
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// is this correct?
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if (!segacd_dmna)
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if (!(scd_rammode&1))
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{
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COMBINE_DATA(&segacd_dataram[offset]);
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segacd_mark_tiles_dirty(space->machine, offset);
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@ -5314,7 +5258,7 @@ static WRITE16_HANDLER( segacd_main_dataram_part1_w )
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}
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}
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else if (segacd_ram_mode==RAM_MODE_1MEG)
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else if ((scd_rammode&2)==RAM_MODE_1MEG)
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{
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if (offset<0x20000/2)
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{
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@ -5322,7 +5266,7 @@ static WRITE16_HANDLER( segacd_main_dataram_part1_w )
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// wordram accees
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// ret bit set by sub cpu determines which half of WorkRAM we have access to?
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if (segacd_ret)
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if (scd_rammode&1)
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{
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segacd_1meg_mode_word_write(offset+0x20000/2, data, mem_mask);
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}
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@ -5333,7 +5277,7 @@ static WRITE16_HANDLER( segacd_main_dataram_part1_w )
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}
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else
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{
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printf("Unspported: segacd_main_dataram_part1_w (Cell rearranged RAM) in mode 1 (illega?)\n"); // is this legal??
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// printf("Unspported: segacd_main_dataram_part1_w (Cell rearranged RAM) in mode 1 (illega?)\n"); // is this legal??
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}
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}
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}
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@ -5913,7 +5857,7 @@ void segacd_init_main_cpu( running_machine* machine )
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segacd_gfx_conversion_timer = machine->scheduler().timer_alloc(FUNC(segacd_gfx_conversion_timer_callback));
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segacd_gfx_conversion_timer->adjust(attotime::never);
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segacd_dmna_ret_timer = machine->scheduler().timer_alloc(FUNC(segacd_dmna_ret_timer_callback));
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//segacd_dmna_ret_timer = machine->scheduler().timer_alloc(FUNC(segacd_dmna_ret_timer_callback));
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segacd_gfx_conversion_timer->adjust(attotime::never);
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segacd_hock_timer = machine->scheduler().timer_alloc(FUNC(segacd_access_timer_callback));
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@ -5961,6 +5905,9 @@ static TIMER_DEVICE_CALLBACK( scd_dma_timer_callback )
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if (sega_cd_connected)
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CDC_Do_DMA(timer.machine, RATE);
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// timed reset of flags
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scd_mode_dmna_ret_flags |= 0x0021;
|
||||
|
||||
scd_dma_timer->adjust(attotime::from_hz(megadriv_framerate) / megadrive_total_scanlines);
|
||||
}
|
||||
|
||||
@ -5996,13 +5943,9 @@ static MACHINE_RESET( segacd )
|
||||
if (segacd.cd)
|
||||
printf("cd found\n");
|
||||
|
||||
segacd_dmna = 0;
|
||||
segacd_ret = 0;
|
||||
scd_rammode = 0;
|
||||
scd_mode_dmna_ret_flags = 0x5421;
|
||||
|
||||
segacd_ram_mode = 0;
|
||||
segacd_ram_mode_old = 0;
|
||||
|
||||
segacd_dmna_ret_timer->adjust(attotime::zero);
|
||||
|
||||
hock_cmd = 0;
|
||||
stopwatch_timer = machine->device<timer_device>("sw_timer");
|
||||
@ -6057,10 +6000,10 @@ static WRITE16_HANDLER( segacd_sub_led_ready_w )
|
||||
|
||||
static READ16_HANDLER( segacd_sub_dataram_part1_r )
|
||||
{
|
||||
if (segacd_ram_mode==RAM_MODE_2MEG)
|
||||
if ((scd_rammode&2)==RAM_MODE_2MEG)
|
||||
{
|
||||
// is this correct?
|
||||
if (segacd_dmna)
|
||||
if (scd_rammode&1)
|
||||
return segacd_dataram[offset];
|
||||
else
|
||||
{
|
||||
@ -6068,7 +6011,7 @@ static READ16_HANDLER( segacd_sub_dataram_part1_r )
|
||||
return 0x0000;
|
||||
}
|
||||
}
|
||||
else if (segacd_ram_mode==RAM_MODE_1MEG)
|
||||
else if ((scd_rammode&2)==RAM_MODE_1MEG)
|
||||
{
|
||||
printf("Unspported: segacd_sub_dataram_part1_r in mode 1 (Word RAM Expander - 1 Byte Per Pixel)\n");
|
||||
return 0x0000;
|
||||
@ -6079,10 +6022,10 @@ static READ16_HANDLER( segacd_sub_dataram_part1_r )
|
||||
|
||||
static WRITE16_HANDLER( segacd_sub_dataram_part1_w )
|
||||
{
|
||||
if (segacd_ram_mode==RAM_MODE_2MEG)
|
||||
if ((scd_rammode&2)==RAM_MODE_2MEG)
|
||||
{
|
||||
// is this correct?
|
||||
if (segacd_dmna)
|
||||
if (scd_rammode&1)
|
||||
{
|
||||
COMBINE_DATA(&segacd_dataram[offset]);
|
||||
segacd_mark_tiles_dirty(space->machine, offset);
|
||||
@ -6092,7 +6035,7 @@ static WRITE16_HANDLER( segacd_sub_dataram_part1_w )
|
||||
printf("Illegal: segacd_sub_dataram_part1_w in mode 0 without permission\n");
|
||||
}
|
||||
}
|
||||
else if (segacd_ram_mode==RAM_MODE_1MEG)
|
||||
else if ((scd_rammode&2)==RAM_MODE_1MEG)
|
||||
{
|
||||
printf("Unspported: segacd_sub_dataram_part1_w in mode 1 (Word RAM Expander - 1 Byte Per Pixel)\n");
|
||||
}
|
||||
@ -6100,22 +6043,22 @@ static WRITE16_HANDLER( segacd_sub_dataram_part1_w )
|
||||
|
||||
static READ16_HANDLER( segacd_sub_dataram_part2_r )
|
||||
{
|
||||
if (segacd_ram_mode==RAM_MODE_2MEG)
|
||||
if ((scd_rammode&2)==RAM_MODE_2MEG)
|
||||
{
|
||||
printf("ILLEGAL segacd_sub_dataram_part2_r in mode 0\n"); // not mapped to anything in mode 0
|
||||
return 0x0000;
|
||||
}
|
||||
else if (segacd_ram_mode==RAM_MODE_1MEG)
|
||||
else if ((scd_rammode&2)==RAM_MODE_1MEG)
|
||||
{
|
||||
//printf("Unsupported: segacd_sub_dataram_part2_r in mode 1 (Word RAM)\n");
|
||||
// ret bit set by sub cpu determines which half of WorkRAM we have access to?
|
||||
if (!segacd_ret)
|
||||
if (scd_rammode&1)
|
||||
{
|
||||
return segacd_1meg_mode_word_read(offset+0x20000/2, mem_mask);
|
||||
return segacd_1meg_mode_word_read(offset+0x00000/2, mem_mask);
|
||||
}
|
||||
else
|
||||
{
|
||||
return segacd_1meg_mode_word_read(offset+0x00000/2, mem_mask);
|
||||
return segacd_1meg_mode_word_read(offset+0x20000/2, mem_mask);
|
||||
}
|
||||
|
||||
}
|
||||
@ -6125,21 +6068,21 @@ static READ16_HANDLER( segacd_sub_dataram_part2_r )
|
||||
|
||||
static WRITE16_HANDLER( segacd_sub_dataram_part2_w )
|
||||
{
|
||||
if (segacd_ram_mode==RAM_MODE_2MEG)
|
||||
if ((scd_rammode&2)==RAM_MODE_2MEG)
|
||||
{
|
||||
printf("ILLEGAL segacd_sub_dataram_part2_w in mode 0\n"); // not mapepd to anything in mode 0
|
||||
printf("ILLEGAL segacd_sub_dataram_part2_w in mode 0\n"); // not mapped to anything in mode 0
|
||||
}
|
||||
else if (segacd_ram_mode==RAM_MODE_1MEG)
|
||||
else if ((scd_rammode&2)==RAM_MODE_1MEG)
|
||||
{
|
||||
//printf("Unsupported: segacd_sub_dataram_part2_w in mode 1 (Word RAM)\n");
|
||||
// ret bit set by sub cpu determines which half of WorkRAM we have access to?
|
||||
if (!segacd_ret)
|
||||
if (scd_rammode&1)
|
||||
{
|
||||
segacd_1meg_mode_word_write(offset+0x20000/2, data, mem_mask);
|
||||
segacd_1meg_mode_word_write(offset+0x00000/2, data, mem_mask);
|
||||
}
|
||||
else
|
||||
{
|
||||
segacd_1meg_mode_word_write(offset+0x00000/2, data, mem_mask);
|
||||
segacd_1meg_mode_word_write(offset+0x20000/2, data, mem_mask);
|
||||
}
|
||||
|
||||
}
|
||||
@ -6354,7 +6297,7 @@ INLINE void write_pixel_to_imagebuffer( running_machine* machine, UINT32 pix, in
|
||||
// this triggers the conversion operation, which will cause an IRQ1 when finished
|
||||
WRITE16_HANDLER( segacd_trace_vector_base_address_w )
|
||||
{
|
||||
if (segacd_ram_mode==RAM_MODE_1MEG)
|
||||
if ((scd_rammode&2)==RAM_MODE_1MEG)
|
||||
{
|
||||
printf("ILLEGAL: segacd_trace_vector_base_address_w %04x %04x in mode 1!\n",data,mem_mask);
|
||||
}
|
||||
@ -9649,7 +9592,7 @@ MACHINE_CONFIG_DERIVED( genesis_scd, megadriv )
|
||||
MCFG_TIMER_ADD("scd_dma_timer", scd_dma_timer_callback)
|
||||
|
||||
|
||||
//MCFG_QUANTUM_PERFECT_CPU("maincpu")
|
||||
MCFG_QUANTUM_PERFECT_CPU("maincpu")
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
/* Different Softlists for different regions (for now at least) */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user