mirror of
https://github.com/holub/mame
synced 2025-05-20 04:39:11 +03:00
Cleanups and version bump.
This commit is contained in:
Aaron Giles
parent
59ef1456fb
commit
213c72af7f
@ -336,7 +336,7 @@ static READ32_HANDLER( pxa255_dma_r )
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verboselog( space->machine, 4, "pxa255_dma_r: DMA Channel Control/Status Register %d: %08x & %08x\n", offset, dma_regs.dcsr[offset], mem_mask );
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return dma_regs.dcsr[offset];
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case PXA255_DINT:
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// verboselog( space->machine, 3, "pxa255_dma_r: DMA Interrupt Register: %08x & %08x\n", dma_regs.dint, mem_mask );
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// verboselog( space->machine, 3, "pxa255_dma_r: DMA Interrupt Register: %08x & %08x\n", dma_regs.dint, mem_mask );
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return dma_regs.dint;
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case PXA255_DRCMR0: case PXA255_DRCMR1: case PXA255_DRCMR2: case PXA255_DRCMR3:
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case PXA255_DRCMR4: case PXA255_DRCMR5: case PXA255_DRCMR6: case PXA255_DRCMR7:
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@ -389,7 +389,7 @@ static WRITE32_HANDLER( pxa255_dma_w )
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case PXA255_DCSR4: case PXA255_DCSR5: case PXA255_DCSR6: case PXA255_DCSR7:
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case PXA255_DCSR8: case PXA255_DCSR9: case PXA255_DCSR10: case PXA255_DCSR11:
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case PXA255_DCSR12: case PXA255_DCSR13: case PXA255_DCSR14: case PXA255_DCSR15:
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// verboselog( space->machine, 3, "pxa255_dma_w: DMA Channel Control/Status Register %d: %08x & %08x\n", offset, data, mem_mask );
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// verboselog( space->machine, 3, "pxa255_dma_w: DMA Channel Control/Status Register %d: %08x & %08x\n", offset, data, mem_mask );
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dma_regs.dcsr[offset] &= ~(data & 0x00000007);
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dma_regs.dcsr[offset] &= ~0x60000000;
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dma_regs.dcsr[offset] |= data & 0x60000000;
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@ -480,7 +480,7 @@ static void pxa255_ostimer_irq_check(running_machine* machine)
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static TIMER_CALLBACK( pxa255_ostimer_match )
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{
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// verboselog(machine, 3, "pxa255_ostimer_match channel %d\n", param);
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// verboselog(machine, 3, "pxa255_ostimer_match channel %d\n", param);
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ostimer_regs.ossr |= (1 << param);
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ostimer_regs.oscr = ostimer_regs.osmr[param];
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pxa255_ostimer_irq_check(machine);
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@ -491,33 +491,33 @@ static READ32_HANDLER( pxa255_ostimer_r )
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switch(PXA255_OSTMR_BASE_ADDR | (offset << 2))
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{
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case PXA255_OSMR0:
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// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Match Register 0: %08x & %08x\n", ostimer_regs.osmr[0], mem_mask );
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// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Match Register 0: %08x & %08x\n", ostimer_regs.osmr[0], mem_mask );
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return ostimer_regs.osmr[0];
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case PXA255_OSMR1:
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// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Match Register 1: %08x & %08x\n", ostimer_regs.osmr[1], mem_mask );
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// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Match Register 1: %08x & %08x\n", ostimer_regs.osmr[1], mem_mask );
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return ostimer_regs.osmr[1];
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case PXA255_OSMR2:
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// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Match Register 2: %08x & %08x\n", ostimer_regs.osmr[2], mem_mask );
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// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Match Register 2: %08x & %08x\n", ostimer_regs.osmr[2], mem_mask );
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return ostimer_regs.osmr[2];
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case PXA255_OSMR3:
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// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Match Register 3: %08x & %08x\n", ostimer_regs.osmr[3], mem_mask );
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// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Match Register 3: %08x & %08x\n", ostimer_regs.osmr[3], mem_mask );
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return ostimer_regs.osmr[3];
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case PXA255_OSCR:
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// verboselog( space->machine, 4, "pxa255_ostimer_r: OS Timer Count Register: %08x & %08x\n", ostimer_regs.oscr, mem_mask );
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// verboselog( space->machine, 4, "pxa255_ostimer_r: OS Timer Count Register: %08x & %08x\n", ostimer_regs.oscr, mem_mask );
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// free-running 3.something MHz counter. this is a complete hack.
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ostimer_regs.oscr += 0x300;
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return ostimer_regs.oscr;
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case PXA255_OSSR:
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// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Status Register: %08x & %08x\n", ostimer_regs.ossr, mem_mask );
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// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Status Register: %08x & %08x\n", ostimer_regs.ossr, mem_mask );
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return ostimer_regs.ossr;
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case PXA255_OWER:
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// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Watchdog Match Enable Register: %08x & %08x\n", ostimer_regs.ower, mem_mask );
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// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Watchdog Match Enable Register: %08x & %08x\n", ostimer_regs.ower, mem_mask );
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return ostimer_regs.ower;
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case PXA255_OIER:
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// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Interrupt Enable Register: %08x & %08x\n", ostimer_regs.oier, mem_mask );
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// verboselog( space->machine, 3, "pxa255_ostimer_r: OS Timer Interrupt Enable Register: %08x & %08x\n", ostimer_regs.oier, mem_mask );
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return ostimer_regs.oier;
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default:
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// verboselog( space->machine, 0, "pxa255_ostimer_r: Unknown address: %08x\n", PXA255_OSTMR_BASE_ADDR | (offset << 2));
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// verboselog( space->machine, 0, "pxa255_ostimer_r: Unknown address: %08x\n", PXA255_OSTMR_BASE_ADDR | (offset << 2));
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break;
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}
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return 0;
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@ -528,7 +528,7 @@ static WRITE32_HANDLER( pxa255_ostimer_w )
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switch(PXA255_OSTMR_BASE_ADDR | (offset << 2))
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{
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case PXA255_OSMR0:
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// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Match Register 0: %08x & %08x\n", data, mem_mask );
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// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Match Register 0: %08x & %08x\n", data, mem_mask );
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ostimer_regs.osmr[0] = data;
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if(ostimer_regs.oier & PXA255_OIER_E0)
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{
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@ -539,7 +539,7 @@ static WRITE32_HANDLER( pxa255_ostimer_w )
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}
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break;
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case PXA255_OSMR1:
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// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Match Register 1: %08x & %08x\n", data, mem_mask );
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// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Match Register 1: %08x & %08x\n", data, mem_mask );
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ostimer_regs.osmr[1] = data;
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if(ostimer_regs.oier & PXA255_OIER_E1)
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{
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@ -549,7 +549,7 @@ static WRITE32_HANDLER( pxa255_ostimer_w )
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}
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break;
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case PXA255_OSMR2:
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// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Match Register 2: %08x & %08x\n", data, mem_mask );
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// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Match Register 2: %08x & %08x\n", data, mem_mask );
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ostimer_regs.osmr[2] = data;
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if(ostimer_regs.oier & PXA255_OIER_E2)
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{
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@ -559,7 +559,7 @@ static WRITE32_HANDLER( pxa255_ostimer_w )
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}
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break;
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case PXA255_OSMR3:
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// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Match Register 3: %08x & %08x\n", data, mem_mask );
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// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Match Register 3: %08x & %08x\n", data, mem_mask );
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ostimer_regs.osmr[3] = data;
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if(ostimer_regs.oier & PXA255_OIER_E3)
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{
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@ -569,22 +569,22 @@ static WRITE32_HANDLER( pxa255_ostimer_w )
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}
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break;
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case PXA255_OSCR:
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// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Count Register: %08x & %08x\n", data, mem_mask );
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// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Count Register: %08x & %08x\n", data, mem_mask );
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ostimer_regs.oscr = data;
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break;
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case PXA255_OSSR:
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// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Status Register: %08x & %08x\n", data, mem_mask );
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// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Status Register: %08x & %08x\n", data, mem_mask );
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ostimer_regs.ossr &= ~data;
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pxa255_ostimer_irq_check(space->machine);
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break;
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case PXA255_OWER:
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// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Watchdog Enable Register: %08x & %08x\n", data, mem_mask );
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// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Watchdog Enable Register: %08x & %08x\n", data, mem_mask );
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ostimer_regs.ower = data & 0x00000001;
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break;
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case PXA255_OIER:
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{
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int index = 0;
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// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Interrupt Enable Register: %08x & %08x\n", data, mem_mask );
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// verboselog( space->machine, 3, "pxa255_ostimer_w: OS Timer Interrupt Enable Register: %08x & %08x\n", data, mem_mask );
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ostimer_regs.oier = data & 0x0000000f;
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for(index = 0; index < 4; index++)
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{
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@ -633,22 +633,22 @@ static READ32_HANDLER( pxa255_intc_r )
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switch(PXA255_INTC_BASE_ADDR | (offset << 2))
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{
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case PXA255_ICIP:
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// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller IRQ Pending Register: %08x & %08x\n", intc_regs.icip, mem_mask );
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// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller IRQ Pending Register: %08x & %08x\n", intc_regs.icip, mem_mask );
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return intc_regs.icip;
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case PXA255_ICMR:
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// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller Mask Register: %08x & %08x\n", intc_regs.icmr, mem_mask );
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// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller Mask Register: %08x & %08x\n", intc_regs.icmr, mem_mask );
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return intc_regs.icmr;
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case PXA255_ICLR:
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// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller Level Register: %08x & %08x\n", intc_regs.iclr, mem_mask );
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// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller Level Register: %08x & %08x\n", intc_regs.iclr, mem_mask );
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return intc_regs.iclr;
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case PXA255_ICFP:
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// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller FIQ Pending Register: %08x & %08x\n", intc_regs.icfp, mem_mask );
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// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller FIQ Pending Register: %08x & %08x\n", intc_regs.icfp, mem_mask );
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return intc_regs.icfp;
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case PXA255_ICPR:
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// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller Pending Register: %08x & %08x\n", intc_regs.icpr, mem_mask );
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// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller Pending Register: %08x & %08x\n", intc_regs.icpr, mem_mask );
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return intc_regs.icpr;
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case PXA255_ICCR:
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// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller Control Register: %08x & %08x\n", intc_regs.iccr, mem_mask );
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// verboselog( space->machine, 3, "pxa255_intc_r: Interrupt Controller Control Register: %08x & %08x\n", intc_regs.iccr, mem_mask );
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return intc_regs.iccr;
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default:
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verboselog( space->machine, 0, "pxa255_intc_r: Unknown address: %08x\n", PXA255_INTC_BASE_ADDR | (offset << 2));
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@ -665,21 +665,21 @@ static WRITE32_HANDLER( pxa255_intc_w )
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verboselog( space->machine, 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller IRQ Pending Register: %08x & %08x\n", data, mem_mask );
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break;
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case PXA255_ICMR:
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// verboselog( space->machine, 3, "pxa255_intc_w: Interrupt Controller Mask Register: %08x & %08x\n", data, mem_mask );
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// verboselog( space->machine, 3, "pxa255_intc_w: Interrupt Controller Mask Register: %08x & %08x\n", data, mem_mask );
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intc_regs.icmr = data & 0xfffe7f00;
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break;
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case PXA255_ICLR:
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// verboselog( space->machine, 3, "pxa255_intc_w: Interrupt Controller Level Register: %08x & %08x\n", data, mem_mask );
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// verboselog( space->machine, 3, "pxa255_intc_w: Interrupt Controller Level Register: %08x & %08x\n", data, mem_mask );
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intc_regs.iclr = data & 0xfffe7f00;
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break;
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case PXA255_ICFP:
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// verboselog( space->machine, 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller FIQ Pending Register: %08x & %08x\n", data, mem_mask );
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// verboselog( space->machine, 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller FIQ Pending Register: %08x & %08x\n", data, mem_mask );
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break;
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case PXA255_ICPR:
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// verboselog( space->machine, 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller Pending Register: %08x & %08x\n", data, mem_mask );
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// verboselog( space->machine, 3, "pxa255_intc_w: (Invalid Write) Interrupt Controller Pending Register: %08x & %08x\n", data, mem_mask );
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break;
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case PXA255_ICCR:
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// verboselog( space->machine, 3, "pxa255_intc_w: Interrupt Controller Control Register: %08x & %08x\n", data, mem_mask );
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// verboselog( space->machine, 3, "pxa255_intc_w: Interrupt Controller Control Register: %08x & %08x\n", data, mem_mask );
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intc_regs.iccr = data & 0x00000001;
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break;
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default:
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@ -707,8 +707,8 @@ static READ32_HANDLER( pxa255_gpio_r )
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verboselog( space->machine, 3, "pxa255_gpio_r: *Not Yet Implemented* GPIO Pin-Level Register 1: %08x & %08x\n", gpio_regs.gplr1, mem_mask );
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return 0xff9fffff;
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/*
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0x200000 = flip screen
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*/
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0x200000 = flip screen
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*/
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case PXA255_GPLR2:
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verboselog( space->machine, 3, "pxa255_gpio_r: *Not Yet Implemented* GPIO Pin-Level Register 2: %08x & %08x\n", gpio_regs.gplr2, mem_mask );
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return gpio_regs.gplr2;
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@ -1025,13 +1025,13 @@ static void pxa255_lcd_check_load_next_branch(running_machine* machine, int chan
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}
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else
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{
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// verboselog( machine, 3, "pxa255_lcd_check_load_next_branch: Not taking branch\n" );
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// verboselog( machine, 3, "pxa255_lcd_check_load_next_branch: Not taking branch\n" );
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}
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}
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static TIMER_CALLBACK( pxa255_lcd_dma_eof )
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{
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// verboselog( machine, 3, "End of frame callback\n" );
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// verboselog( machine, 3, "End of frame callback\n" );
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if(lcd_regs.dma[param].ldcmd & PXA255_LDCMD_EOFINT)
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{
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lcd_regs.liidr = lcd_regs.dma[param].fidr;
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@ -1076,7 +1076,7 @@ static READ32_HANDLER( pxa255_lcd_r )
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verboselog( space->machine, 3, "pxa255_lcd_r: TMED RGB Seed Register: %08x & %08x\n", lcd_regs.tcr, mem_mask );
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return lcd_regs.tcr;
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case PXA255_FDADR0: // 0x44000200
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// verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Frame Descriptor Address Register 0: %08x & %08x\n", lcd_regs.dma[0].fdadr, mem_mask );
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// verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Frame Descriptor Address Register 0: %08x & %08x\n", lcd_regs.dma[0].fdadr, mem_mask );
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return lcd_regs.dma[0].fdadr;
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case PXA255_FSADR0: // 0x44000204
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verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Frame Source Address Register 0: %08x & %08x\n", lcd_regs.dma[0].fsadr, mem_mask );
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@ -1085,7 +1085,7 @@ static READ32_HANDLER( pxa255_lcd_r )
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verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Frame ID Register 0: %08x & %08x\n", lcd_regs.dma[0].fidr, mem_mask );
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return lcd_regs.dma[0].fidr;
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case PXA255_LDCMD0: // 0x4400020c
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// verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Command Register 0: %08x & %08x\n", lcd_regs.dma[0].ldcmd & 0xfff00000, mem_mask );
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// verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Command Register 0: %08x & %08x\n", lcd_regs.dma[0].ldcmd & 0xfff00000, mem_mask );
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return lcd_regs.dma[0].ldcmd & 0xfff00000;
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case PXA255_FDADR1: // 0x44000210
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verboselog( space->machine, 3, "pxa255_lcd_r: LCD DMA Frame Descriptor Address Register 1: %08x & %08x\n", lcd_regs.dma[1].fdadr, mem_mask );
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@ -1131,7 +1131,7 @@ static WRITE32_HANDLER( pxa255_lcd_w )
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lcd_regs.fbr[0] = data & 0xfffffff3;
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if(!timer_enabled(lcd_regs.dma[0].eof))
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{
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// verboselog( space->machine, 3, "ch0 EOF timer is not enabled, taking branch now\n" );
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// verboselog( space->machine, 3, "ch0 EOF timer is not enabled, taking branch now\n" );
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pxa255_lcd_check_load_next_branch(space->machine, 0);
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pxa255_lcd_irq_check(space->machine);
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}
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@ -1216,19 +1216,19 @@ static INTERRUPT_GEN( pxa255_vblank_start )
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//static READ32_HANDLER( return_zero )
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//{
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// return 0;
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// return 0;
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//}
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//static READ32_HANDLER( unknown_r )
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//{
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// //return 0x00008000;
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// //return 0x00008000;
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//}
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static UINT32 seed, magic;
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static UINT32 state = 0;
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static READ32_HANDLER( cpld_r )
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{
|
||||
// printf("CPLD read @ %x (PC %x state %d)\n", offset, cpu_get_pc(space->cpu), state);
|
||||
// printf("CPLD read @ %x (PC %x state %d)\n", offset, cpu_get_pc(space->cpu), state);
|
||||
|
||||
if (cpu_get_pc(space->cpu) == 0x3f04)
|
||||
{
|
||||
@ -1296,10 +1296,10 @@ static WRITE32_HANDLER( cpld_w )
|
||||
else if (offset == 0xa)
|
||||
{
|
||||
}
|
||||
// else
|
||||
// {
|
||||
// printf("%08x: CPLD_W: %08x = %08x & %08x\n", cpu_get_pc(space->cpu), offset, data, mem_mask);
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
// printf("%08x: CPLD_W: %08x = %08x & %08x\n", cpu_get_pc(space->cpu), offset, data, mem_mask);
|
||||
// }
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START( 39in1_map, ADDRESS_SPACE_PROGRAM, 32 )
|
||||
@ -1452,7 +1452,7 @@ static MACHINE_DRIVER_START( 39in1 )
|
||||
MDRV_SCREEN_REFRESH_RATE(60)
|
||||
MDRV_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
|
||||
MDRV_SCREEN_FORMAT(BITMAP_FORMAT_RGB32)
|
||||
//MDRV_SCREEN_RAW_PARAMS(16777216/4, 308, 0, 240, 228, 0, 160) // completely bogus for this h/w
|
||||
//MDRV_SCREEN_RAW_PARAMS(16777216/4, 308, 0, 240, 228, 0, 160) // completely bogus for this h/w
|
||||
MDRV_SCREEN_SIZE(1024, 1024)
|
||||
MDRV_SCREEN_VISIBLE_AREA(0, 295, 0, 479)
|
||||
MDRV_PALETTE_LENGTH(256)
|
||||
@ -1480,12 +1480,12 @@ ROM_START( 39in1 )
|
||||
ROM_END
|
||||
|
||||
/*ROM_START( arm4in1 )
|
||||
// main program, encrypted
|
||||
ROM_REGION( 0x80000, "maincpu", 0 )
|
||||
// main program, encrypted
|
||||
ROM_REGION( 0x80000, "maincpu", 0 )
|
||||
ROM_LOAD( "27c4096_plz-v001_ver.300.bin", 0x000000, 0x080000, CRC(9149dbc4) SHA1(40efe1f654f11474f75ae7fee1613f435dbede38) )
|
||||
|
||||
// data ROM - contains a filesystem with ROMs, fonts, graphics, etc. in an unknown compressed format
|
||||
ROM_REGION32_LE( 0x200000, "data", 0 )
|
||||
// data ROM - contains a filesystem with ROMs, fonts, graphics, etc. in an unknown compressed format
|
||||
ROM_REGION32_LE( 0x200000, "data", 0 )
|
||||
ROM_LOAD( "16mflash.bin", 0x000000, 0x200000, CRC(a089f0f8) SHA1(e975eadd9176a8b9e416229589dfe3158cba22cb) )
|
||||
ROM_END*/
|
||||
|
||||
|
||||
@ -1111,7 +1111,7 @@ static INPUT_PORTS_START( paddlema )
|
||||
PORT_DIPSETTING( 0x80, "A to B" ) /* Manual shows "Upright Sytle B" */
|
||||
PORT_DIPSETTING( 0x00, "A to C" ) /* Manual shows "Upright Sytle A" */
|
||||
PORT_DIPSETTING( 0x40, "A to E" ) /* Manual shows "Table Sytle C" */
|
||||
// PORT_DIPSETTING( 0xc0, "A to B" ) /* Manual shows "Table Sytle D" */
|
||||
// PORT_DIPSETTING( 0xc0, "A to B" ) /* Manual shows "Table Sytle D" */
|
||||
|
||||
PORT_START("IN4") // DSW1
|
||||
PORT_SERVICE_DIPLOC( 0x01, IP_ACTIVE_HIGH, "SW2:8" )
|
||||
@ -1342,7 +1342,7 @@ static INPUT_PORTS_START( goldmedl )
|
||||
PORT_DIPSETTING( 0x00, "Upright 2 Players" )
|
||||
PORT_DIPSETTING( 0x80, "Upright 4 Players" )
|
||||
PORT_DIPSETTING( 0x88, DEF_STR( Cocktail ) )
|
||||
//PORT_DIPSETTING( 0x08, DEF_STR( Cocktail ) ) /* Not documented. */
|
||||
//PORT_DIPSETTING( 0x08, DEF_STR( Cocktail ) ) /* Not documented. */
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START3 ) PORT_DIPLOCATION("SW1:3") /* Listed as "Always OFF". */
|
||||
PORT_DIPNAME( 0x20, 0x20, "Speed For 100M Dash" ) PORT_DIPLOCATION("SW1:4")
|
||||
PORT_DIPSETTING( 0x00, "10 Beats For Max Speed" )
|
||||
|
||||
@ -183,12 +183,12 @@ static INPUT_PORTS_START( aquarium )
|
||||
PORT_DIPSETTING( 0x000c, "1/1" )
|
||||
PORT_DIPSETTING( 0x0008, "2/3" )
|
||||
PORT_DIPSETTING( 0x0004, "3/5" )
|
||||
// PORT_DIPSETTING( 0x0000, "1/1" ) /* Not used or listed in manual */
|
||||
// PORT_DIPSETTING( 0x0000, "1/1" ) /* Not used or listed in manual */
|
||||
PORT_DIPNAME( 0x0030, 0x0030, "Winning Rounds (Player VS Player)" ) PORT_DIPLOCATION("SW1:5,6")
|
||||
PORT_DIPSETTING( 0x0030, "1/1" )
|
||||
PORT_DIPSETTING( 0x0020, "2/3" )
|
||||
PORT_DIPSETTING( 0x0010, "3/5" )
|
||||
// PORT_DIPSETTING( 0x0000, "1/1" ) /* Not used or listed in manual */
|
||||
// PORT_DIPSETTING( 0x0000, "1/1" ) /* Not used or listed in manual */
|
||||
PORT_DIPUNUSED_DIPLOC( 0x0040, 0x0040, "SW1:7" ) /* Listed in the manual as always OFF */
|
||||
PORT_DIPUNUSED_DIPLOC( 0x0080, 0x0080, "SW1:8" ) /* Listed in the manual as always OFF */
|
||||
PORT_DIPNAME( 0x0700, 0x0700, DEF_STR( Coinage ) ) PORT_DIPLOCATION("SW2:1,2,3")
|
||||
|
||||
@ -69,10 +69,10 @@ static ADDRESS_MAP_START( bingor_map, ADDRESS_SPACE_PROGRAM, 16 )
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( bingor_io, ADDRESS_SPACE_IO, 16 )
|
||||
// AM_RANGE(0x0000, 0x00ff) AM_READ( test_r )
|
||||
// AM_RANGE(0x0000, 0x00ff) AM_READ( test_r )
|
||||
AM_RANGE(0x0100, 0x0101) AM_DEVWRITE8("saa", saa1099_data_w, 0x00ff)
|
||||
AM_RANGE(0x0102, 0x0103) AM_DEVWRITE8("saa", saa1099_control_w, 0x00ff)
|
||||
// AM_RANGE(0x0200, 0x0201) AM_READ( test_r )
|
||||
// AM_RANGE(0x0200, 0x0201) AM_READ( test_r )
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static READ8_HANDLER( test8_r )
|
||||
@ -139,7 +139,7 @@ INPUT_PORTS_END
|
||||
|
||||
static INTERRUPT_GEN( vblank_irq )
|
||||
{
|
||||
// cpu_set_input_line_and_vector(device,0,HOLD_LINE,0x08/4); // reads i/o 0x200 and puts the result in ram, pic irq?
|
||||
// cpu_set_input_line_and_vector(device,0,HOLD_LINE,0x08/4); // reads i/o 0x200 and puts the result in ram, pic irq?
|
||||
cpu_set_input_line_and_vector(device,0,HOLD_LINE,0x4c/4); // ?
|
||||
}
|
||||
|
||||
|
||||
@ -485,9 +485,9 @@ READ16_HANDLER( scudhamm_analog_r )
|
||||
prev=i;
|
||||
|
||||
/* effect of hammer collision 'accelerometer':
|
||||
$00 - $09 - no hit
|
||||
$0A - $3F - soft hit
|
||||
$40 - $FF - hard hit */
|
||||
$00 - $09 - no hit
|
||||
$0A - $3F - soft hit
|
||||
$40 - $FF - hard hit */
|
||||
if (j<0) return 0;
|
||||
else if (j>0xff) return 0xff;
|
||||
return j;
|
||||
|
||||
@ -54,7 +54,7 @@ ADDRESS_MAP_END
|
||||
static ADDRESS_MAP_START( sound_map, ADDRESS_SPACE_PROGRAM, 8 )
|
||||
AM_RANGE(0x0000, 0x0fff) AM_RAM
|
||||
AM_RANGE(0x4000, 0x4001) AM_DEVWRITE("ay", ay8910_address_data_w)
|
||||
// AM_RANGE(0x4002, 0x4002) AM_DEVREAD("ay", ay8910_r) /* ?? */
|
||||
// AM_RANGE(0x4002, 0x4002) AM_DEVREAD("ay", ay8910_r) /* ?? */
|
||||
AM_RANGE(0x6000, 0x6001) AM_DEVREADWRITE("ym", ym2203_r, ym2203_w)
|
||||
AM_RANGE(0x8000, 0xffff) AM_ROM
|
||||
ADDRESS_MAP_END
|
||||
@ -205,7 +205,7 @@ static MACHINE_DRIVER_START( citycon )
|
||||
|
||||
MDRV_CPU_ADD("audiocpu", M6809, 640000) /* 0.640 MHz ??? */
|
||||
MDRV_CPU_PROGRAM_MAP(sound_map)
|
||||
// MDRV_CPU_VBLANK_INT("screen", irq0_line_hold) //actually unused, probably it was during development
|
||||
// MDRV_CPU_VBLANK_INT("screen", irq0_line_hold) //actually unused, probably it was during development
|
||||
|
||||
/* video hardware */
|
||||
MDRV_SCREEN_ADD("screen", RASTER)
|
||||
|
||||
@ -1952,7 +1952,7 @@ GFXDECODE_END
|
||||
static const pia6821_interface pia0_intf =
|
||||
/*
|
||||
TAB light green board
|
||||
---------------------
|
||||
---------------------
|
||||
|
||||
PIA 0 PIA 1
|
||||
.--------u--------. .--------u--------.
|
||||
|
||||
@ -1202,13 +1202,13 @@ NAMCO_56DSW0
|
||||
PORT_DIPSETTING( 0x04, "30k Only" ) PORT_CONDITION("DSW2",0x02,PORTCOND_NOTEQUALS,0x00)
|
||||
PORT_DIPSETTING( 0x18, "30k & 60k Only" ) PORT_CONDITION("DSW2",0x02,PORTCOND_NOTEQUALS,0x00)
|
||||
PORT_DIPSETTING( 0x1c, "30k & 100k Only" ) PORT_CONDITION("DSW2",0x02,PORTCOND_NOTEQUALS,0x00)
|
||||
// PORT_DIPSETTING( 0x14, "30k 100k" ) // repeated PORT_CONDITION("DSW2",0x02,PORTCOND_NOTEQUALS,0x00)
|
||||
// PORT_DIPSETTING( 0x14, "30k 100k" ) // repeated PORT_CONDITION("DSW2",0x02,PORTCOND_NOTEQUALS,0x00)
|
||||
PORT_DIPSETTING( 0x0c, "30k, 120k & Every 120k" ) PORT_CONDITION("DSW2",0x02,PORTCOND_NOTEQUALS,0x00)
|
||||
PORT_DIPSETTING( 0x0c, "20k & 80k Only" ) PORT_CONDITION("DSW2",0x02,PORTCOND_EQUALS,0x00)
|
||||
PORT_DIPSETTING( 0x08, "30k" ) PORT_CONDITION("DSW2",0x02,PORTCOND_EQUALS,0x00)
|
||||
PORT_DIPSETTING( 0x10, "30k, 100k & Every 100k" ) PORT_CONDITION("DSW2",0x02,PORTCOND_EQUALS,0x00)
|
||||
PORT_DIPSETTING( 0x1c, "30k & 100k Only" ) PORT_CONDITION("DSW2",0x02,PORTCOND_EQUALS,0x00)
|
||||
// PORT_DIPSETTING( 0x14, "30k 100k" ) // repeated PORT_CONDITION("DSW2",0x02,PORTCOND_EQUALS,0x00)
|
||||
// PORT_DIPSETTING( 0x14, "30k 100k" ) // repeated PORT_CONDITION("DSW2",0x02,PORTCOND_EQUALS,0x00)
|
||||
PORT_DIPSETTING( 0x18, "40k & 80k Only" ) PORT_CONDITION("DSW2",0x02,PORTCOND_EQUALS,0x00)
|
||||
PORT_DIPSETTING( 0x04, "100k Only" ) PORT_CONDITION("DSW2",0x02,PORTCOND_EQUALS,0x00)
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( None ) )
|
||||
|
||||
@ -4703,7 +4703,7 @@ static ADDRESS_MAP_START( afega, ADDRESS_SPACE_PROGRAM, 16 )
|
||||
/**/AM_RANGE(0x08c000, 0x08c003) AM_RAM_WRITE(afega_scroll0_w) AM_BASE(&afega_scroll_0) // Scroll
|
||||
/**/AM_RANGE(0x08c004, 0x08c007) AM_RAM_WRITE(afega_scroll1_w) AM_BASE(&afega_scroll_1) //
|
||||
AM_RANGE(0x08c008, 0x08ffff) AM_WRITE(SMH_RAM) //
|
||||
/**/AM_RANGE(0x090000, 0x093fff) AM_RAM_WRITE(nmk_bgvideoram0_w) AM_BASE(&nmk_bgvideoram0) // Layer 0 // ?
|
||||
/**/AM_RANGE(0x090000, 0x093fff) AM_RAM_WRITE(nmk_bgvideoram0_w) AM_BASE(&nmk_bgvideoram0) // Layer 0 // ?
|
||||
/**/AM_RANGE(0x09c000, 0x09c7ff) AM_RAM_WRITE(nmk_txvideoram_w) AM_BASE(&nmk_txvideoram) // Layer 1
|
||||
|
||||
AM_RANGE(0x0c0000, 0x0cffff) AM_RAM_WRITE(nmk16_mainram_strange_w) AM_SHARE(1) AM_BASE(&nmk16_mainram)
|
||||
|
||||
@ -1,27 +1,27 @@
|
||||
/*
|
||||
Photon System
|
||||
Photon System
|
||||
|
||||
Uses PK8000 emulation by Miodrag Milanovic
|
||||
Imported to MAME by Mariusz Wojcieszek
|
||||
Uses PK8000 emulation by Miodrag Milanovic
|
||||
Imported to MAME by Mariusz Wojcieszek
|
||||
|
||||
Russian arcade system based on PK8000 home computer, created by unknown manufacturer
|
||||
in late 1980s or early 1990s.
|
||||
Russian arcade system based on PK8000 home computer, created by unknown manufacturer
|
||||
in late 1980s or early 1990s.
|
||||
|
||||
Following games were produced for this system:
|
||||
- Tetris
|
||||
- Python
|
||||
- Treasure/Labyrinth
|
||||
Following games were produced for this system:
|
||||
- Tetris
|
||||
- Python
|
||||
- Treasure/Labyrinth
|
||||
|
||||
Dump was made using custom adaptor, hence it is marked as bad dump.
|
||||
The real machine has following roms:
|
||||
0000...07FFh - ROM1 (D41)
|
||||
0800...0FFFh - ROM2 (D42)
|
||||
1000...17FFh - ROM3 (D43)
|
||||
1800...1FFFh - not chip sealed (D44)
|
||||
2000...27FFh - ROM5 (D45)
|
||||
2800...2FFFh - ROM6 (D46)
|
||||
3000...37FFh - ROM7 (D47)
|
||||
3000...37FFh - ROM8 (D48)
|
||||
Dump was made using custom adaptor, hence it is marked as bad dump.
|
||||
The real machine has following roms:
|
||||
0000...07FFh - ROM1 (D41)
|
||||
0800...0FFFh - ROM2 (D42)
|
||||
1000...17FFh - ROM3 (D43)
|
||||
1800...1FFFh - not chip sealed (D44)
|
||||
2000...27FFh - ROM5 (D45)
|
||||
2800...2FFFh - ROM6 (D46)
|
||||
3000...37FFh - ROM7 (D47)
|
||||
3000...37FFh - ROM8 (D48)
|
||||
|
||||
*/
|
||||
|
||||
|
||||
@ -1,81 +1,81 @@
|
||||
/*
|
||||
Polygonet Commanders (Konami, 1993)
|
||||
Poly-Net Warriors (Konami, 1993)
|
||||
Polygonet Commanders (Konami, 1993)
|
||||
Poly-Net Warriors (Konami, 1993)
|
||||
|
||||
Preliminary driver by R. Belmont
|
||||
Additional work by Andrew Gardner
|
||||
Preliminary driver by R. Belmont
|
||||
Additional work by Andrew Gardner
|
||||
|
||||
This is Konami's first 3D game!
|
||||
This is Konami's first 3D game!
|
||||
|
||||
Hardware:
|
||||
68EC020 @ 16 MHz
|
||||
Motorola XC56156-40 DSP @ 40 MHz
|
||||
Z80 + K054539 for sound
|
||||
Network to connect up to 4 PCBs.
|
||||
Hardware:
|
||||
68EC020 @ 16 MHz
|
||||
Motorola XC56156-40 DSP @ 40 MHz
|
||||
Z80 + K054539 for sound
|
||||
Network to connect up to 4 PCBs.
|
||||
|
||||
Video hardware:
|
||||
TTL text plane similar to Run and Gun.
|
||||
Konami K054009(x2) + K054010(x2) (polygon rasterizers)
|
||||
Konami K053936 "PSAC2" (3d roz plane, used for backgrounds)
|
||||
24.0 MHz crystal to drive the video hardware
|
||||
Video hardware:
|
||||
TTL text plane similar to Run and Gun.
|
||||
Konami K054009(x2) + K054010(x2) (polygon rasterizers)
|
||||
Konami K053936 "PSAC2" (3d roz plane, used for backgrounds)
|
||||
24.0 MHz crystal to drive the video hardware
|
||||
|
||||
Driver includes:
|
||||
- 68020 memory map
|
||||
- Z80 + sound system
|
||||
- EEPROM
|
||||
- service switch
|
||||
- TTL text plane
|
||||
Driver includes:
|
||||
- 68020 memory map
|
||||
- Z80 + sound system
|
||||
- EEPROM
|
||||
- service switch
|
||||
- TTL text plane
|
||||
|
||||
Driver needs:
|
||||
- Handle network at 580800 so game starts
|
||||
- Polygon rasterization (K054009 + K054010)
|
||||
- Hook up PSAC2 (gfx decode for it is already present and correct)
|
||||
- Palettes
|
||||
- Controls
|
||||
- Priorities. From the original board it appears they're fixed, in front to back order:
|
||||
(all the way in front) TTL text layer -> polygons -> PSAC2 (all the way in back)
|
||||
Driver needs:
|
||||
- Handle network at 580800 so game starts
|
||||
- Polygon rasterization (K054009 + K054010)
|
||||
- Hook up PSAC2 (gfx decode for it is already present and correct)
|
||||
- Palettes
|
||||
- Controls
|
||||
- Priorities. From the original board it appears they're fixed, in front to back order:
|
||||
(all the way in front) TTL text layer -> polygons -> PSAC2 (all the way in back)
|
||||
|
||||
Tech info by Phil Bennett, from the schematics:
|
||||
Tech info by Phil Bennett, from the schematics:
|
||||
|
||||
68000 address map
|
||||
=================
|
||||
68000 address map
|
||||
=================
|
||||
|
||||
400000-43ffff = PSAC
|
||||
440000-47ffff = PSVR
|
||||
480000-4bffff = IO
|
||||
4c0000-4fffff = SYS
|
||||
500000-53ffff = DSP
|
||||
540000-57ffff = FIX
|
||||
580000-5bffff = OP1
|
||||
5c0000-5fffff = UNUSED
|
||||
400000-43ffff = PSAC
|
||||
440000-47ffff = PSVR
|
||||
480000-4bffff = IO
|
||||
4c0000-4fffff = SYS
|
||||
500000-53ffff = DSP
|
||||
540000-57ffff = FIX
|
||||
580000-5bffff = OP1
|
||||
5c0000-5fffff = UNUSED
|
||||
|
||||
|
||||
SYS (Write only?)
|
||||
=================
|
||||
SYS (Write only?)
|
||||
=================
|
||||
|
||||
D28 = /FIXKILL - Disable 'FIX' layer?
|
||||
D27 = MUTE
|
||||
D26 = EEPROM CLK
|
||||
D25 = EEPROM CS
|
||||
D24 = EEPROM DATA
|
||||
D23 = BRMAS - 68k bus error mask
|
||||
D22 = L7MAS - L7 interrupt mask (unusued - should always be '1')
|
||||
D21 = /L5MAS - L5 interrupt mask/acknowledge
|
||||
D20 = L3MAS - L3 interrupt mask
|
||||
D19 = VFLIP - Flip video vertically
|
||||
D18 = HFLIP - Flip video horizontally
|
||||
D17 = COIN2 - Coin counter 2
|
||||
D16 = COIN1 - Coin counter 1
|
||||
D28 = /FIXKILL - Disable 'FIX' layer?
|
||||
D27 = MUTE
|
||||
D26 = EEPROM CLK
|
||||
D25 = EEPROM CS
|
||||
D24 = EEPROM DATA
|
||||
D23 = BRMAS - 68k bus error mask
|
||||
D22 = L7MAS - L7 interrupt mask (unusued - should always be '1')
|
||||
D21 = /L5MAS - L5 interrupt mask/acknowledge
|
||||
D20 = L3MAS - L3 interrupt mask
|
||||
D19 = VFLIP - Flip video vertically
|
||||
D18 = HFLIP - Flip video horizontally
|
||||
D17 = COIN2 - Coin counter 2
|
||||
D16 = COIN1 - Coin counter 1
|
||||
|
||||
|
||||
DSP
|
||||
===
|
||||
DSP
|
||||
===
|
||||
|
||||
500000-503fff = HCOM - 16kB common RAM
|
||||
504000-504fff = CONTROL - DSP/Host Control
|
||||
D10? = COMBNK - Switch between 68k and DSP access to common RAM
|
||||
D08? = RESN - Reset DSP
|
||||
506000-506fff = HEN - DSP/Host interface
|
||||
500000-503fff = HCOM - 16kB common RAM
|
||||
504000-504fff = CONTROL - DSP/Host Control
|
||||
D10? = COMBNK - Switch between 68k and DSP access to common RAM
|
||||
D08? = RESN - Reset DSP
|
||||
506000-506fff = HEN - DSP/Host interface
|
||||
|
||||
*/
|
||||
|
||||
|
||||
@ -50,10 +50,10 @@ Quantum3D's GCI (Game Control Interface) - a unique, low-cost subsystem
|
||||
|
||||
===============================================================================
|
||||
TODO:
|
||||
* Add BIOS dump (custom 440LX motherboard or standard?)
|
||||
* Hook up PC hardware
|
||||
* Hook up the GCI (details? ROMs?)
|
||||
* What's the dongle do?
|
||||
* Add BIOS dump (custom 440LX motherboard or standard?)
|
||||
* Hook up PC hardware
|
||||
* Hook up the GCI (details? ROMs?)
|
||||
* What's the dongle do?
|
||||
===============================================================================
|
||||
*/
|
||||
|
||||
@ -81,22 +81,22 @@ static ADDRESS_MAP_START( quake_map, ADDRESS_SPACE_PROGRAM, 32 )
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( quake_io, ADDRESS_SPACE_IO, 32 )
|
||||
// AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", dma8237_r, dma8237_w, 0xffffffff)
|
||||
// AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", dma8237_r, dma8237_w, 0xffffffff)
|
||||
AM_RANGE(0x0020, 0x003f) AM_DEVREADWRITE8("pic8259_1", pic8259_r, pic8259_w, 0xffffffff)
|
||||
// AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE8("pit8254", pit8253_r, pit8253_w, 0xffffffff)
|
||||
// AM_RANGE(0x0060, 0x006f) AM_READWRITE(kbdc8042_32le_r, kbdc8042_32le_w)
|
||||
// AM_RANGE(0x0070, 0x007f) AM_READWRITE(mc146818_port32le_r, mc146818_port32le_w)
|
||||
// AM_RANGE(0x0080, 0x009f) AM_READWRITE(at_page32_r, at_page32_w)
|
||||
// AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE8("pit8254", pit8253_r, pit8253_w, 0xffffffff)
|
||||
// AM_RANGE(0x0060, 0x006f) AM_READWRITE(kbdc8042_32le_r, kbdc8042_32le_w)
|
||||
// AM_RANGE(0x0070, 0x007f) AM_READWRITE(mc146818_port32le_r, mc146818_port32le_w)
|
||||
// AM_RANGE(0x0080, 0x009f) AM_READWRITE(at_page32_r, at_page32_w)
|
||||
AM_RANGE(0x00a0, 0x00bf) AM_DEVREADWRITE8("pic8259_2", pic8259_r, pic8259_w, 0xffffffff)
|
||||
// AM_RANGE(0x00c0, 0x00df) AM_DEVREADWRITE("dma8237_2", at32_dma8237_2_r, at32_dma8237_2_w)
|
||||
// AM_RANGE(0x00c0, 0x00df) AM_DEVREADWRITE("dma8237_2", at32_dma8237_2_r, at32_dma8237_2_w)
|
||||
AM_RANGE(0x00e8, 0x00eb) AM_NOP
|
||||
// AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_r, ide_w)
|
||||
// AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_r, ide_w)
|
||||
AM_RANGE(0x0300, 0x03af) AM_NOP
|
||||
AM_RANGE(0x03b0, 0x03df) AM_NOP
|
||||
// AM_RANGE(0x0278, 0x027b) AM_WRITE(pnp_config_w)
|
||||
// AM_RANGE(0x03f0, 0x03ff) AM_DEVREADWRITE("ide", fdc_r, fdc_w)
|
||||
// AM_RANGE(0x0a78, 0x0a7b) AM_WRITE(pnp_data_w)
|
||||
// AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_32le_r, pci_32le_w)
|
||||
// AM_RANGE(0x0278, 0x027b) AM_WRITE(pnp_config_w)
|
||||
// AM_RANGE(0x03f0, 0x03ff) AM_DEVREADWRITE("ide", fdc_r, fdc_w)
|
||||
// AM_RANGE(0x0a78, 0x0a7b) AM_WRITE(pnp_data_w)
|
||||
// AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_32le_r, pci_32le_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
/*************************************************************
|
||||
|
||||
@ -1946,7 +1946,7 @@ static ADDRESS_MAP_START( jjsquawb_map, ADDRESS_SPACE_PROGRAM, 16 )
|
||||
AM_RANGE(0x908000, 0x908005) AM_RAM AM_BASE(&seta_vctrl_0) // VRAM 0&1 Ctrl
|
||||
AM_RANGE(0x909000, 0x909005) AM_RAM AM_BASE(&seta_vctrl_2) // VRAM 2&3 Ctrl
|
||||
AM_RANGE(0xa0a000, 0xa0a607) AM_RAM AM_BASE(&spriteram16) // RZ: Sprites Y
|
||||
// AM_RANGE(0xa80000, 0xa80001) AM_RAM // ? 0x4000
|
||||
// AM_RANGE(0xa80000, 0xa80001) AM_RAM // ? 0x4000
|
||||
AM_RANGE(0xb0c000, 0xb0ffff) AM_RAM AM_BASE(&spriteram16_2) // RZ: Sprites Code + X + Attr
|
||||
AM_RANGE(0xc00000, 0xc03fff) AM_DEVREADWRITE("x1", seta_sound_word_r,seta_sound_word_w) // Sound
|
||||
#if __uPD71054_TIMER
|
||||
|
||||
@ -16,64 +16,64 @@ TODO:
|
||||
|
||||
Bought as "old poker game by videotronics early 80's"
|
||||
|
||||
Scratched on the CPU board SN1069
|
||||
Scratched on the CPU board SN1069
|
||||
Scratched on the CPU board SN1069
|
||||
Scratched on the CPU board SN1069
|
||||
|
||||
CPU board
|
||||
.0 2716 stickered DRAWPKR2 located top left
|
||||
8-F
|
||||
REV A
|
||||
.0 2716 stickered DRAWPKR2 located top left
|
||||
8-F
|
||||
REV A
|
||||
|
||||
.1 2716 stickered DRAWPKR2 located next to .0
|
||||
0-7
|
||||
REV A
|
||||
.1 2716 stickered DRAWPKR2 located next to .0
|
||||
0-7
|
||||
REV A
|
||||
|
||||
ROM board
|
||||
Top of board left to right
|
||||
.R0 2716 stickered RA
|
||||
0-7
|
||||
.R0 2716 stickered RA
|
||||
0-7
|
||||
|
||||
.R1 2716 stickered RA
|
||||
8-F
|
||||
.R1 2716 stickered RA
|
||||
8-F
|
||||
|
||||
.R2 2716 stickered BA
|
||||
0-7
|
||||
.R2 2716 stickered BA
|
||||
0-7
|
||||
|
||||
.R3 2716 stickered BA
|
||||
8-F
|
||||
.R3 2716 stickered BA
|
||||
8-F
|
||||
|
||||
.R4 2716 stickered GA
|
||||
0-7
|
||||
.R4 2716 stickered GA
|
||||
0-7
|
||||
|
||||
.R5 2716 stickered GA
|
||||
8-F
|
||||
.R5 2716 stickered GA
|
||||
8-F
|
||||
|
||||
|
||||
Below top row left to right
|
||||
.R6 2716 stickered RB
|
||||
0-7
|
||||
.R6 2716 stickered RB
|
||||
0-7
|
||||
|
||||
.R7 2716 stickered RB
|
||||
8-F
|
||||
.R7 2716 stickered RB
|
||||
8-F
|
||||
|
||||
.R8 2716 stickered BB
|
||||
0-7
|
||||
.R8 2716 stickered BB
|
||||
0-7
|
||||
|
||||
.R9 2716 stickered BB
|
||||
8-F
|
||||
.R9 2716 stickered BB
|
||||
8-F
|
||||
|
||||
.R10 2716 stickered GB
|
||||
0-7
|
||||
.R10 2716 stickered GB
|
||||
0-7
|
||||
|
||||
.R11 2716 stickered GB
|
||||
8-F
|
||||
.R11 2716 stickered GB
|
||||
8-F
|
||||
|
||||
ROM data showed cards
|
||||
|
||||
6809 cpu
|
||||
4.000Mhz crystal
|
||||
MC6840P
|
||||
mm74c920J/mmc6551j-9 x2
|
||||
mm74c920J/mmc6551j-9 x2
|
||||
|
||||
|
||||
**************************************************************************************************************/
|
||||
@ -130,7 +130,7 @@ static WRITE8_HANDLER( blitter_w )
|
||||
blit_offs = (blit_ram[1] & 0x01)<<8|(blit_ram[2] & 0xff);
|
||||
|
||||
videoram[blit_offs] = blit_ram[0];
|
||||
// printf("%02x %02x %02x %02x %02x %02x %02x %02x\n",blit_ram[0],blit_ram[1],blit_ram[2],blit_ram[3],blit_ram[4],blit_ram[5],blit_ram[6],blit_ram[7]);
|
||||
// printf("%02x %02x %02x %02x %02x %02x %02x %02x\n",blit_ram[0],blit_ram[1],blit_ram[2],blit_ram[3],blit_ram[4],blit_ram[5],blit_ram[6],blit_ram[7]);
|
||||
}
|
||||
}
|
||||
|
||||
@ -399,7 +399,7 @@ static MACHINE_DRIVER_START( vpoker )
|
||||
/* basic machine hardware */
|
||||
MDRV_CPU_ADD("maincpu",M6809,XTAL_4MHz)
|
||||
MDRV_CPU_PROGRAM_MAP(main_map)
|
||||
// MDRV_CPU_VBLANK_INT("screen",irq0_line_hold) //irq0 valid too
|
||||
// MDRV_CPU_VBLANK_INT("screen",irq0_line_hold) //irq0 valid too
|
||||
|
||||
/* video hardware */
|
||||
MDRV_SCREEN_ADD("screen", RASTER)
|
||||
@ -420,8 +420,8 @@ static MACHINE_DRIVER_START( vpoker )
|
||||
|
||||
/* sound hardware */
|
||||
MDRV_SPEAKER_STANDARD_MONO("mono")
|
||||
// MDRV_SOUND_ADD("ay", AY8910, 8000000/4 /* guess */)
|
||||
// MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.30)
|
||||
// MDRV_SOUND_ADD("ay", AY8910, 8000000/4 /* guess */)
|
||||
// MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.30)
|
||||
MACHINE_DRIVER_END
|
||||
|
||||
/***************************************************************************
|
||||
|
||||
@ -530,7 +530,7 @@ ReadWriteC148( const address_space *space, offs_t offset, UINT16 data, int bWrit
|
||||
{
|
||||
// mame_printf_debug( "cpu(%d) RAM[0x%06x] = 0x%x\n", cpu, addr, data );
|
||||
/* Dubious to assert IRQ for other CPU here, but Starblade seems to rely on it.
|
||||
It fails to show large polygons otherwise. */
|
||||
It fails to show large polygons otherwise. */
|
||||
cpu_set_input_line(altcpu, pC148RegAlt[NAMCOS2_C148_CPUIRQ], ASSERT_LINE);
|
||||
}
|
||||
break;
|
||||
|
||||
@ -250,14 +250,14 @@ WRITE16_HANDLER( namcos2_68k_video_palette_w )
|
||||
|
||||
/* register 4: ? */
|
||||
/* sets using it:
|
||||
assault: $0020
|
||||
burnforc: $0130 after titlescreen
|
||||
dirtfoxj: $0108 at game start
|
||||
finalap1/2/3: $00C0
|
||||
finehour: $0168 after titlescreen
|
||||
fourtrax: $00E8 and $00F0
|
||||
luckywld: $00E8 at titlescreen, $00A0 in game and $0118 if in tunnel
|
||||
suzuka8h1/2: $00E8 and $00A0 */
|
||||
assault: $0020
|
||||
burnforc: $0130 after titlescreen
|
||||
dirtfoxj: $0108 at game start
|
||||
finalap1/2/3: $00C0
|
||||
finehour: $0168 after titlescreen
|
||||
fourtrax: $00E8 and $00F0
|
||||
luckywld: $00E8 at titlescreen, $00A0 in game and $0118 if in tunnel
|
||||
suzuka8h1/2: $00E8 and $00A0 */
|
||||
case 0x1808: case 0x1809:
|
||||
// if (data^namcos2_68k_palette_ram[offset]) printf("%04X\n",data<<((~offset&1)<<3)|namcos2_68k_palette_ram[offset^1]<<((offset&1)<<3));
|
||||
break;
|
||||
|
||||
@ -618,16 +618,16 @@ static void draw_sprites( const device_config *device, UINT8 *line_priority )
|
||||
plane1 = memory_read_byte(device->space[0], (index1 + sprite_line) & 0x1fff);
|
||||
plane2 = memory_read_byte(device->space[0], (index1 + sprite_line + 8) & 0x1fff);
|
||||
|
||||
// sd = gfx_element_get_data(device->machine->gfx[gfx_bank], index1 % total_elements) + start;
|
||||
// if (size > 8)
|
||||
// gfx_element_get_data(device->machine->gfx[gfx_bank], (index1 + 1) % total_elements);
|
||||
// sd = gfx_element_get_data(device->machine->gfx[gfx_bank], index1 % total_elements) + start;
|
||||
// if (size > 8)
|
||||
// gfx_element_get_data(device->machine->gfx[gfx_bank], (index1 + 1) % total_elements);
|
||||
|
||||
if (pri)
|
||||
{
|
||||
/* draw the low-priority sprites */
|
||||
for (pixel = 0; pixel < 8; pixel++)
|
||||
{
|
||||
// UINT8 pixelData = flipx ? sd[7-pixel] : sd[pixel];
|
||||
// UINT8 pixelData = flipx ? sd[7-pixel] : sd[pixel];
|
||||
UINT8 pixelData;
|
||||
if (flipx)
|
||||
{
|
||||
@ -998,7 +998,7 @@ static DEVICE_RESET( ppu2c0x )
|
||||
|
||||
/*************************************
|
||||
*
|
||||
* PPU Memory functions
|
||||
* PPU Memory functions
|
||||
*
|
||||
*************************************/
|
||||
|
||||
@ -1278,7 +1278,7 @@ void ppu2c0x_spriteram_dma( const address_space *space, const device_config *dev
|
||||
{
|
||||
UINT8 spriteData = memory_read_byte(space, address + i);
|
||||
memory_write_byte(space, 0x2004, spriteData);
|
||||
// ppu2c0x_w(device, PPU_SPRITE_DATA, spriteData);
|
||||
// ppu2c0x_w(device, PPU_SPRITE_DATA, spriteData);
|
||||
}
|
||||
|
||||
// should last 513 CPU cycles.
|
||||
|
||||
@ -10,4 +10,4 @@
|
||||
***************************************************************************/
|
||||
|
||||
extern const char build_version[];
|
||||
const char build_version[] = "0.133 ("__DATE__")";
|
||||
const char build_version[] = "0.133u1 ("__DATE__")";
|
||||
|
||||
Loading…
Reference in New Issue
Block a user