mirror of
https://github.com/holub/mame
synced 2025-04-19 15:11:37 +03:00
added interrupt handling
This commit is contained in:
hap
parent
ba0057dfc0
commit
215e9a8be9
@ -10,7 +10,7 @@
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*/
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#include "m58846.h"
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#include "debugger.h"
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//#include "debugger.h"
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@ -50,6 +50,9 @@ offs_t m58846_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *o
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void m58846_device::device_start()
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{
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melps4_cpu_device::device_start();
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m_timer[0] = timer_alloc(0);
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m_timer[1] = timer_alloc(1);
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}
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@ -61,6 +64,52 @@ void m58846_device::device_start()
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void m58846_device::device_reset()
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{
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melps4_cpu_device::device_reset();
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// timer 1 runs continuously
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reset_timer1();
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}
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//-------------------------------------------------
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// timers
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//-------------------------------------------------
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void m58846_device::reset_timer1()
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{
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// reset 7-bit prescaler
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attotime base = attotime::from_ticks(6 * 128, unscaled_clock());
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m_timer[0]->adjust(base);
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}
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void m58846_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
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{
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switch (id)
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{
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// timer 1
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case 0:
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m_irqflag[1] = true;
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m_possible_irq = true;
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reset_timer1();
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break;
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// timer 2
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case 1:
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break;
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default:
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assert_always(FALSE, "Unknown id in m58846_device::device_timer");
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break;
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}
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}
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void m58846_device::write_v(UINT8 data)
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{
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// d0: enable timer 1 irq
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m_tmr_irq_enabled[0] = (data & 1) ? true : false;
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m_possible_irq = true;
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m_v = data;
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}
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@ -29,6 +29,13 @@ protected:
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// device_disasm_interface overrides
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
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// timers
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virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
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virtual void write_v(UINT8 data);
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emu_timer *m_timer[2];
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void reset_timer1();
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};
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@ -46,12 +46,15 @@ void melps4_cpu_device::state_string_export(const device_state_entry &entry, std
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{
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// obviously not from a single flags register, letters are made up
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case STATE_GENFLAGS:
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strprintf(str, "%c%c%c%c%c",
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strprintf(str, "%c%c%c%c%c %c%c%c",
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m_intp ? 'P':'p',
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m_inte ? 'I':'i',
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m_sm ? 'S':'s',
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m_cps ? 'D':'d',
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m_cy ? 'C':'c'
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m_cy ? 'C':'c',
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m_irqflag[0] ? 'X':'.', // exf
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m_irqflag[1] ? '1':'.', // 1f
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m_irqflag[2] ? '2':'.' // 2f
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);
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break;
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@ -111,7 +114,11 @@ void melps4_cpu_device::device_start()
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m_skip = false;
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m_inte = 0;
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m_intp = 1;
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m_irqflag[0] = m_irqflag[1] = m_irqflag[2] = false;
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m_tmr_irq_enabled[0] = m_tmr_irq_enabled[1] = false;
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m_int_state = 0;
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m_prohibit_irq = false;
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m_possible_irq = false;
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m_a = 0;
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m_b = 0;
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@ -147,7 +154,11 @@ void melps4_cpu_device::device_start()
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save_item(NAME(m_skip));
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save_item(NAME(m_inte));
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save_item(NAME(m_intp));
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save_item(NAME(m_irqflag));
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save_item(NAME(m_tmr_irq_enabled));
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save_item(NAME(m_int_state));
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save_item(NAME(m_prohibit_irq));
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save_item(NAME(m_possible_irq));
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save_item(NAME(m_a));
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save_item(NAME(m_b));
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@ -165,7 +176,7 @@ void melps4_cpu_device::device_start()
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// register state for debugger
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state_add(STATE_GENPC, "curpc", m_pc).formatstr("%04X").noshow();
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state_add(STATE_GENFLAGS, "GENFLAGS", m_cy).formatstr("%5s").noshow();
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state_add(STATE_GENFLAGS, "GENFLAGS", m_cy).formatstr("%9s").noshow();
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state_add(MELPS4_PC, "PC", m_pc).formatstr("%04X");
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state_add(MELPS4_A, "A", m_a).formatstr("%2d"); // show in decimal
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@ -194,18 +205,20 @@ void melps4_cpu_device::device_reset()
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{
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m_sm = m_sms = false;
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m_ba_flag = false;
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m_prohibit_irq = false;
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m_skip = false;
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m_op = m_prev_op = 0;
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m_pc = m_prev_pc = 0;
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m_inte = 0;
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m_intp = 1;
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op_lcps(); // CPS=0
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m_v = 0;
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m_w = 0;
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// clear interrupts
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m_inte = 0;
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m_intp = 1;
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write_v(0);
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write_w(0);
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m_irqflag[0] = m_irqflag[1] = m_irqflag[2] = false;
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m_prohibit_irq = false;
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m_possible_irq = false;
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// clear ports
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write_d_pin(MELPS4_PORTD_CLR, 0);
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write_gen_port(MELPS4_PORTS, 0);
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@ -291,6 +304,73 @@ void melps4_cpu_device::write_d_pin(int bit, int state)
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//-------------------------------------------------
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// interrupts
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//-------------------------------------------------
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void melps4_cpu_device::execute_set_input(int line, int state)
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{
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state = (state) ? 1 : 0;
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switch (line)
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{
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// external interrupt
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case MELPS4_INPUT_LINE_INT:
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// irq on rising/falling edge
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if (state != m_int_state && state == m_intp)
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{
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m_irqflag[0] = true;
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m_possible_irq = true;
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}
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m_int_state = state;
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break;
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// timer input pin
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case MELPS4_INPUT_LINE_T:
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break;
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default:
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break;
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}
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}
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void melps4_cpu_device::do_interrupt(int which)
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{
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m_inte = 0;
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m_irqflag[which] = false;
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m_icount--;
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push_pc();
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m_sms = m_sm;
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m_sm = false;
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m_op = 0; // fake nop
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m_pc = m_int_page << 7 | (which * 2);
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standard_irq_callback(which);
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}
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void melps4_cpu_device::check_interrupt()
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{
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if (!m_inte)
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return;
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int which = 0;
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// assume that lower irq vectors have higher priority
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if (m_irqflag[0])
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which = 0;
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else if (m_irqflag[1] && m_tmr_irq_enabled[0])
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which = 1;
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else if (m_irqflag[2] && m_tmr_irq_enabled[1])
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which = 2;
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else
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return;
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do_interrupt(which);
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}
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//-------------------------------------------------
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// execute
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//-------------------------------------------------
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@ -314,8 +394,14 @@ void melps4_cpu_device::execute_run()
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m_prev_op = m_op;
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m_prev_pc = m_pc;
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// irq is not accepted during skip or LXY, LA, EI, DI, RT/RTS/RTI or any branch
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//..
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// Interrupts are not accepted during skips or LXY, LA, EI, DI, RT/RTS/RTI or any branch.
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// Documentation is conflicting here: older docs say that it is allowed during skips,
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// newer docs specifically say when interrupts are prohibited.
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if (m_possible_irq && !m_prohibit_irq && !m_skip)
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{
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m_possible_irq = false;
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check_interrupt();
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}
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m_prohibit_irq = false;
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// fetch next opcode
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@ -60,6 +60,12 @@ enum
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MELPS4_PORTU
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};
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enum
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{
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MELPS4_INPUT_LINE_INT = 0,
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MELPS4_INPUT_LINE_T
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};
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// pinout reference
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@ -142,8 +148,9 @@ protected:
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virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const { return (clocks + 6 - 1) / 6; } // 6 t-states per machine cycle
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virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const { return (cycles * 6); } // "
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virtual UINT32 execute_min_cycles() const { return 1; }
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virtual UINT32 execute_max_cycles() const { return 1; }
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virtual UINT32 execute_max_cycles() const { return 1+1; } // max opcode cycles + interrupt duration
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virtual UINT32 execute_input_lines() const { return 3; } // up to 3 (some internal)
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virtual void execute_set_input(int line, int state);
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virtual void execute_run();
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virtual void execute_one();
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@ -189,14 +196,18 @@ protected:
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UINT8 m_port_s; // "
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UINT8 m_port_f; // "
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bool m_sm, m_sms; // subroutine mode flag + stack
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bool m_sm, m_sms; // subroutine mode flag + irq stack
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bool m_ba_flag; // temp flag indicates BA opcode was executed
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UINT8 m_sp_param; // temp register holding SP opcode parameter
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UINT8 m_cps; // DP,CY or DP',CY' selected
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bool m_skip; // skip next opcode
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UINT8 m_inte; // interrupt enable flag
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UINT8 m_intp; // external interrupt polarity ('40 to '44)
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int m_intp; // external interrupt polarity ('40 to '44)
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bool m_irqflag[3]; // irq flags: exf, 1f, 2f (external, timer 1, timer 2)
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bool m_tmr_irq_enabled[2];
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int m_int_state; // INT pin state
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bool m_prohibit_irq; // interrupt is prohibited during certain opcodes
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bool m_possible_irq; // indicate that irq needs to be rechecked
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// work registers (unless specified, each is 4-bit)
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UINT8 m_a; // accumulator
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@ -225,6 +236,11 @@ protected:
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devcb_write8 m_write_g;
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devcb_write8 m_write_u;
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devcb_write_line m_write_t;
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virtual void write_v(UINT8 data) { m_v = data; }
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virtual void write_w(UINT8 data) { m_w = data; }
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virtual void do_interrupt(int which);
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virtual void check_interrupt();
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UINT8 read_gen_port(int port);
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void write_gen_port(int port, UINT8 data);
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@ -419,25 +419,27 @@ void melps4_cpu_device::op_tab2()
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void melps4_cpu_device::op_tva()
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{
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// TVA: transfer A to timer control V
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m_v = m_a;
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write_v(m_a);
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}
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void melps4_cpu_device::op_twa()
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{
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// TWA: transfer A to timer control W
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m_w = m_a;
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write_w(m_a);
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}
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void melps4_cpu_device::op_snz1()
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{
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// SNZ1: skip next on flag 1F
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op_illegal();
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m_skip = m_irqflag[1];
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m_irqflag[1] = false;
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}
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void melps4_cpu_device::op_snz2()
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{
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// SNZ2: skip next on flag 2F
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op_illegal();
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m_skip = m_irqflag[2];
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m_irqflag[2] = false;
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}
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@ -631,6 +633,7 @@ void melps4_cpu_device::op_ei()
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{
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// EI: enable interrupt flag
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m_prohibit_irq = true;
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m_possible_irq = true;
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m_inte = 1;
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}
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