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Revert "h8_sci: Suppress SCK transition at end of transmit sequence (fixes regression in puzzlet)"
This reverts commit 3c038a50af
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parent
7067cbda9a
commit
21d9f725a0
@ -374,12 +374,8 @@ u64 h8_sci_device::internal_update(u64 current_time)
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bool new_clock = delta >= m_divider;
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if(new_clock != m_tx_clock_value) {
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machine().scheduler().synchronize();
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if(!new_clock) {
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if(!new_clock)
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tx_dropped_edge();
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// HACK: prevent extra transition on SCK output at end of transmission sequence
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if(m_tx_state == ST_IDLE)
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new_clock = true;
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}
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m_tx_clock_value = new_clock;
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if(m_clock_state || m_tx_clock_value)
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@ -425,12 +421,8 @@ u64 h8_sci_device::internal_update(u64 current_time)
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bool new_clock = delta >= m_divider*8;
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if(new_clock != m_tx_clock_value) {
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machine().scheduler().synchronize();
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if(!new_clock) {
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if(!new_clock)
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tx_dropped_edge();
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// HACK: prevent extra transition on SCK output at end of transmission sequence
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if(m_tx_state == ST_IDLE)
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new_clock = true;
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}
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m_tx_clock_value = new_clock;
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if(m_clock_mode == clock_mode_t::INTERNAL_ASYNC_OUT && (m_clock_state || !m_tx_clock_value))
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