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add Special Status Word (SSW) to exception frames

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This commit is contained in:
Sven Schnelle 2018-10-07 10:58:50 +02:00
parent be699d5197
commit 222e0d5522
4 changed files with 34 additions and 5 deletions
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7
src/devices/cpu/m68000/m68000.h
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@ -32,6 +32,10 @@ constexpr int M68K_IRQ_5 = 5;
constexpr int M68K_IRQ_6 = 6;
constexpr int M68K_IRQ_7 = 7;
constexpr int M68K_SZ_LONG = 0;
constexpr int M68K_SZ_BYTE = 1;
constexpr int M68K_SZ_WORD = 2;
// special input lines
constexpr int M68K_LINE_BUSERROR = 16;
@ -278,10 +282,13 @@ protected:
uint16_t m_mmu_tmp_sr; /* temporary hack: status code for ptest and to handle write protection */
uint16_t m_mmu_tmp_fc; /* temporary hack: function code for the mmu (moves) */
uint16_t m_mmu_tmp_rw; /* temporary hack: read/write (1/0) for the mmu */
uint8_t m_mmu_tmp_sz; /* temporary hack: size for mmu */
uint32_t m_mmu_tmp_buserror_address; /* temporary hack: (first) bus error address */
uint16_t m_mmu_tmp_buserror_occurred; /* temporary hack: flag that bus error has occurred from mmu */
uint16_t m_mmu_tmp_buserror_fc; /* temporary hack: (first) bus error fc */
uint16_t m_mmu_tmp_buserror_rw; /* temporary hack: (first) bus error rw */
uint16_t m_mmu_tmp_buserror_sz; /* temporary hack: (first) bus error size` */
uint32_t m_ic_address[M68K_IC_SIZE]; /* instruction cache address data */
uint32_t m_ic_data[M68K_IC_SIZE]; /* instruction cache content data */

4
src/devices/cpu/m68000/m68kcpu.cpp
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@ -669,6 +669,10 @@ void m68000_base_device::postload()
void m68000_base_device::m68k_cause_bus_error()
{
m_mmu_tmp_buserror_fc = m_mmu_tmp_fc;
m_mmu_tmp_buserror_rw = m_mmu_tmp_rw;
m_mmu_tmp_buserror_sz = m_mmu_tmp_sz;
// Halt the cpu on berr when writing the stack frame.
if (m_run_mode == RUN_MODE_BERR_AERR_RESET_WSF)
{

18
src/devices/cpu/m68000/m68kcpu.h
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@ -590,7 +590,7 @@ inline uint32_t m68ki_read_imm_16()
m_mmu_tmp_fc = m_s_flag | FUNCTION_CODE_USER_PROGRAM;
m_mmu_tmp_rw = 1;
m_mmu_tmp_sz = M68K_SZ_WORD;
m68ki_check_address_error(m_pc, MODE_READ, m_s_flag | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
if (m_pc != m_pref_addr)
@ -617,7 +617,7 @@ inline uint32_t m68ki_read_imm_32()
m_mmu_tmp_fc = m_s_flag | FUNCTION_CODE_USER_PROGRAM;
m_mmu_tmp_rw = 1;
m_mmu_tmp_sz = M68K_SZ_LONG;
m68ki_check_address_error(m_pc, MODE_READ, m_s_flag | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */
if(m_pc != m_pref_addr)
@ -652,6 +652,7 @@ inline uint32_t m68ki_read_8_fc(uint32_t address, uint32_t fc)
{
m_mmu_tmp_fc = fc;
m_mmu_tmp_rw = 1;
m_mmu_tmp_sz = M68K_SZ_BYTE;
return m_read8(address);
}
inline uint32_t m68ki_read_16_fc(uint32_t address, uint32_t fc)
@ -662,6 +663,7 @@ inline uint32_t m68ki_read_16_fc(uint32_t address, uint32_t fc)
}
m_mmu_tmp_fc = fc;
m_mmu_tmp_rw = 1;
m_mmu_tmp_sz = M68K_SZ_WORD;
return m_read16(address);
}
inline uint32_t m68ki_read_32_fc(uint32_t address, uint32_t fc)
@ -672,6 +674,7 @@ inline uint32_t m68ki_read_32_fc(uint32_t address, uint32_t fc)
}
m_mmu_tmp_fc = fc;
m_mmu_tmp_rw = 1;
m_mmu_tmp_sz = M68K_SZ_LONG;
return m_read32(address);
}
@ -679,6 +682,7 @@ inline void m68ki_write_8_fc(uint32_t address, uint32_t fc, uint32_t value)
{
m_mmu_tmp_fc = fc;
m_mmu_tmp_rw = 0;
m_mmu_tmp_sz = M68K_SZ_BYTE;
m_write8(address, value);
}
inline void m68ki_write_16_fc(uint32_t address, uint32_t fc, uint32_t value)
@ -689,6 +693,7 @@ inline void m68ki_write_16_fc(uint32_t address, uint32_t fc, uint32_t value)
}
m_mmu_tmp_fc = fc;
m_mmu_tmp_rw = 0;
m_mmu_tmp_sz = M68K_SZ_WORD;
m_write16(address, value);
}
inline void m68ki_write_32_fc(uint32_t address, uint32_t fc, uint32_t value)
@ -699,6 +704,7 @@ inline void m68ki_write_32_fc(uint32_t address, uint32_t fc, uint32_t value)
}
m_mmu_tmp_fc = fc;
m_mmu_tmp_rw = 0;
m_mmu_tmp_sz = M68K_SZ_LONG;
m_write32(address, value);
}
@ -715,6 +721,7 @@ inline void m68ki_write_32_pd_fc(uint32_t address, uint32_t fc, uint32_t value)
}
m_mmu_tmp_fc = fc;
m_mmu_tmp_rw = 0;
m_mmu_tmp_sz = M68K_SZ_LONG;
m_write16(address+2, value>>16);
m_write16(address, value&0xffff);
}
@ -1219,6 +1226,7 @@ inline void m68ki_stack_frame_1010(uint32_t sr, uint32_t vector, uint32_t pc, ui
{
int orig_rw = m_mmu_tmp_buserror_rw; // this gets splatted by the following pushes, so save it now
int orig_fc = m_mmu_tmp_buserror_fc;
int orig_sz = m_mmu_tmp_buserror_sz;
/* INTERNAL REGISTER */
m68ki_push_16(0);
@ -1247,7 +1255,7 @@ inline void m68ki_stack_frame_1010(uint32_t sr, uint32_t vector, uint32_t pc, ui
/* SPECIAL STATUS REGISTER */
// set bit for: Rerun Faulted bus Cycle, or run pending prefetch
// set FC
m68ki_push_16(0x0100 | orig_fc | orig_rw<<6);
m68ki_push_16(0x0100 | orig_fc | orig_rw<<6 | orig_sz<<4);
/* INTERNAL REGISTER */
m68ki_push_16(0);
@ -1271,7 +1279,7 @@ inline void m68ki_stack_frame_1011(uint32_t sr, uint32_t vector, uint32_t pc, ui
{
int orig_rw = m_mmu_tmp_buserror_rw; // this gets splatted by the following pushes, so save it now
int orig_fc = m_mmu_tmp_buserror_fc;
int orig_sz = m_mmu_tmp_buserror_sz;
/* INTERNAL REGISTERS (18 words) */
m68ki_push_32(0);
m68ki_push_32(0);
@ -1322,7 +1330,7 @@ inline void m68ki_stack_frame_1011(uint32_t sr, uint32_t vector, uint32_t pc, ui
m68ki_push_16(0);
/* SPECIAL STATUS REGISTER */
m68ki_push_16(0x0100 | orig_fc | orig_rw<<6);
m68ki_push_16(0x0100 | orig_fc | (orig_rw<<6) | (orig_sz<<4));
/* INTERNAL REGISTER */
m68ki_push_16(0);

10
src/devices/cpu/m68000/m68kmmu.h
View File

@ -489,6 +489,7 @@ uint32_t pmmu_translate_addr_with_fc(uint32_t addr_in, uint8_t fc, uint8_t ptest
m_mmu_tmp_buserror_address = addr_in;
m_mmu_tmp_buserror_rw = m_mmu_tmp_rw;
m_mmu_tmp_buserror_fc = m_mmu_tmp_fc;
m_mmu_tmp_buserror_sz = m_mmu_tmp_sz;
}
}
else if (m_mmu_tmp_sr & M68K_MMU_SR_SUPERVISOR_ONLY)
@ -498,6 +499,7 @@ uint32_t pmmu_translate_addr_with_fc(uint32_t addr_in, uint8_t fc, uint8_t ptest
m_mmu_tmp_buserror_address = addr_in;
m_mmu_tmp_buserror_rw = m_mmu_tmp_rw;
m_mmu_tmp_buserror_fc = m_mmu_tmp_fc;
m_mmu_tmp_buserror_sz = m_mmu_tmp_sz;
}
}
else if ((m_mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT) && !m_mmu_tmp_rw)
@ -507,6 +509,7 @@ uint32_t pmmu_translate_addr_with_fc(uint32_t addr_in, uint8_t fc, uint8_t ptest
m_mmu_tmp_buserror_address = addr_in;
m_mmu_tmp_buserror_rw = m_mmu_tmp_rw;
m_mmu_tmp_buserror_fc = m_mmu_tmp_fc;
m_mmu_tmp_buserror_sz = m_mmu_tmp_sz;
}
}
@ -568,6 +571,7 @@ uint32_t pmmu_translate_addr_with_fc_040(uint32_t addr_in, uint8_t fc, uint8_t p
m_mmu_tmp_buserror_address = addr_in;
m_mmu_tmp_buserror_rw = m_mmu_tmp_rw;
m_mmu_tmp_buserror_fc = m_mmu_tmp_fc;
m_mmu_tmp_buserror_sz = m_mmu_tmp_sz;
}
}
@ -593,6 +597,7 @@ uint32_t pmmu_translate_addr_with_fc_040(uint32_t addr_in, uint8_t fc, uint8_t p
m_mmu_tmp_buserror_address = addr_in;
m_mmu_tmp_buserror_rw = m_mmu_tmp_rw;
m_mmu_tmp_buserror_fc = m_mmu_tmp_fc;
m_mmu_tmp_buserror_sz = m_mmu_tmp_sz;
}
}
@ -663,6 +668,7 @@ uint32_t pmmu_translate_addr_with_fc_040(uint32_t addr_in, uint8_t fc, uint8_t p
m_mmu_tmp_buserror_address = addr_in;
m_mmu_tmp_buserror_rw = m_mmu_tmp_rw;
m_mmu_tmp_buserror_fc = m_mmu_tmp_fc;
m_mmu_tmp_buserror_sz = m_mmu_tmp_sz;
}
return addr_in;
@ -677,6 +683,7 @@ uint32_t pmmu_translate_addr_with_fc_040(uint32_t addr_in, uint8_t fc, uint8_t p
m_mmu_tmp_buserror_address = addr_in;
m_mmu_tmp_buserror_rw = m_mmu_tmp_rw;
m_mmu_tmp_buserror_fc = m_mmu_tmp_fc;
m_mmu_tmp_buserror_sz = m_mmu_tmp_sz;
}
return addr_in;
@ -695,6 +702,7 @@ uint32_t pmmu_translate_addr_with_fc_040(uint32_t addr_in, uint8_t fc, uint8_t p
m_mmu_tmp_buserror_address = addr_in;
m_mmu_tmp_buserror_rw = m_mmu_tmp_rw;
m_mmu_tmp_buserror_fc = m_mmu_tmp_fc;
m_mmu_tmp_buserror_sz = m_mmu_tmp_sz;
}
}
@ -739,6 +747,7 @@ uint32_t pmmu_translate_addr_with_fc_040(uint32_t addr_in, uint8_t fc, uint8_t p
m_mmu_tmp_buserror_address = addr_in;
m_mmu_tmp_buserror_rw = m_mmu_tmp_rw;
m_mmu_tmp_buserror_fc = m_mmu_tmp_fc;
m_mmu_tmp_buserror_sz = m_mmu_tmp_sz;
}
return addr_in;
@ -755,6 +764,7 @@ uint32_t pmmu_translate_addr_with_fc_040(uint32_t addr_in, uint8_t fc, uint8_t p
m_mmu_tmp_buserror_address = addr_in;
m_mmu_tmp_buserror_rw = m_mmu_tmp_rw;
m_mmu_tmp_buserror_fc = m_mmu_tmp_fc;
m_mmu_tmp_buserror_sz = m_mmu_tmp_sz;
}
}