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WIP, small update (sync with master)

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This commit is contained in:
hap 2015-11-01 22:23:23 +01:00
parent 9e5ddc1310
commit 22408efde3
4 changed files with 15 additions and 25 deletions
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28
src/mame/drivers/champbas.c
View File

@ -103,7 +103,6 @@ CUSTOM_INPUT_MEMBER(champbas_state::champbas_watchdog_bit2)
return (0x10 - machine().get_vblank_watchdog_counter()) >> 2 & 1;
}
WRITE8_MEMBER(champbas_state::irq_enable_w)
{
m_irq_mask = data & 1;
@ -117,22 +116,17 @@ TIMER_DEVICE_CALLBACK_MEMBER(champbas_state::exctsccr_sound_irq)
m_audiocpu->set_input_line_and_vector(0, HOLD_LINE, 0xff);
}
// Champion Baseball has only one DAC
WRITE8_MEMBER(champbas_state::champbas_dac_w)
{
m_dac->write_signed8(data << 2);
}
WRITE8_MEMBER(champbas_state::champbas_dac1_w)
WRITE8_MEMBER(champbas_state::dac1_w)
{
m_dac1->write_signed8(data << 2);
}
WRITE8_MEMBER(champbas_state::champbas_dac2_w)
WRITE8_MEMBER(champbas_state::dac2_w)
{
m_dac2->write_signed8(data << 2);
}
/*************************************
*
* Protection handling
@ -157,7 +151,7 @@ WRITE8_MEMBER(champbas_state::champbas_mcu_halt_w)
/* champbja another protection */
READ8_MEMBER(champbas_state::champbja_alt_protection_r)
READ8_MEMBER(champbas_state::champbja_protection_r)
{
UINT8 data = 0;
/*
@ -253,7 +247,7 @@ static ADDRESS_MAP_START( champbas_main_map, AS_PROGRAM, 8, champbas_state )
AM_RANGE(0xa0c0, 0xa0c0) AM_WRITE(watchdog_reset_w)
/* champbja only */
AM_RANGE(0x6800, 0x68ff) AM_READ(champbja_alt_protection_r)
AM_RANGE(0x6800, 0x68ff) AM_READ(champbja_protection_r)
ADDRESS_MAP_END
static ADDRESS_MAP_START( exctsccrb_main_map, AS_PROGRAM, 8, champbas_state )
@ -313,7 +307,7 @@ static ADDRESS_MAP_START( champbas_sub_map, AS_PROGRAM, 8, champbas_state )
AM_RANGE(0x6000, 0x7fff) AM_READ(soundlatch_byte_r)
AM_RANGE(0x8000, 0x9fff) AM_WRITENOP // 4-bit return code to main CPU (not used)
AM_RANGE(0xa000, 0xbfff) AM_WRITE(soundlatch_clear_byte_w)
AM_RANGE(0xc000, 0xdfff) AM_WRITE(champbas_dac_w)
AM_RANGE(0xc000, 0xdfff) AM_WRITE(dac1_w)
AM_RANGE(0xe000, 0xe3ff) AM_MIRROR(0x1c00) AM_RAM
ADDRESS_MAP_END
@ -321,8 +315,8 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( exctsccr_sub_map, AS_PROGRAM, 8, champbas_state )
AM_RANGE(0x0000, 0x8fff) AM_ROM
AM_RANGE(0xa000, 0xa7ff) AM_RAM
AM_RANGE(0xc008, 0xc008) AM_WRITE(champbas_dac1_w)
AM_RANGE(0xc009, 0xc009) AM_WRITE(champbas_dac2_w)
AM_RANGE(0xc008, 0xc008) AM_WRITE(dac1_w)
AM_RANGE(0xc009, 0xc009) AM_WRITE(dac2_w)
AM_RANGE(0xc00c, 0xc00c) AM_WRITE(soundlatch_clear_byte_w)
AM_RANGE(0xc00d, 0xc00d) AM_READ(soundlatch_byte_r)
// AM_RANGE(0xc00f, 0xc00f) AM_WRITENOP /* ??? */
@ -432,7 +426,6 @@ static INPUT_PORTS_START( champbas )
PORT_DIPSETTING( 0x20, DEF_STR( Easy ) )
PORT_DIPSETTING( 0x00, DEF_STR( Hard ))
PORT_DIPUNKNOWN( 0x40, 0x00 )
PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, champbas_state, champbas_watchdog_bit2, NULL) // bit 2 of the watchdog counter
INPUT_PORTS_END
static INPUT_PORTS_START( exctsccr )
@ -458,7 +451,6 @@ static INPUT_PORTS_START( exctsccr )
PORT_DIPSETTING( 0x00, "2 Min." )
PORT_DIPSETTING( 0x60, "3 Min." )
PORT_DIPSETTING( 0x40, "4 Min." )
PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM_MEMBER(DEVICE_SELF, champbas_state, champbas_watchdog_bit2, NULL) // bit 2 of the watchdog counter
INPUT_PORTS_END
@ -640,7 +632,7 @@ static MACHINE_CONFIG_START( champbas, champbas_state )
MCFG_SOUND_ADD("aysnd", AY8910, XTAL_18_432MHz/12)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.30)
MCFG_DAC_ADD("dac")
MCFG_DAC_ADD("dac1")
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.70)
MACHINE_CONFIG_END
@ -749,7 +741,7 @@ static MACHINE_CONFIG_START( exctsccrb, champbas_state )
MCFG_SOUND_ADD("aysnd", AY8910, XTAL_18_432MHz/12)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.30)
MCFG_DAC_ADD("dac")
MCFG_DAC_ADD("dac1")
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.70)
MACHINE_CONFIG_END

9
src/mame/includes/champbas.h
View File

@ -17,7 +17,6 @@ public:
m_maincpu(*this, "maincpu"),
m_audiocpu(*this, "audiocpu"),
m_mcu(*this, "mcu"),
m_dac(*this, "dac"),
m_dac1(*this, "dac1"),
m_dac2(*this, "dac2"),
m_gfxdecode(*this, "gfxdecode"),
@ -31,7 +30,6 @@ public:
required_device<cpu_device> m_maincpu;
optional_device<cpu_device> m_audiocpu;
optional_device<cpu_device> m_mcu;
optional_device<dac_device> m_dac;
optional_device<dac_device> m_dac1;
optional_device<dac_device> m_dac2;
required_device<gfxdecode_device> m_gfxdecode;
@ -52,15 +50,14 @@ public:
DECLARE_WRITE8_MEMBER(irq_enable_w);
DECLARE_WRITE8_MEMBER(champbas_mcu_switch_w);
DECLARE_WRITE8_MEMBER(champbas_mcu_halt_w);
DECLARE_READ8_MEMBER(champbja_alt_protection_r);
DECLARE_READ8_MEMBER(champbja_protection_r);
DECLARE_WRITE8_MEMBER(champbas_bg_videoram_w);
DECLARE_WRITE8_MEMBER(champbas_gfxbank_w);
DECLARE_WRITE8_MEMBER(champbas_palette_bank_w);
DECLARE_WRITE8_MEMBER(champbas_flipscreen_w);
DECLARE_CUSTOM_INPUT_MEMBER(champbas_watchdog_bit2);
DECLARE_WRITE8_MEMBER(champbas_dac_w);
DECLARE_WRITE8_MEMBER(champbas_dac1_w);
DECLARE_WRITE8_MEMBER(champbas_dac2_w);
DECLARE_WRITE8_MEMBER(dac1_w);
DECLARE_WRITE8_MEMBER(dac2_w);
DECLARE_DRIVER_INIT(exctsccr);
DECLARE_DRIVER_INIT(champbas);
TILE_GET_INFO_MEMBER(champbas_get_bg_tile_info);

2
src/mame/machine/alpha8201.c
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@ -403,7 +403,7 @@ WRITE16_MEMBER(alpha_8201_device::mcu_d_w)
WRITE_LINE_MEMBER(alpha_8201_device::bus_dir_w)
{
// set bus direction to 0: external, 1: MCU side
// set RAM bus direction to 0: external, 1: MCU side
// selects one of two 74LS245 (octal bus transceiver) for databus, addressbus via
// a couple of 74LS157 (2-input multiplexer)
m_bus = (state) ? 1 : 0;

1
src/mame/video/champbas.c
View File

@ -168,6 +168,7 @@ WRITE8_MEMBER(champbas_state::champbas_bg_videoram_w)
WRITE8_MEMBER(champbas_state::champbas_gfxbank_w)
{
data &= 1;
if (m_gfx_bank != data)
{
m_gfx_bank = data;