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Basic hooks for Funky Ball, it basically follows Area 51 hooks

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This commit is contained in:
Angelo Salese 2012-01-02 01:19:18 +00:00
parent bfd71f45a2
commit 22f58b0c13
2 changed files with 421 additions and 28 deletions
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439
src/mame/drivers/funkball.c
View File

@ -1,5 +1,5 @@
// dgPIX 'VRender 2 Beta Rev4' hardware // dgPIX 'VRender 2 Beta Rev4' hardware
// MEDIAGX CPU + 3dFX VooDoo chipset // funkball CPU + 3dFX VooDoo chipset
/*************************************************************************** /***************************************************************************
@ -60,60 +60,453 @@ Notes:
***************************************************************************/ ***************************************************************************/
#define ADDRESS_MAP_MODERN
#include "emu.h" #include "emu.h"
#include "cpu/i386/i386.h" #include "cpu/i386/i386.h"
#include "memconv.h" #include "memconv.h"
#include "devconv.h" #include "devconv.h"
#include "machine/8237dma.h"
#include "machine/pic8259.h"
#include "machine/pit8253.h"
#include "machine/mc146818.h"
#include "machine/pcshare.h"
#include "machine/pci.h"
#include "machine/8042kbdc.h"
#include "machine/pckeybrd.h"
#include "machine/idectrl.h"
class funkball_state : public driver_device class funkball_state : public driver_device
{ {
public: public:
funkball_state(const machine_config &mconfig, device_type type, const char *tag) funkball_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag) { } : driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_pit8254(*this, "pit8254"),
m_dma8237_1(*this, "dma8237_1"),
m_dma8237_2(*this, "dma8237_2"),
m_pic8259_1(*this, "pic8259_1"),
m_pic8259_2(*this, "pic8259_2")
{ }
int m_dma_channel;
UINT8 m_dma_offset[2][4];
UINT8 m_at_pages[0x10];
UINT8 m_funkball_config_reg_sel;
UINT8 m_funkball_config_regs[256];
UINT32 m_cx5510_regs[256/4];
// devices
required_device<cpu_device> m_maincpu;
required_device<pit8254_device> m_pit8254;
required_device<i8237_device> m_dma8237_1;
required_device<i8237_device> m_dma8237_2;
required_device<pic8259_device> m_pic8259_1;
required_device<pic8259_device> m_pic8259_2;
DECLARE_READ8_MEMBER( get_slave_ack );
}; };
static UINT32 cx5510_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask)
static VIDEO_START(funkball)
{ {
funkball_state *state = busdevice->machine().driver_data<funkball_state>();
//mame_printf_debug("CX5510: PCI read %d, %02X, %08X\n", function, reg, mem_mask);
switch (reg)
{
case 0: return 0x00001078;
}
return state->m_cx5510_regs[reg/4];
} }
static SCREEN_UPDATE(funkball) static void cx5510_pci_w(device_t *busdevice, device_t *device, int function, int reg, UINT32 data, UINT32 mem_mask)
{ {
return 0; funkball_state *state = busdevice->machine().driver_data<funkball_state>();
//mame_printf_debug("CX5510: PCI write %d, %02X, %08X, %08X\n", function, reg, data, mem_mask);
COMBINE_DATA(state->m_cx5510_regs + (reg/4));
} }
static ADDRESS_MAP_START(funkball_map, AS_PROGRAM, 32) static READ32_DEVICE_HANDLER( ide_r )
AM_RANGE(0xffff0000, 0xffffffff) AM_ROM AM_REGION("user1", 0) /* System BIOS */ {
return ide_controller32_r(device, 0x1f0/4 + offset, mem_mask);
}
static WRITE32_DEVICE_HANDLER( ide_w )
{
ide_controller32_w(device, 0x1f0/4 + offset, data, mem_mask);
}
static READ32_DEVICE_HANDLER( fdc_r )
{
return ide_controller32_r(device, 0x3f0/4 + offset, mem_mask);
}
static WRITE32_DEVICE_HANDLER( fdc_w )
{
//mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
ide_controller32_w(device, 0x3f0/4 + offset, data, mem_mask);
}
static READ8_HANDLER(at_page8_r)
{
funkball_state *state = space->machine().driver_data<funkball_state>();
UINT8 data = state->m_at_pages[offset % 0x10];
switch(offset % 8) {
case 1:
data = state->m_dma_offset[(offset / 8) & 1][2];
break;
case 2:
data = state->m_dma_offset[(offset / 8) & 1][3];
break;
case 3:
data = state->m_dma_offset[(offset / 8) & 1][1];
break;
case 7:
data = state->m_dma_offset[(offset / 8) & 1][0];
break;
}
return data;
}
static WRITE8_HANDLER(at_page8_w)
{
funkball_state *state = space->machine().driver_data<funkball_state>();
state->m_at_pages[offset % 0x10] = data;
switch(offset % 8) {
case 1:
state->m_dma_offset[(offset / 8) & 1][2] = data;
break;
case 2:
state->m_dma_offset[(offset / 8) & 1][3] = data;
break;
case 3:
state->m_dma_offset[(offset / 8) & 1][1] = data;
break;
case 7:
state->m_dma_offset[(offset / 8) & 1][0] = data;
break;
}
}
static READ32_HANDLER(at_page32_r)
{
return read32le_with_read8_handler(at_page8_r, space, offset, mem_mask);
}
static WRITE32_HANDLER(at_page32_w)
{
write32le_with_write8_handler(at_page8_w, space, offset, data, mem_mask);
}
static READ8_DEVICE_HANDLER(at_dma8237_2_r)
{
return i8237_r(device, offset / 2);
}
static WRITE8_DEVICE_HANDLER(at_dma8237_2_w)
{
i8237_w(device, offset / 2, data);
}
static READ32_DEVICE_HANDLER(at32_dma8237_2_r)
{
return read32le_with_read8_device_handler(at_dma8237_2_r, device, offset, mem_mask);
}
static WRITE32_DEVICE_HANDLER(at32_dma8237_2_w)
{
write32le_with_write8_device_handler(at_dma8237_2_w, device, offset, data, mem_mask);
}
static WRITE_LINE_DEVICE_HANDLER( pc_dma_hrq_changed )
{
cputag_set_input_line(device->machine(), "maincpu", INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
/* Assert HLDA */
i8237_hlda_w( device, state );
}
static READ8_HANDLER( pc_dma_read_byte )
{
funkball_state *state = space->machine().driver_data<funkball_state>();
offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16)
& 0xFF0000;
return space->read_byte(page_offset + offset);
}
static WRITE8_HANDLER( pc_dma_write_byte )
{
funkball_state *state = space->machine().driver_data<funkball_state>();
offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16)
& 0xFF0000;
space->write_byte(page_offset + offset, data);
}
static void set_dma_channel(device_t *device, int channel, int state)
{
funkball_state *drvstate = device->machine().driver_data<funkball_state>();
if (!state) drvstate->m_dma_channel = channel;
}
static WRITE_LINE_DEVICE_HANDLER( pc_dack0_w ) { set_dma_channel(device, 0, state); }
static WRITE_LINE_DEVICE_HANDLER( pc_dack1_w ) { set_dma_channel(device, 1, state); }
static WRITE_LINE_DEVICE_HANDLER( pc_dack2_w ) { set_dma_channel(device, 2, state); }
static WRITE_LINE_DEVICE_HANDLER( pc_dack3_w ) { set_dma_channel(device, 3, state); }
static I8237_INTERFACE( dma8237_1_config )
{
DEVCB_LINE(pc_dma_hrq_changed),
DEVCB_NULL,
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_byte),
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_byte),
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_LINE(pc_dack0_w), DEVCB_LINE(pc_dack1_w), DEVCB_LINE(pc_dack2_w), DEVCB_LINE(pc_dack3_w) }
};
static I8237_INTERFACE( dma8237_2_config )
{
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
DEVCB_NULL,
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
};
static UINT8 funkball_config_reg_r(device_t *device)
{
funkball_state *state = device->machine().driver_data<funkball_state>();
//mame_printf_debug("funkball_config_reg_r %02X\n", funkball_config_reg_sel);
return state->m_funkball_config_regs[state->m_funkball_config_reg_sel];
}
static void funkball_config_reg_w(device_t *device, UINT8 data)
{
funkball_state *state = device->machine().driver_data<funkball_state>();
//mame_printf_debug("funkball_config_reg_w %02X, %02X\n", funkball_config_reg_sel, data);
state->m_funkball_config_regs[state->m_funkball_config_reg_sel] = data;
}
static READ8_DEVICE_HANDLER( io20_r )
{
UINT8 r = 0;
// 0x22, 0x23, Cyrix configuration registers
if (offset == 0x02)
{
}
else if (offset == 0x03)
{
r = funkball_config_reg_r(device);
}
else
{
r = pic8259_r(device, offset);
}
return r;
}
static WRITE8_DEVICE_HANDLER( io20_w )
{
funkball_state *state = device->machine().driver_data<funkball_state>();
// 0x22, 0x23, Cyrix configuration registers
if (offset == 0x02)
{
state->m_funkball_config_reg_sel = data;
}
else if (offset == 0x03)
{
funkball_config_reg_w(device, data);
}
else
{
pic8259_w(device, offset, data);
}
}
static ADDRESS_MAP_START(funkball_map, AS_PROGRAM, 32, funkball_state)
AM_RANGE(0x00000000, 0x0009ffff) AM_RAM
AM_RANGE(0x000a0000, 0x000bffff) AM_RAM
// AM_RANGE(0x000c0000, 0x000c7fff) AM_ROM AM_REGION("video_bios", 0) /* System BIOS */
AM_RANGE(0x000f0000, 0x000fffff) AM_ROM AM_REGION("bios", 0) AM_WRITENOP /* System BIOS */
AM_RANGE(0x00100000, 0x01ffffff) AM_RAM
AM_RANGE(0x40010e00, 0x40010eff) AM_RAM
AM_RANGE(0xffff0000, 0xffffffff) AM_ROM AM_REGION("bios", 0) /* System BIOS */
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START(funkball_io, AS_IO, 32) static ADDRESS_MAP_START(funkball_io, AS_IO, 32, funkball_state)
AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8_LEGACY("dma8237_1", i8237_r, i8237_w, 0xffffffff)
AM_RANGE(0x0020, 0x003f) AM_DEVREADWRITE8_LEGACY("pic8259_1", io20_r, io20_w, 0xffffffff)
AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE8_LEGACY("pit8254", pit8253_r, pit8253_w, 0xffffffff)
AM_RANGE(0x0060, 0x006f) AM_READWRITE_LEGACY(kbdc8042_32le_r, kbdc8042_32le_w)
AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("rtc", mc146818_device, read, write, 0xffffffff) /* todo: nvram (CMOS Setup Save)*/
AM_RANGE(0x0080, 0x009f) AM_READWRITE_LEGACY(at_page32_r, at_page32_w)
AM_RANGE(0x00a0, 0x00bf) AM_DEVREADWRITE8_LEGACY("pic8259_2", pic8259_r, pic8259_w, 0xffffffff)
AM_RANGE(0x00c0, 0x00df) AM_DEVREADWRITE_LEGACY("dma8237_2", at32_dma8237_2_r, at32_dma8237_2_w)
AM_RANGE(0x00e8, 0x00ef) AM_NOP
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE_LEGACY("ide", ide_r, ide_w)
// AM_RANGE(0x0350, 0x035f) AM_NOP
AM_RANGE(0x03f0, 0x03ff) AM_DEVREADWRITE_LEGACY("ide", fdc_r, fdc_w)
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE_LEGACY("pcibus", pci_32le_r, pci_32le_w)
ADDRESS_MAP_END ADDRESS_MAP_END
static INPUT_PORTS_START( funkball ) static const struct pit8253_config funkball_pit8254_config =
INPUT_PORTS_END {
{
{
4772720/4, /* heartbeat IRQ */
DEVCB_NULL,
DEVCB_DEVICE_LINE("pic8259_1", pic8259_ir0_w)
}, {
4772720/4, /* dram refresh */
DEVCB_NULL,
DEVCB_NULL
}, {
4772720/4, /* pio port c pin 4, and speaker polling enough */
DEVCB_NULL,
DEVCB_NULL
}
}
};
static WRITE_LINE_DEVICE_HANDLER( funkball_pic8259_1_set_int_line )
{
funkball_state *drvstate = device->machine().driver_data<funkball_state>();
device_set_input_line(drvstate->m_maincpu, 0, state ? HOLD_LINE : CLEAR_LINE);
}
READ8_MEMBER( funkball_state::get_slave_ack )
{
if (offset==2) { // IRQ = 2
logerror("pic8259_slave_ACK!\n");
return pic8259_acknowledge(m_pic8259_2);
}
return 0x00;
}
static const struct pic8259_interface funkball_pic8259_1_config =
{
DEVCB_LINE(funkball_pic8259_1_set_int_line),
DEVCB_LINE_VCC,
DEVCB_MEMBER(funkball_state,get_slave_ack)
};
static const struct pic8259_interface funkball_pic8259_2_config =
{
DEVCB_DEVICE_LINE("pic8259_1", pic8259_ir2_w),
DEVCB_LINE_GND,
DEVCB_NULL
};
static void set_gate_a20(running_machine &machine, int a20)
{
funkball_state *state = machine.driver_data<funkball_state>();
device_set_input_line(state->m_maincpu, INPUT_LINE_A20, a20);
}
static void keyboard_interrupt(running_machine &machine, int state)
{
funkball_state *drvstate = machine.driver_data<funkball_state>();
pic8259_ir1_w(drvstate->m_pic8259_1, state);
}
static int funkball_get_out2(running_machine &machine)
{
funkball_state *state = machine.driver_data<funkball_state>();
return pit8253_get_output(state->m_pit8254, 2 );
}
static const struct kbdc8042_interface at8042 =
{
KBDC8042_AT386, set_gate_a20, keyboard_interrupt, NULL, funkball_get_out2
};
static void funkball_set_keyb_int(running_machine &machine, int state)
{
funkball_state *drvstate = machine.driver_data<funkball_state>();
pic8259_ir1_w(drvstate->m_pic8259_1, state);
}
static IRQ_CALLBACK(irq_callback)
{
funkball_state *state = device->machine().driver_data<funkball_state>();
return pic8259_acknowledge( state->m_pic8259_1);
}
static void ide_interrupt(device_t *device, int state)
{
funkball_state *drvstate = device->machine().driver_data<funkball_state>();
pic8259_ir6_w(drvstate->m_pic8259_2, state);
}
static MACHINE_START( funkball )
{
funkball_state *state = machine.driver_data<funkball_state>();
init_pc_common(machine, PCCOMMON_KEYBOARD_AT, funkball_set_keyb_int);
device_set_irq_callback(state->m_maincpu, irq_callback);
kbdc8042_init(machine, &at8042);
}
static MACHINE_RESET( funkball )
{
// ...
}
static MACHINE_CONFIG_START( funkball, funkball_state ) static MACHINE_CONFIG_START( funkball, funkball_state )
MCFG_CPU_ADD("maincpu", MEDIAGX, 66666666*3.5) MCFG_CPU_ADD("maincpu", MEDIAGX, 66666666*3.5)
MCFG_CPU_PROGRAM_MAP(funkball_map) MCFG_CPU_PROGRAM_MAP(funkball_map)
MCFG_CPU_IO_MAP(funkball_io) MCFG_CPU_IO_MAP(funkball_io)
/* video hardware */ MCFG_MACHINE_START(funkball)
MCFG_SCREEN_ADD("screen", RASTER) MCFG_MACHINE_RESET(funkball)
MCFG_SCREEN_REFRESH_RATE(60)
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
MCFG_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
MCFG_SCREEN_SIZE(640, 480)
MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 199)
MCFG_SCREEN_UPDATE(funkball)
MCFG_PALETTE_LENGTH(16)
MCFG_VIDEO_START(funkball) MCFG_PIT8254_ADD( "pit8254", funkball_pit8254_config )
MCFG_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, dma8237_1_config )
MCFG_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
MCFG_PIC8259_ADD( "pic8259_1", funkball_pic8259_1_config )
MCFG_PIC8259_ADD( "pic8259_2", funkball_pic8259_2_config )
MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
MCFG_PCI_BUS_ADD("pcibus", 0)
MCFG_PCI_BUS_DEVICE(18, NULL, cx5510_pci_r, cx5510_pci_w)
MCFG_IDE_CONTROLLER_ADD("ide", ide_interrupt)
/* video hardware */
// ...
MACHINE_CONFIG_END MACHINE_CONFIG_END
ROM_START( funkball ) ROM_START( funkball )
ROM_REGION32_LE(0x10000, "user1", 0) ROM_REGION32_LE(0x10000, "bios", ROMREGION_ERASEFF)
ROM_LOAD( "512k-epr.u62", 0x000000, 0x010000, CRC(cced894a) SHA1(298c81716e375da4b7215f3e588a45ca3ea7e35c) ) ROM_LOAD( "512k-epr.u62", 0x000000, 0x010000, CRC(cced894a) SHA1(298c81716e375da4b7215f3e588a45ca3ea7e35c) )
ROM_REGION(0x400000, "user2", 0) ROM_REGION(0x400000, "user2", 0)
@ -125,4 +518,4 @@ ROM_START( funkball )
ROM_END ROM_END
GAME(1998, funkball, 0, funkball, funkball, 0, ROT0, "dgPIX Entertainment Inc.", "Funky Ball", GAME_IS_SKELETON) GAME(1998, funkball, 0, funkball, at_keyboard, 0, ROT0, "dgPIX Entertainment Inc.", "Funky Ball", GAME_IS_SKELETON)

10
src/mame/drivers/midqslvr.c
View File

@ -131,7 +131,7 @@ static void mxtc_config_w(device_t *busdevice, device_t *device, int function, i
if (data & 0x10) // enable RAM access to region 0xf0000 - 0xfffff if (data & 0x10) // enable RAM access to region 0xf0000 - 0xfffff
memory_set_bankptr(busdevice->machine(), "bios_bank", state->m_bios_ram); memory_set_bankptr(busdevice->machine(), "bios_bank", state->m_bios_ram);
else // disable RAM access (reads go to BIOS ROM) else // disable RAM access (reads go to BIOS ROM)
memory_set_bankptr(busdevice->machine(), "bios_bank", busdevice->machine().region("bios")->base() + 0x10000); memory_set_bankptr(busdevice->machine(), "bios_bank", busdevice->machine().region("bios")->base() + 0x70000);
break; break;
} }
case 0x5a: // PAM1 case 0x5a: // PAM1
@ -153,12 +153,12 @@ static void mxtc_config_w(device_t *busdevice, device_t *device, int function, i
if (data & 0x1) if (data & 0x1)
memory_set_bankptr(busdevice->machine(), "bios_ext1", state->m_bios_ext1_ram); memory_set_bankptr(busdevice->machine(), "bios_ext1", state->m_bios_ext1_ram);
else else
memory_set_bankptr(busdevice->machine(), "bios_ext1", busdevice->machine().region("bios")->base() + 0); memory_set_bankptr(busdevice->machine(), "bios_ext1", busdevice->machine().region("bios")->base() + 0x60000);
if (data & 0x10) if (data & 0x10)
memory_set_bankptr(busdevice->machine(), "bios_ext2", state->m_bios_ext2_ram); memory_set_bankptr(busdevice->machine(), "bios_ext2", state->m_bios_ext2_ram);
else else
memory_set_bankptr(busdevice->machine(), "bios_ext2", busdevice->machine().region("bios")->base() + 0x4000); memory_set_bankptr(busdevice->machine(), "bios_ext2", busdevice->machine().region("bios")->base() + 0x64000);
break; break;
} }
@ -167,12 +167,12 @@ static void mxtc_config_w(device_t *busdevice, device_t *device, int function, i
if (data & 0x1) if (data & 0x1)
memory_set_bankptr(busdevice->machine(), "bios_ext3", state->m_bios_ext3_ram); memory_set_bankptr(busdevice->machine(), "bios_ext3", state->m_bios_ext3_ram);
else else
memory_set_bankptr(busdevice->machine(), "bios_ext3", busdevice->machine().region("bios")->base() + 0x8000); memory_set_bankptr(busdevice->machine(), "bios_ext3", busdevice->machine().region("bios")->base() + 0x68000);
if (data & 0x10) if (data & 0x10)
memory_set_bankptr(busdevice->machine(), "bios_ext4", state->m_bios_ext4_ram); memory_set_bankptr(busdevice->machine(), "bios_ext4", state->m_bios_ext4_ram);
else else
memory_set_bankptr(busdevice->machine(), "bios_ext4", busdevice->machine().region("bios")->base() + 0xc000); memory_set_bankptr(busdevice->machine(), "bios_ext4", busdevice->machine().region("bios")->base() + 0x6c000);
break; break;
} }