mirror of
https://github.com/holub/mame
synced 2025-07-01 08:18:59 +03:00
fmtowns.cpp, hp9k_3xx.cpp: Eliminate machine().device (nw)
This commit is contained in:
parent
89550d3b19
commit
2340ce2a45
@ -492,12 +492,12 @@ READ8_MEMBER(towns_state::towns_floppy_r)
|
|||||||
{
|
{
|
||||||
case 1:
|
case 1:
|
||||||
ret |= 0x0c;
|
ret |= 0x0c;
|
||||||
if(m_flop0->get_device()->exists())
|
if(m_flop[0]->get_device()->exists())
|
||||||
ret |= 0x03;
|
ret |= 0x03;
|
||||||
break;
|
break;
|
||||||
case 2:
|
case 2:
|
||||||
ret |= 0x0c;
|
ret |= 0x0c;
|
||||||
if(m_flop1->get_device()->exists())
|
if(m_flop[1]->get_device()->exists())
|
||||||
ret |= 0x03;
|
ret |= 0x03;
|
||||||
break;
|
break;
|
||||||
case 3:
|
case 3:
|
||||||
@ -510,9 +510,9 @@ READ8_MEMBER(towns_state::towns_floppy_r)
|
|||||||
case 0x0e: // DRVCHG
|
case 0x0e: // DRVCHG
|
||||||
logerror("FDC: read from offset 0x0e\n");
|
logerror("FDC: read from offset 0x0e\n");
|
||||||
if(m_towns_selected_drive == 1)
|
if(m_towns_selected_drive == 1)
|
||||||
return m_flop0->get_device()->dskchg_r();
|
return m_flop[0]->get_device()->dskchg_r();
|
||||||
if(m_towns_selected_drive == 2)
|
if(m_towns_selected_drive == 2)
|
||||||
return m_flop1->get_device()->dskchg_r();
|
return m_flop[1]->get_device()->dskchg_r();
|
||||||
return 0x00;
|
return 0x00;
|
||||||
default:
|
default:
|
||||||
logerror("FDC: read from invalid or unimplemented register %02x\n",offset);
|
logerror("FDC: read from invalid or unimplemented register %02x\n",offset);
|
||||||
@ -522,7 +522,7 @@ READ8_MEMBER(towns_state::towns_floppy_r)
|
|||||||
|
|
||||||
WRITE8_MEMBER(towns_state::towns_floppy_w)
|
WRITE8_MEMBER(towns_state::towns_floppy_w)
|
||||||
{
|
{
|
||||||
floppy_image_device* sel[4] = { m_flop0->get_device(), m_flop1->get_device(), nullptr, nullptr };
|
floppy_image_device* sel[4] = { m_flop[0]->get_device(), m_flop[1]->get_device(), nullptr, nullptr };
|
||||||
|
|
||||||
switch(offset)
|
switch(offset)
|
||||||
{
|
{
|
||||||
@ -1147,7 +1147,7 @@ WRITE8_MEMBER(towns_state::towns_pad_mask_w)
|
|||||||
READ8_MEMBER( towns_state::towns_cmos_low_r )
|
READ8_MEMBER( towns_state::towns_cmos_low_r )
|
||||||
{
|
{
|
||||||
if(m_towns_mainmem_enable != 0)
|
if(m_towns_mainmem_enable != 0)
|
||||||
return m_messram->pointer()[offset + 0xd8000];
|
return m_ram->pointer()[offset + 0xd8000];
|
||||||
|
|
||||||
if(m_nvram)
|
if(m_nvram)
|
||||||
return m_nvram[offset];
|
return m_nvram[offset];
|
||||||
@ -1158,7 +1158,7 @@ READ8_MEMBER( towns_state::towns_cmos_low_r )
|
|||||||
WRITE8_MEMBER( towns_state::towns_cmos_low_w )
|
WRITE8_MEMBER( towns_state::towns_cmos_low_w )
|
||||||
{
|
{
|
||||||
if(m_towns_mainmem_enable != 0)
|
if(m_towns_mainmem_enable != 0)
|
||||||
m_messram->pointer()[offset+0xd8000] = data;
|
m_ram->pointer()[offset+0xd8000] = data;
|
||||||
else
|
else
|
||||||
if(m_nvram)
|
if(m_nvram)
|
||||||
m_nvram[offset] = data;
|
m_nvram[offset] = data;
|
||||||
@ -1188,42 +1188,42 @@ void towns_state::towns_update_video_banks(address_space& space)
|
|||||||
|
|
||||||
if(m_towns_mainmem_enable != 0) // first MB is RAM
|
if(m_towns_mainmem_enable != 0) // first MB is RAM
|
||||||
{
|
{
|
||||||
// membank(1)->set_base(m_messram->pointer()+0xc0000);
|
// membank(1)->set_base(m_ram->pointer()+0xc0000);
|
||||||
// membank(2)->set_base(m_messram->pointer()+0xc8000);
|
// membank(2)->set_base(m_ram->pointer()+0xc8000);
|
||||||
// membank(3)->set_base(m_messram->pointer()+0xc9000);
|
// membank(3)->set_base(m_ram->pointer()+0xc9000);
|
||||||
// membank(4)->set_base(m_messram->pointer()+0xca000);
|
// membank(4)->set_base(m_ram->pointer()+0xca000);
|
||||||
// membank(5)->set_base(m_messram->pointer()+0xca000);
|
// membank(5)->set_base(m_ram->pointer()+0xca000);
|
||||||
// membank(10)->set_base(m_messram->pointer()+0xca800);
|
// membank(10)->set_base(m_ram->pointer()+0xca800);
|
||||||
m_bank_cb000_r->set_base(m_messram->pointer()+0xcb000);
|
m_bank_cb000_r->set_base(m_ram->pointer()+0xcb000);
|
||||||
m_bank_cb000_w->set_base(m_messram->pointer()+0xcb000);
|
m_bank_cb000_w->set_base(m_ram->pointer()+0xcb000);
|
||||||
if(m_towns_system_port & 0x02)
|
if(m_towns_system_port & 0x02)
|
||||||
m_bank_f8000_r->set_base(m_messram->pointer()+0xf8000);
|
m_bank_f8000_r->set_base(m_ram->pointer()+0xf8000);
|
||||||
else
|
else
|
||||||
m_bank_f8000_r->set_base(ROM+0x238000);
|
m_bank_f8000_r->set_base(ROM+0x238000);
|
||||||
m_bank_f8000_w->set_base(m_messram->pointer()+0xf8000);
|
m_bank_f8000_w->set_base(m_ram->pointer()+0xf8000);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
else // enable I/O ports and VRAM
|
else // enable I/O ports and VRAM
|
||||||
{
|
{
|
||||||
// membank(1)->set_base(towns_gfxvram+(towns_vram_rplane*0x8000));
|
// membank(1)->set_base(towns_gfxvram+(towns_vram_rplane*0x8000));
|
||||||
// membank(2)->set_base(towns_txtvram);
|
// membank(2)->set_base(towns_txtvram);
|
||||||
// membank(3)->set_base(m_messram->pointer()+0xc9000);
|
// membank(3)->set_base(m_ram->pointer()+0xc9000);
|
||||||
// if(towns_ankcg_enable != 0)
|
// if(towns_ankcg_enable != 0)
|
||||||
// membank(4)->set_base(ROM+0x180000+0x3d000); // ANK CG 8x8
|
// membank(4)->set_base(ROM+0x180000+0x3d000); // ANK CG 8x8
|
||||||
// else
|
// else
|
||||||
// membank(4)->set_base(towns_txtvram+0x2000);
|
// membank(4)->set_base(towns_txtvram+0x2000);
|
||||||
// membank(5)->set_base(towns_txtvram+0x2000);
|
// membank(5)->set_base(towns_txtvram+0x2000);
|
||||||
// membank(10)->set_base(m_messram->pointer()+0xca800);
|
// membank(10)->set_base(m_ram->pointer()+0xca800);
|
||||||
if(m_towns_ankcg_enable != 0)
|
if(m_towns_ankcg_enable != 0)
|
||||||
m_bank_cb000_r->set_base(ROM+0x180000+0x3d800); // ANK CG 8x16
|
m_bank_cb000_r->set_base(ROM+0x180000+0x3d800); // ANK CG 8x16
|
||||||
else
|
else
|
||||||
m_bank_cb000_r->set_base(m_messram->pointer()+0xcb000);
|
m_bank_cb000_r->set_base(m_ram->pointer()+0xcb000);
|
||||||
m_bank_cb000_w->set_base(m_messram->pointer()+0xcb000);
|
m_bank_cb000_w->set_base(m_ram->pointer()+0xcb000);
|
||||||
if(m_towns_system_port & 0x02)
|
if(m_towns_system_port & 0x02)
|
||||||
m_bank_f8000_r->set_base(m_messram->pointer()+0xf8000);
|
m_bank_f8000_r->set_base(m_ram->pointer()+0xf8000);
|
||||||
else
|
else
|
||||||
m_bank_f8000_r->set_base(ROM+0x238000);
|
m_bank_f8000_r->set_base(ROM+0x238000);
|
||||||
m_bank_f8000_w->set_base(m_messram->pointer()+0xf8000);
|
m_bank_f8000_w->set_base(m_ram->pointer()+0xf8000);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -2658,7 +2658,7 @@ void towns_state::driver_start()
|
|||||||
memset(&m_towns_cd,0,sizeof(struct towns_cdrom_controller));
|
memset(&m_towns_cd,0,sizeof(struct towns_cdrom_controller));
|
||||||
m_towns_cd.status = 0x01; // CDROM controller ready
|
m_towns_cd.status = 0x01; // CDROM controller ready
|
||||||
m_towns_cd.buffer_ptr = -1;
|
m_towns_cd.buffer_ptr = -1;
|
||||||
m_towns_cd.read_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(towns_state::towns_cdrom_read_byte),this), (void*)machine().device("dma_1"));
|
m_towns_cd.read_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(towns_state::towns_cdrom_read_byte),this), (void*)m_dma_1.target());
|
||||||
|
|
||||||
save_pointer(m_video.towns_crtc_reg,"CRTC registers",32);
|
save_pointer(m_video.towns_crtc_reg,"CRTC registers",32);
|
||||||
save_pointer(m_video.towns_video_reg,"Video registers",2);
|
save_pointer(m_video.towns_video_reg,"Video registers",2);
|
||||||
@ -2675,17 +2675,13 @@ void marty_state::driver_start()
|
|||||||
|
|
||||||
void towns_state::machine_start()
|
void towns_state::machine_start()
|
||||||
{
|
{
|
||||||
m_flop0->get_device()->set_rpm(360);
|
m_flop[0]->get_device()->set_rpm(360);
|
||||||
m_flop1->get_device()->set_rpm(360);
|
m_flop[1]->get_device()->set_rpm(360);
|
||||||
}
|
}
|
||||||
|
|
||||||
void towns_state::machine_reset()
|
void towns_state::machine_reset()
|
||||||
{
|
{
|
||||||
address_space &program = m_maincpu->space(AS_PROGRAM);
|
address_space &program = m_maincpu->space(AS_PROGRAM);
|
||||||
m_messram = m_ram;
|
|
||||||
m_cdrom = machine().device<cdrom_image_device>("cdrom");
|
|
||||||
m_cdda = machine().device<cdda_device>("cdda");
|
|
||||||
m_scsi = machine().device<fmscsi_device>("fmscsi");
|
|
||||||
m_ftimer = 0x00;
|
m_ftimer = 0x00;
|
||||||
m_freerun_timer = 0x00;
|
m_freerun_timer = 0x00;
|
||||||
m_nmi_mask = 0x00;
|
m_nmi_mask = 0x00;
|
||||||
|
@ -356,13 +356,13 @@ READ16_MEMBER(hp9k3xx_state::buserror16_r)
|
|||||||
{
|
{
|
||||||
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
|
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
|
||||||
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
|
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
|
||||||
m_lastpc = machine().device<cpu_device>("maincpu")->pc();
|
m_lastpc = m_maincpu->pc();
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
WRITE16_MEMBER(hp9k3xx_state::buserror16_w)
|
WRITE16_MEMBER(hp9k3xx_state::buserror16_w)
|
||||||
{
|
{
|
||||||
if (m_lastpc == machine().device<cpu_device>("maincpu")->pc()) {
|
if (m_lastpc == m_maincpu->pc()) {
|
||||||
logerror("%s: ignoring r-m-w double bus error\n", __FUNCTION__);
|
logerror("%s: ignoring r-m-w double bus error\n", __FUNCTION__);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@ -375,13 +375,13 @@ READ32_MEMBER(hp9k3xx_state::buserror_r)
|
|||||||
{
|
{
|
||||||
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
|
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
|
||||||
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
|
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
|
||||||
m_lastpc = machine().device<cpu_device>("maincpu")->pc();
|
m_lastpc = m_maincpu->pc();
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
WRITE32_MEMBER(hp9k3xx_state::buserror_w)
|
WRITE32_MEMBER(hp9k3xx_state::buserror_w)
|
||||||
{
|
{
|
||||||
if (m_lastpc == machine().device<cpu_device>("maincpu")->pc()) {
|
if (m_lastpc == m_maincpu->pc()) {
|
||||||
logerror("%s: ignoring r-m-w double bus error\n", __FUNCTION__);
|
logerror("%s: ignoring r-m-w double bus error\n", __FUNCTION__);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
@ -99,13 +99,16 @@ class towns_state : public driver_device
|
|||||||
, m_palette16(*this, "palette16_%u", 0U)
|
, m_palette16(*this, "palette16_%u", 0U)
|
||||||
, m_ram(*this, RAM_TAG)
|
, m_ram(*this, RAM_TAG)
|
||||||
, m_fdc(*this, "fdc")
|
, m_fdc(*this, "fdc")
|
||||||
, m_flop0(*this, "fdc:0")
|
, m_flop(*this, "fdc:%u", 0U)
|
||||||
, m_flop1(*this, "fdc:1")
|
|
||||||
, m_icmemcard(*this, "icmemcard")
|
, m_icmemcard(*this, "icmemcard")
|
||||||
, m_i8251(*this, "i8251")
|
, m_i8251(*this, "i8251")
|
||||||
, m_rs232(*this, "rs232c")
|
, m_rs232(*this, "rs232c")
|
||||||
, m_screen(*this, "screen")
|
, m_screen(*this, "screen")
|
||||||
, m_rtc(*this, "rtc58321")
|
, m_rtc(*this, "rtc58321")
|
||||||
|
, m_dma_1(*this, "dma_1")
|
||||||
|
, m_cdrom(*this, "cdrom")
|
||||||
|
, m_cdda(*this, "cdda")
|
||||||
|
, m_scsi(*this, "fmscsi")
|
||||||
, m_bank_cb000_r(*this, "bank_cb000_r")
|
, m_bank_cb000_r(*this, "bank_cb000_r")
|
||||||
, m_bank_cb000_w(*this, "bank_cb000_w")
|
, m_bank_cb000_w(*this, "bank_cb000_w")
|
||||||
, m_bank_f8000_r(*this, "bank_f8000_r")
|
, m_bank_f8000_r(*this, "bank_f8000_r")
|
||||||
@ -140,24 +143,22 @@ class towns_state : public driver_device
|
|||||||
required_device_array<palette_device, 2> m_palette16;
|
required_device_array<palette_device, 2> m_palette16;
|
||||||
required_device<ram_device> m_ram;
|
required_device<ram_device> m_ram;
|
||||||
required_device<mb8877_device> m_fdc;
|
required_device<mb8877_device> m_fdc;
|
||||||
required_device<floppy_connector> m_flop0;
|
required_device_array<floppy_connector, 2> m_flop;
|
||||||
required_device<floppy_connector> m_flop1;
|
|
||||||
required_device<fmt_icmem_device> m_icmemcard;
|
required_device<fmt_icmem_device> m_icmemcard;
|
||||||
required_device<i8251_device> m_i8251;
|
required_device<i8251_device> m_i8251;
|
||||||
required_device<rs232_port_device> m_rs232;
|
required_device<rs232_port_device> m_rs232;
|
||||||
required_device<screen_device> m_screen;
|
required_device<screen_device> m_screen;
|
||||||
required_device<msm58321_device> m_rtc;
|
required_device<msm58321_device> m_rtc;
|
||||||
|
required_device<upd71071_device> m_dma_1;
|
||||||
|
required_device<cdrom_image_device> m_cdrom;
|
||||||
|
required_device<cdda_device> m_cdda;
|
||||||
|
required_device<fmscsi_device> m_scsi;
|
||||||
|
|
||||||
required_memory_bank m_bank_cb000_r;
|
required_memory_bank m_bank_cb000_r;
|
||||||
required_memory_bank m_bank_cb000_w;
|
required_memory_bank m_bank_cb000_w;
|
||||||
required_memory_bank m_bank_f8000_r;
|
required_memory_bank m_bank_f8000_r;
|
||||||
required_memory_bank m_bank_f8000_w;
|
required_memory_bank m_bank_f8000_w;
|
||||||
|
|
||||||
ram_device* m_messram;
|
|
||||||
cdrom_image_device* m_cdrom;
|
|
||||||
cdda_device* m_cdda;
|
|
||||||
class fmscsi_device* m_scsi;
|
|
||||||
|
|
||||||
uint16_t m_ftimer;
|
uint16_t m_ftimer;
|
||||||
uint16_t m_freerun_timer;
|
uint16_t m_freerun_timer;
|
||||||
emu_timer* m_towns_freerun_counter;
|
emu_timer* m_towns_freerun_counter;
|
||||||
|
@ -161,7 +161,7 @@ READ8_MEMBER( towns_state::towns_gfx_r )
|
|||||||
uint8_t ret = 0;
|
uint8_t ret = 0;
|
||||||
|
|
||||||
if(m_towns_mainmem_enable != 0)
|
if(m_towns_mainmem_enable != 0)
|
||||||
return m_messram->pointer()[offset+0xc0000];
|
return m_ram->pointer()[offset+0xc0000];
|
||||||
|
|
||||||
offset = offset << 2;
|
offset = offset << 2;
|
||||||
|
|
||||||
@ -184,7 +184,7 @@ WRITE8_MEMBER( towns_state::towns_gfx_w )
|
|||||||
{
|
{
|
||||||
if(m_towns_mainmem_enable != 0)
|
if(m_towns_mainmem_enable != 0)
|
||||||
{
|
{
|
||||||
m_messram->pointer()[offset+0xc0000] = data;
|
m_ram->pointer()[offset+0xc0000] = data;
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
offset = offset << 2;
|
offset = offset << 2;
|
||||||
@ -350,7 +350,7 @@ WRITE8_MEMBER( towns_state::towns_video_cff80_w )
|
|||||||
READ8_MEMBER( towns_state::towns_video_cff80_mem_r )
|
READ8_MEMBER( towns_state::towns_video_cff80_mem_r )
|
||||||
{
|
{
|
||||||
if(m_towns_mainmem_enable != 0)
|
if(m_towns_mainmem_enable != 0)
|
||||||
return m_messram->pointer()[offset+0xcff80];
|
return m_ram->pointer()[offset+0xcff80];
|
||||||
|
|
||||||
return towns_video_cff80_r(space,offset);
|
return towns_video_cff80_r(space,offset);
|
||||||
}
|
}
|
||||||
@ -359,7 +359,7 @@ WRITE8_MEMBER( towns_state::towns_video_cff80_mem_w )
|
|||||||
{
|
{
|
||||||
if(m_towns_mainmem_enable != 0)
|
if(m_towns_mainmem_enable != 0)
|
||||||
{
|
{
|
||||||
m_messram->pointer()[offset+0xcff80] = data;
|
m_ram->pointer()[offset+0xcff80] = data;
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
towns_video_cff80_w(space,offset,data);
|
towns_video_cff80_w(space,offset,data);
|
||||||
@ -662,7 +662,7 @@ READ8_MEMBER(towns_state::towns_video_unknown_r)
|
|||||||
*/
|
*/
|
||||||
READ8_MEMBER(towns_state::towns_spriteram_low_r)
|
READ8_MEMBER(towns_state::towns_spriteram_low_r)
|
||||||
{
|
{
|
||||||
uint8_t* RAM = m_messram->pointer();
|
uint8_t* RAM = m_ram->pointer();
|
||||||
uint8_t* ROM = m_user->base();
|
uint8_t* ROM = m_user->base();
|
||||||
|
|
||||||
if(offset < 0x1000)
|
if(offset < 0x1000)
|
||||||
@ -700,7 +700,7 @@ READ8_MEMBER(towns_state::towns_spriteram_low_r)
|
|||||||
|
|
||||||
WRITE8_MEMBER(towns_state::towns_spriteram_low_w)
|
WRITE8_MEMBER(towns_state::towns_spriteram_low_w)
|
||||||
{
|
{
|
||||||
uint8_t* RAM = m_messram->pointer();
|
uint8_t* RAM = m_ram->pointer();
|
||||||
|
|
||||||
if(offset < 0x1000)
|
if(offset < 0x1000)
|
||||||
{ // 0xc8000-0xc8fff
|
{ // 0xc8000-0xc8fff
|
||||||
|
Loading…
Reference in New Issue
Block a user