mirror of
https://github.com/holub/mame
synced 2025-04-23 08:49:55 +03:00
hd63450: Even more cleanup (nw)
This commit is contained in:
AJR
parent
80d1186218
commit
239476d98f
@ -24,7 +24,6 @@ hd63450_device::hd63450_device(const machine_config &mconfig, const char *tag, d
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memset(&m_reg[i], 0, sizeof(m_reg[i]));
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m_timer[i] = nullptr;
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m_in_progress[i] = 0;
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m_transfer_size[i] = 0;
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m_halted[i] = 0;
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m_drq_state[i] = 0;
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@ -72,7 +71,6 @@ void hd63450_device::device_start()
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save_item(NAME(m_reg[x].gcr), x);
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}
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save_item(NAME(m_in_progress));
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save_item(NAME(m_transfer_size));
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save_item(NAME(m_halted));
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save_item(NAME(m_drq_state));
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@ -94,7 +92,6 @@ void hd63450_device::device_reset()
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m_reg[x].gcr = 0;
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m_timer[x]->adjust(attotime::never);
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m_in_progress[x] = 0;
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m_halted[x] = 0;
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}
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}
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@ -157,7 +154,7 @@ WRITE16_MEMBER(hd63450_device::write)
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switch(reg)
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{
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case 0x00: // CSR / CER
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if(ACCESSING_BITS_8_15)
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if (ACCESSING_BITS_8_15)
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{
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// Writes to CSR clear all corresponding 1 bits except PCS and ACT
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m_reg[channel].csr &= ~((data & 0xf600) >> 8);
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@ -169,33 +166,33 @@ WRITE16_MEMBER(hd63450_device::write)
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}
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break;
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case 0x02: // DCR / OCR
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if(ACCESSING_BITS_8_15)
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if (ACCESSING_BITS_8_15)
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{
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m_reg[channel].dcr = (data & 0xff00) >> 8;
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logerror("DMA#%i: Device Control write : %02x\n",channel,m_reg[channel].dcr);
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}
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if(ACCESSING_BITS_0_7)
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if (ACCESSING_BITS_0_7)
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{
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m_reg[channel].ocr = data & 0x00ff;
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logerror("DMA#%i: Operation Control write : %02x\n",channel,m_reg[channel].ocr);
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}
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break;
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case 0x03: // SCR / CCR
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if(ACCESSING_BITS_8_15)
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if (ACCESSING_BITS_8_15)
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{
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m_reg[channel].scr = (data & 0xff00) >> 8;
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logerror("DMA#%i: Sequence Control write : %02x\n",channel,m_reg[channel].scr);
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}
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if(ACCESSING_BITS_0_7)
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if (ACCESSING_BITS_0_7)
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{
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m_reg[channel].ccr = data & 0x00ff;
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if((data & 0x0080))// && !m_dma_read[channel] && !m_dma_write[channel])
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if ((data & 0x0080))// && !m_dma_read[channel] && !m_dma_write[channel])
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dma_transfer_start(channel);
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if(data & 0x0010) // software abort
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if (data & 0x0010) // software abort
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dma_transfer_abort(channel);
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if(data & 0x0020) // halt operation
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if (data & 0x0020) // halt operation
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dma_transfer_halt(channel);
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if(data & 0x0040) // continure operation
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if (data & 0x0040) // continure operation
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dma_transfer_continue(channel);
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logerror("DMA#%i: Channel Control write : %02x\n",channel,m_reg[channel].ccr);
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}
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@ -266,30 +263,29 @@ WRITE16_MEMBER(hd63450_device::write)
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void hd63450_device::dma_transfer_start(int channel)
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{
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address_space &space = m_cpu->space(AS_PROGRAM);
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m_in_progress[channel] = 1;
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m_reg[channel].csr &= ~0xe0;
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m_reg[channel].csr |= 0x08; // Channel active
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m_reg[channel].csr &= ~0x30; // Reset Error and Normal termination bits
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if((m_reg[channel].ocr & 0x0c) != 0x00) // Array chain or Link array chain
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if ((m_reg[channel].ocr & 0x0c) != 0x00) // Array chain or Link array chain
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{
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m_reg[channel].mar = space.read_word(m_reg[channel].bar) << 16;
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m_reg[channel].mar |= space.read_word(m_reg[channel].bar+2);
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m_reg[channel].mtc = space.read_word(m_reg[channel].bar+4);
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if(m_reg[channel].btc > 0)
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if (m_reg[channel].btc > 0)
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m_reg[channel].btc--;
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}
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// Burst transfers will halt the CPU until the transfer is complete
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if((m_reg[channel].dcr & 0xc0) == 0x00) // Burst transfer
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if ((m_reg[channel].dcr & 0xc0) == 0x00) // Burst transfer
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{
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m_cpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
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m_timer[channel]->adjust(attotime::zero, channel, m_burst_clock[channel]);
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}
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else if(!(m_reg[channel].ocr & 2))
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else if (!(m_reg[channel].ocr & 2))
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m_timer[channel]->adjust(attotime::from_usec(500), channel, m_our_clock[channel]);
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else if((m_reg[channel].ocr & 3) == 3)
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else if ((m_reg[channel].ocr & 3) == 3)
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m_timer[channel]->adjust(attotime::from_usec(500), channel, attotime::never);
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else if((m_reg[channel].ocr & 3) == 2)
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else if ((m_reg[channel].ocr & 3) == 2)
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m_timer[channel]->adjust(attotime::never, channel, attotime::never);
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m_transfer_size[channel] = m_reg[channel].mtc;
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@ -300,25 +296,24 @@ void hd63450_device::dma_transfer_start(int channel)
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void hd63450_device::set_timer(int channel, const attotime &tm)
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{
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m_our_clock[channel] = tm;
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if(m_in_progress[channel] != 0)
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if (dma_in_progress(channel))
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m_timer[channel]->adjust(attotime::zero, channel, m_our_clock[channel]);
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}
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TIMER_CALLBACK_MEMBER(hd63450_device::dma_transfer_timer)
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{
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if(((m_reg[param].ocr & 3) == 2) && !m_drq_state[param])
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if (((m_reg[param].ocr & 3) == 2) && !m_drq_state[param])
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return;
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single_transfer(param);
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}
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void hd63450_device::dma_transfer_abort(int channel)
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{
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if(!m_in_progress[channel])
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if (!dma_in_progress(channel))
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return;
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logerror("DMA#%i: Transfer aborted\n",channel);
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m_timer[channel]->adjust(attotime::never);
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m_in_progress[channel] = 0;
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m_reg[channel].csr |= 0x90; // channel error
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m_reg[channel].csr &= ~0x08; // channel no longer active
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m_reg[channel].cer = 0x11;
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@ -334,7 +329,7 @@ void hd63450_device::dma_transfer_halt(int channel)
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void hd63450_device::dma_transfer_continue(int channel)
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{
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if(m_halted[channel] != 0)
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if (m_halted[channel] != 0)
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{
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m_halted[channel] = 0;
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m_timer[channel]->adjust(attotime::zero, channel, m_our_clock[channel]);
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@ -347,174 +342,131 @@ void hd63450_device::single_transfer(int x)
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int data;
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int datasize = 1;
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if(m_in_progress[x] != 0) // DMA in progress in channel x
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if (!dma_in_progress(x)) // DMA in progress in channel x
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return;
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if (m_reg[x].ocr & 0x80) // direction: 1 = device -> memory
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{
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if (!m_dma_read[x].isnull())
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{
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if(m_reg[x].ocr & 0x80) // direction: 1 = device -> memory
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data = m_dma_read[x](m_reg[x].mar);
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if (data == -1)
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return; // not ready to receive data
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space.write_byte(m_reg[x].mar,data);
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datasize = 1;
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}
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else
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{
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switch(m_reg[x].ocr & 0x30) // operation size
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{
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if((x == 0) && !m_dma_read[0].isnull())
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{
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data = m_dma_read[0](m_reg[x].mar);
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if(data == -1)
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return; // not ready to receive data
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space.write_byte(m_reg[x].mar,data);
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datasize = 1;
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}
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else if((x == 1) && !m_dma_read[1].isnull())
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{
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data = m_dma_read[1](m_reg[x].mar);
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if(data == -1)
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return; // not ready to receive data
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space.write_byte(m_reg[x].mar,data);
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datasize = 1;
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}
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else if((x == 2) && !m_dma_read[2].isnull())
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{
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data = m_dma_read[2](m_reg[x].mar);
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if(data == -1)
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return; // not ready to receive data
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space.write_byte(m_reg[x].mar,data);
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datasize = 1;
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}
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else if((x == 3) && !m_dma_read[3].isnull())
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{
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data = m_dma_read[3](m_reg[x].mar);
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if(data == -1)
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return; // not ready to receive data
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space.write_byte(m_reg[x].mar,data);
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datasize = 1;
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}
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else
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{
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switch(m_reg[x].ocr & 0x30) // operation size
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{
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case 0x00: // 8 bit
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data = space.read_byte(m_reg[x].dar); // read from device address
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space.write_byte(m_reg[x].mar, data); // write to memory address
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datasize = 1;
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break;
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case 0x10: // 16 bit
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data = space.read_word(m_reg[x].dar); // read from device address
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space.write_word(m_reg[x].mar, data); // write to memory address
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datasize = 2;
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break;
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case 0x20: // 32 bit
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data = space.read_word(m_reg[x].dar) << 16; // read from device address
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data |= space.read_word(m_reg[x].dar+2);
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space.write_word(m_reg[x].mar, (data & 0xffff0000) >> 16); // write to memory address
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space.write_word(m_reg[x].mar+2, data & 0x0000ffff);
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datasize = 4;
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break;
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case 0x30: // 8 bit packed (?)
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data = space.read_byte(m_reg[x].dar); // read from device address
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space.write_byte(m_reg[x].mar, data); // write to memory address
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datasize = 1;
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break;
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}
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}
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// logerror("DMA#%i: byte transfer %08lx -> %08lx (byte = %02x)\n",x,dmac.reg[x].dar,dmac.reg[x].mar,data);
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}
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else // memory -> device
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{
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if((x == 0) && !m_dma_write[0].isnull())
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{
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data = space.read_byte(m_reg[x].mar);
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m_dma_write[0]((offs_t)m_reg[x].mar,data);
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datasize = 1;
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}
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else if((x == 1) && !m_dma_write[1].isnull())
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{
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data = space.read_byte(m_reg[x].mar);
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m_dma_write[1]((offs_t)m_reg[x].mar,data);
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datasize = 1;
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}
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else if((x == 2) && !m_dma_write[2].isnull())
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{
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data = space.read_byte(m_reg[x].mar);
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m_dma_write[2]((offs_t)m_reg[x].mar,data);
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datasize = 1;
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}
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else if((x == 3) && !m_dma_write[3].isnull())
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{
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data = space.read_byte(m_reg[x].mar);
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m_dma_write[3]((offs_t)m_reg[x].mar,data);
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datasize = 1;
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}
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else
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{
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switch(m_reg[x].ocr & 0x30) // operation size
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{
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case 0x00: // 8 bit
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data = space.read_byte(m_reg[x].mar); // read from memory address
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space.write_byte(m_reg[x].dar, data); // write to device address
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datasize = 1;
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break;
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case 0x10: // 16 bit
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data = space.read_word(m_reg[x].mar); // read from memory address
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space.write_word(m_reg[x].dar, data); // write to device address
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datasize = 2;
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break;
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case 0x20: // 32 bit
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data = space.read_word(m_reg[x].mar) << 16; // read from memory address
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data |= space.read_word(m_reg[x].mar+2); // read from memory address
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space.write_word(m_reg[x].dar, (data & 0xffff0000) >> 16); // write to device address
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space.write_word(m_reg[x].dar+2, data & 0x0000ffff); // write to device address
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datasize = 4;
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break;
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case 0x30: // 8 bit packed (?)
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data = space.read_byte(m_reg[x].mar); // read from memory address
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space.write_byte(m_reg[x].dar, data); // write to device address
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datasize = 1;
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break;
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}
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}
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// logerror("DMA#%i: byte transfer %08lx -> %08lx\n",x,m_reg[x].mar,m_reg[x].dar);
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}
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// decrease memory transfer counter
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if(m_reg[x].mtc > 0)
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m_reg[x].mtc--;
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// handle change of memory and device addresses
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if((m_reg[x].scr & 0x03) == 0x01)
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m_reg[x].dar+=datasize;
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else if((m_reg[x].scr & 0x03) == 0x02)
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m_reg[x].dar-=datasize;
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if((m_reg[x].scr & 0x0c) == 0x04)
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m_reg[x].mar+=datasize;
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else if((m_reg[x].scr & 0x0c) == 0x08)
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m_reg[x].mar-=datasize;
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if(m_reg[x].mtc <= 0)
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{
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// End of transfer
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logerror("DMA#%i: End of transfer\n",x);
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if((m_reg[x].ocr & 0x0c) != 0 && m_reg[x].btc > 0)
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{
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m_reg[x].btc--;
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m_reg[x].bar+=6;
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m_reg[x].mar = space.read_word(m_reg[x].bar) << 16;
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m_reg[x].mar |= space.read_word(m_reg[x].bar+2);
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m_reg[x].mtc = space.read_word(m_reg[x].bar+4);
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return;
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}
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m_timer[x]->adjust(attotime::never);
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m_in_progress[x] = 0;
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m_reg[x].csr |= 0xe0; // channel operation complete, block transfer complete
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m_reg[x].csr &= ~0x08; // channel no longer active
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m_reg[x].ccr &= ~0xc0;
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// Burst transfer
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if((m_reg[x].dcr & 0xc0) == 0x00)
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{
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m_cpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
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}
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if(!m_dma_end.isnull())
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m_dma_end((offs_t)x, m_reg[x].ccr & 0x08);
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case 0x00: // 8 bit
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data = space.read_byte(m_reg[x].dar); // read from device address
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space.write_byte(m_reg[x].mar, data); // write to memory address
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datasize = 1;
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break;
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case 0x10: // 16 bit
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data = space.read_word(m_reg[x].dar); // read from device address
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space.write_word(m_reg[x].mar, data); // write to memory address
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datasize = 2;
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break;
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case 0x20: // 32 bit
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data = space.read_word(m_reg[x].dar) << 16; // read from device address
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data |= space.read_word(m_reg[x].dar+2);
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space.write_word(m_reg[x].mar, (data & 0xffff0000) >> 16); // write to memory address
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space.write_word(m_reg[x].mar+2, data & 0x0000ffff);
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datasize = 4;
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break;
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case 0x30: // 8 bit packed (?)
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data = space.read_byte(m_reg[x].dar); // read from device address
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space.write_byte(m_reg[x].mar, data); // write to memory address
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datasize = 1;
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break;
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}
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}
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// logerror("DMA#%i: byte transfer %08lx -> %08lx (byte = %02x)\n",x,dmac.reg[x].dar,dmac.reg[x].mar,data);
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}
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else // memory -> device
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{
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if (!m_dma_write[x].isnull())
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{
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data = space.read_byte(m_reg[x].mar);
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m_dma_write[x]((offs_t)m_reg[x].mar,data);
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datasize = 1;
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}
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else
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{
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switch(m_reg[x].ocr & 0x30) // operation size
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{
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case 0x00: // 8 bit
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data = space.read_byte(m_reg[x].mar); // read from memory address
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space.write_byte(m_reg[x].dar, data); // write to device address
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datasize = 1;
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break;
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case 0x10: // 16 bit
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data = space.read_word(m_reg[x].mar); // read from memory address
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space.write_word(m_reg[x].dar, data); // write to device address
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datasize = 2;
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break;
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case 0x20: // 32 bit
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data = space.read_word(m_reg[x].mar) << 16; // read from memory address
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data |= space.read_word(m_reg[x].mar+2); // read from memory address
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space.write_word(m_reg[x].dar, (data & 0xffff0000) >> 16); // write to device address
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space.write_word(m_reg[x].dar+2, data & 0x0000ffff); // write to device address
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datasize = 4;
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break;
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case 0x30: // 8 bit packed (?)
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data = space.read_byte(m_reg[x].mar); // read from memory address
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space.write_byte(m_reg[x].dar, data); // write to device address
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datasize = 1;
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break;
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}
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}
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// logerror("DMA#%i: byte transfer %08lx -> %08lx\n",x,m_reg[x].mar,m_reg[x].dar);
|
||||
}
|
||||
|
||||
|
||||
// decrease memory transfer counter
|
||||
if (m_reg[x].mtc > 0)
|
||||
m_reg[x].mtc--;
|
||||
|
||||
// handle change of memory and device addresses
|
||||
if ((m_reg[x].scr & 0x03) == 0x01)
|
||||
m_reg[x].dar+=datasize;
|
||||
else if ((m_reg[x].scr & 0x03) == 0x02)
|
||||
m_reg[x].dar-=datasize;
|
||||
|
||||
if ((m_reg[x].scr & 0x0c) == 0x04)
|
||||
m_reg[x].mar+=datasize;
|
||||
else if ((m_reg[x].scr & 0x0c) == 0x08)
|
||||
m_reg[x].mar-=datasize;
|
||||
|
||||
if (m_reg[x].mtc <= 0)
|
||||
{
|
||||
// End of transfer
|
||||
logerror("DMA#%i: End of transfer\n",x);
|
||||
if ((m_reg[x].ocr & 0x0c) != 0 && m_reg[x].btc > 0)
|
||||
{
|
||||
m_reg[x].btc--;
|
||||
m_reg[x].bar+=6;
|
||||
m_reg[x].mar = space.read_word(m_reg[x].bar) << 16;
|
||||
m_reg[x].mar |= space.read_word(m_reg[x].bar+2);
|
||||
m_reg[x].mtc = space.read_word(m_reg[x].bar+4);
|
||||
return;
|
||||
}
|
||||
m_timer[x]->adjust(attotime::never);
|
||||
m_reg[x].csr |= 0xe0; // channel operation complete, block transfer complete
|
||||
m_reg[x].csr &= ~0x08; // channel no longer active
|
||||
m_reg[x].ccr &= ~0xc0;
|
||||
|
||||
// Burst transfer
|
||||
if ((m_reg[x].dcr & 0xc0) == 0x00)
|
||||
{
|
||||
m_cpu->set_input_line(INPUT_LINE_HALT, CLEAR_LINE);
|
||||
}
|
||||
|
||||
if (!m_dma_end.isnull())
|
||||
m_dma_end((offs_t)x, m_reg[x].ccr & 0x08);
|
||||
}
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(hd63450_device::drq0_w)
|
||||
@ -522,13 +474,13 @@ WRITE_LINE_MEMBER(hd63450_device::drq0_w)
|
||||
bool ostate = m_drq_state[0];
|
||||
m_drq_state[0] = state;
|
||||
|
||||
if((m_reg[0].ocr & 2) && (state && !ostate))
|
||||
if ((m_reg[0].ocr & 2) && (state && !ostate))
|
||||
{
|
||||
// in cycle steal mode drq is supposed to be edge triggered
|
||||
single_transfer(0);
|
||||
m_timer[0]->adjust(m_our_clock[0], 0, m_our_clock[0]);
|
||||
}
|
||||
else if(!state)
|
||||
else if (!state)
|
||||
m_timer[0]->adjust(attotime::never);
|
||||
}
|
||||
|
||||
@ -537,12 +489,12 @@ WRITE_LINE_MEMBER(hd63450_device::drq1_w)
|
||||
bool ostate = m_drq_state[1];
|
||||
m_drq_state[1] = state;
|
||||
|
||||
if((m_reg[1].ocr & 2) && (state && !ostate))
|
||||
if ((m_reg[1].ocr & 2) && (state && !ostate))
|
||||
{
|
||||
single_transfer(1);
|
||||
m_timer[1]->adjust(m_our_clock[1], 1, m_our_clock[1]);
|
||||
}
|
||||
else if(!state)
|
||||
else if (!state)
|
||||
m_timer[1]->adjust(attotime::never);
|
||||
}
|
||||
|
||||
@ -551,12 +503,12 @@ WRITE_LINE_MEMBER(hd63450_device::drq2_w)
|
||||
bool ostate = m_drq_state[2];
|
||||
m_drq_state[2] = state;
|
||||
|
||||
if((m_reg[2].ocr & 2) && (state && !ostate))
|
||||
if ((m_reg[2].ocr & 2) && (state && !ostate))
|
||||
{
|
||||
single_transfer(2);
|
||||
m_timer[2]->adjust(m_our_clock[2], 2, m_our_clock[2]);
|
||||
}
|
||||
else if(!state)
|
||||
else if (!state)
|
||||
m_timer[2]->adjust(attotime::never);
|
||||
}
|
||||
|
||||
@ -565,12 +517,12 @@ WRITE_LINE_MEMBER(hd63450_device::drq3_w)
|
||||
bool ostate = m_drq_state[3];
|
||||
m_drq_state[3] = state;
|
||||
|
||||
if((m_reg[3].ocr & 2) && (state && !ostate))
|
||||
if ((m_reg[3].ocr & 2) && (state && !ostate))
|
||||
{
|
||||
single_transfer(3);
|
||||
m_timer[3]->adjust(m_our_clock[3], 3, m_our_clock[3]);
|
||||
}
|
||||
else if(!state)
|
||||
else if (!state)
|
||||
m_timer[3]->adjust(attotime::never);
|
||||
}
|
||||
|
||||
|
||||
@ -126,12 +126,14 @@ private:
|
||||
// internal state
|
||||
hd63450_regs m_reg[4];
|
||||
emu_timer* m_timer[4]; // for timing data reading/writing each channel
|
||||
int m_in_progress[4]; // if a channel is in use
|
||||
int m_transfer_size[4];
|
||||
int m_halted[4]; // non-zero if a channel has been halted, and can be continued later.
|
||||
required_device<cpu_device> m_cpu;
|
||||
bool m_drq_state[4];
|
||||
|
||||
// tell if a channel is in use
|
||||
bool dma_in_progress(int channel) const { return (m_reg[channel].csr & 0x08) != 0; }
|
||||
|
||||
TIMER_CALLBACK_MEMBER(dma_transfer_timer);
|
||||
void dma_transfer_abort(int channel);
|
||||
void dma_transfer_halt(int channel);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user