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hd63450: Even more cleanup (nw)

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This commit is contained in:
AJR 2018-06-25 16:11:54 -04:00
parent 80d1186218
commit 239476d98f
2 changed files with 151 additions and 197 deletions
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66
src/devices/machine/hd63450.cpp
View File

@ -24,7 +24,6 @@ hd63450_device::hd63450_device(const machine_config &mconfig, const char *tag, d
memset(&m_reg[i], 0, sizeof(m_reg[i]));
m_timer[i] = nullptr;
m_in_progress[i] = 0;
m_transfer_size[i] = 0;
m_halted[i] = 0;
m_drq_state[i] = 0;
@ -72,7 +71,6 @@ void hd63450_device::device_start()
save_item(NAME(m_reg[x].gcr), x);
}
save_item(NAME(m_in_progress));
save_item(NAME(m_transfer_size));
save_item(NAME(m_halted));
save_item(NAME(m_drq_state));
@ -94,7 +92,6 @@ void hd63450_device::device_reset()
m_reg[x].gcr = 0;
m_timer[x]->adjust(attotime::never);
m_in_progress[x] = 0;
m_halted[x] = 0;
}
}
@ -266,7 +263,6 @@ WRITE16_MEMBER(hd63450_device::write)
void hd63450_device::dma_transfer_start(int channel)
{
address_space &space = m_cpu->space(AS_PROGRAM);
m_in_progress[channel] = 1;
m_reg[channel].csr &= ~0xe0;
m_reg[channel].csr |= 0x08; // Channel active
m_reg[channel].csr &= ~0x30; // Reset Error and Normal termination bits
@ -300,7 +296,7 @@ void hd63450_device::dma_transfer_start(int channel)
void hd63450_device::set_timer(int channel, const attotime &tm)
{
m_our_clock[channel] = tm;
if(m_in_progress[channel] != 0)
if (dma_in_progress(channel))
m_timer[channel]->adjust(attotime::zero, channel, m_our_clock[channel]);
}
@ -313,12 +309,11 @@ TIMER_CALLBACK_MEMBER(hd63450_device::dma_transfer_timer)
void hd63450_device::dma_transfer_abort(int channel)
{
if(!m_in_progress[channel])
if (!dma_in_progress(channel))
return;
logerror("DMA#%i: Transfer aborted\n",channel);
m_timer[channel]->adjust(attotime::never);
m_in_progress[channel] = 0;
m_reg[channel].csr |= 0x90; // channel error
m_reg[channel].csr &= ~0x08; // channel no longer active
m_reg[channel].cer = 0x11;
@ -347,37 +342,14 @@ void hd63450_device::single_transfer(int x)
int data;
int datasize = 1;
if(m_in_progress[x] != 0) // DMA in progress in channel x
{
if (!dma_in_progress(x)) // DMA in progress in channel x
return;
if (m_reg[x].ocr & 0x80) // direction: 1 = device -> memory
{
if((x == 0) && !m_dma_read[0].isnull())
if (!m_dma_read[x].isnull())
{
data = m_dma_read[0](m_reg[x].mar);
if(data == -1)
return; // not ready to receive data
space.write_byte(m_reg[x].mar,data);
datasize = 1;
}
else if((x == 1) && !m_dma_read[1].isnull())
{
data = m_dma_read[1](m_reg[x].mar);
if(data == -1)
return; // not ready to receive data
space.write_byte(m_reg[x].mar,data);
datasize = 1;
}
else if((x == 2) && !m_dma_read[2].isnull())
{
data = m_dma_read[2](m_reg[x].mar);
if(data == -1)
return; // not ready to receive data
space.write_byte(m_reg[x].mar,data);
datasize = 1;
}
else if((x == 3) && !m_dma_read[3].isnull())
{
data = m_dma_read[3](m_reg[x].mar);
data = m_dma_read[x](m_reg[x].mar);
if (data == -1)
return; // not ready to receive data
space.write_byte(m_reg[x].mar,data);
@ -415,28 +387,10 @@ void hd63450_device::single_transfer(int x)
}
else // memory -> device
{
if((x == 0) && !m_dma_write[0].isnull())
if (!m_dma_write[x].isnull())
{
data = space.read_byte(m_reg[x].mar);
m_dma_write[0]((offs_t)m_reg[x].mar,data);
datasize = 1;
}
else if((x == 1) && !m_dma_write[1].isnull())
{
data = space.read_byte(m_reg[x].mar);
m_dma_write[1]((offs_t)m_reg[x].mar,data);
datasize = 1;
}
else if((x == 2) && !m_dma_write[2].isnull())
{
data = space.read_byte(m_reg[x].mar);
m_dma_write[2]((offs_t)m_reg[x].mar,data);
datasize = 1;
}
else if((x == 3) && !m_dma_write[3].isnull())
{
data = space.read_byte(m_reg[x].mar);
m_dma_write[3]((offs_t)m_reg[x].mar,data);
m_dma_write[x]((offs_t)m_reg[x].mar,data);
datasize = 1;
}
else
@ -500,7 +454,6 @@ void hd63450_device::single_transfer(int x)
return;
}
m_timer[x]->adjust(attotime::never);
m_in_progress[x] = 0;
m_reg[x].csr |= 0xe0; // channel operation complete, block transfer complete
m_reg[x].csr &= ~0x08; // channel no longer active
m_reg[x].ccr &= ~0xc0;
@ -515,7 +468,6 @@ void hd63450_device::single_transfer(int x)
m_dma_end((offs_t)x, m_reg[x].ccr & 0x08);
}
}
}
WRITE_LINE_MEMBER(hd63450_device::drq0_w)
{

4
src/devices/machine/hd63450.h
View File

@ -126,12 +126,14 @@ private:
// internal state
hd63450_regs m_reg[4];
emu_timer* m_timer[4]; // for timing data reading/writing each channel
int m_in_progress[4]; // if a channel is in use
int m_transfer_size[4];
int m_halted[4]; // non-zero if a channel has been halted, and can be continued later.
required_device<cpu_device> m_cpu;
bool m_drq_state[4];
// tell if a channel is in use
bool dma_in_progress(int channel) const { return (m_reg[channel].csr & 0x08) != 0; }
TIMER_CALLBACK_MEMBER(dma_transfer_timer);
void dma_transfer_abort(int channel);
void dma_transfer_halt(int channel);