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mips1: undocumented behaviour (nw)

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This commit is contained in:
Patrick Mackinlay 2019-08-29 19:45:01 +07:00
parent cbb3262e2a
commit 23a5e12303
1 changed files with 12 additions and 1 deletions
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13
src/devices/cpu/mips/mips1.cpp
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@ -383,7 +383,18 @@ void mips1core_device_base::execute_run()
} }
break; break;
case 0x01: // REGIMM case 0x01: // REGIMM
switch (RTREG) /*
* Hardware testing has established that MIPS-1 processors do
* not decode bit 17 of REGIMM format instructions. This bit is
* used to add the "branch likely" instructions for MIPS-2 and
* later architectures.
*
* IRIX 5.3 inst(1M) uses this behaviour to distinguish MIPS-1
* from MIPS-2 processors; the latter nullify the delay slot
* instruction if the branch is not taken, whereas the former
* execute the delay slot instruction regardless.
*/
switch (RTREG & 0x1d)
{ {
case 0x00: // BLTZ case 0x00: // BLTZ
if (s32(m_r[RSREG]) < 0) if (s32(m_r[RSREG]) < 0)