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trident: hopefully found the clock divider bit used by the BIOS, refresh rates should now be pretty correct.

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This commit is contained in:
mahlemiut 2014-10-04 07:58:42 +00:00
parent d23aa31fb8
commit 23a8adb411
2 changed files with 16 additions and 2 deletions
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17
src/emu/bus/isa/trident.c
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@ -173,6 +173,7 @@ void trident_vga_device::device_start()
save_pointer(vga.sequencer.data,"Sequencer Registers",0x100); save_pointer(vga.sequencer.data,"Sequencer Registers",0x100);
save_pointer(vga.attribute.data,"Attribute Registers", 0x15); save_pointer(vga.attribute.data,"Attribute Registers", 0x15);
save_pointer(tri.accel_pattern,"Pattern Data", 0x80); save_pointer(tri.accel_pattern,"Pattern Data", 0x80);
save_pointer(tri.lutdac_reg,"LUTDAC registers", 0x100);
m_vblank_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(vga_device::vblank_timer_cb),this)); m_vblank_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(vga_device::vblank_timer_cb),this));
vga.svga_intf.seq_regcount = 0x0f; vga.svga_intf.seq_regcount = 0x0f;
@ -371,9 +372,14 @@ void trident_vga_device::trident_define_video_mode()
case 0: case 0:
default: xtal = XTAL_25_1748MHz; break; default: xtal = XTAL_25_1748MHz; break;
case 1: xtal = XTAL_28_63636MHz; break; case 1: xtal = XTAL_28_63636MHz; break;
case 2: xtal = calculate_clock(); break; // how to divide the clock? Needed for higher refresh rates (75Hz+) case 2: xtal = calculate_clock(); break;
} }
if(tri.gc0f & 0x08) // 16 pixels per character clock
xtal = xtal / 2;
if(tri.port_3db & 0x20)
xtal = xtal / 2; // correct?
svga.rgb8_en = svga.rgb15_en = svga.rgb16_en = svga.rgb32_en = 0; svga.rgb8_en = svga.rgb15_en = svga.rgb16_en = svga.rgb32_en = 0;
switch((tri.pixel_depth & 0x0c) >> 2) switch((tri.pixel_depth & 0x0c) >> 2)
@ -438,9 +444,9 @@ UINT8 trident_vga_device::trident_seq_reg_read(UINT8 index)
void trident_vga_device::trident_seq_reg_write(UINT8 index, UINT8 data) void trident_vga_device::trident_seq_reg_write(UINT8 index, UINT8 data)
{ {
vga.sequencer.data[vga.sequencer.index] = data;
if(index <= 0x04) if(index <= 0x04)
{ {
vga.sequencer.data[vga.sequencer.index] = data;
seq_reg_write(vga.sequencer.index,data); seq_reg_write(vga.sequencer.index,data);
recompute_params(); recompute_params();
} }
@ -745,6 +751,7 @@ void trident_vga_device::trident_gc_reg_write(UINT8 index, UINT8 data)
break; break;
case 0x0f: case 0x0f:
tri.gc0f = data; tri.gc0f = data;
trident_define_video_mode();
break; break;
case 0x2f: // XFree86 refers to this register as "MiscIntContReg", setting bit 2, but gives no indication as to what it does case 0x2f: // XFree86 refers to this register as "MiscIntContReg", setting bit 2, but gives no indication as to what it does
tri.gc2f = data; tri.gc2f = data;
@ -855,6 +862,9 @@ READ8_MEMBER(trident_vga_device::port_03d0_r)
else else
res = 0xff; res = 0xff;
break; break;
case 11:
res = tri.port_3db;
break;
default: default:
res = vga_device::port_03d0_r(space,offset,mem_mask); res = vga_device::port_03d0_r(space,offset,mem_mask);
break; break;
@ -896,6 +906,9 @@ WRITE8_MEMBER(trident_vga_device::port_03d0_w)
} }
} }
break; break;
case 11:
tri.port_3db = data; // no info on this port? Bit 5 appears to be a clock divider...
break;
default: default:
vga_device::port_03d0_w(space,offset,data,mem_mask); vga_device::port_03d0_w(space,offset,data,mem_mask);
break; break;

1
src/emu/bus/isa/trident.h
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@ -60,6 +60,7 @@ protected:
UINT8 lutdac_index; UINT8 lutdac_index;
bool new_mode; bool new_mode;
bool port_3c3; bool port_3c3;
UINT8 port_3db;
UINT8 clock; UINT8 clock;
UINT8 pixel_depth; UINT8 pixel_depth;
UINT8 revision; UINT8 revision;