Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-20 23:42:22 +03:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

(MESS) Modernized MC68328 (DragonBall) device. [Fabio Priuli]

Browse Source
This commit is contained in:
Fabio Priuli 2013-06-03 18:26:37 +00:00
parent 6dd8e21fee
commit 23b782ac5c
7 changed files with 1859 additions and 1922 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.gitattributes vendored
View File

@ -6599,7 +6599,6 @@ src/mess/includes/mbc55x.h svneol=native#text/plain
src/mess/includes/mbee.h svneol=native#text/plain
src/mess/includes/mboard.h svneol=native#text/plain
src/mess/includes/mc1000.h svneol=native#text/plain
src/mess/includes/mc68328.h svneol=native#text/plain
src/mess/includes/mc80.h svneol=native#text/plain
src/mess/includes/micronic.h svneol=native#text/plain
src/mess/includes/microtan.h svneol=native#text/plain
@ -8123,7 +8122,6 @@ src/mess/video/lviv.c svneol=native#text/plain
src/mess/video/mac.c svneol=native#text/plain
src/mess/video/mbc55x.c svneol=native#text/plain
src/mess/video/mbee.c svneol=native#text/plain
src/mess/video/mc68328.c svneol=native#text/plain
src/mess/video/mc80.c svneol=native#text/plain
src/mess/video/microtan.c svneol=native#text/plain
src/mess/video/mikro80.c svneol=native#text/plain

48
src/mess/drivers/palm.c
View File

@ -11,12 +11,14 @@
#include "emu.h"
#include "cpu/m68000/m68000.h"
#include "includes/mc68328.h"
#include "machine/mc68328.h"
#include "machine/ram.h"
#include "sound/dac.h"
#include "debugger.h"
#include "machine/ram.h"
#include "rendlay.h"
#define MC68328_TAG "dragonball"
class palm_state : public driver_device
{
public:
@ -35,7 +37,6 @@ public:
required_device<mc68328_device> m_lsi;
required_device<dac_device> m_dac;
required_device<ram_device> m_ram;
// mc68328 needs modernising
//DECLARE_WRITE8_MEMBER(palm_dac_transition);
//DECLARE_WRITE8_MEMBER(palm_port_f_out);
//DECLARE_READ8_MEMBER(palm_port_c_in);
@ -54,6 +55,7 @@ public:
DECLARE_WRITE16_MEMBER(palm_spim_out);
DECLARE_READ16_MEMBER(palm_spim_in);
DECLARE_WRITE8_MEMBER(palm_dac_transition);
DECLARE_WRITE_LINE_MEMBER(palm_spim_exchange);
required_ioport m_io_penx;
required_ioport m_io_peny;
@ -73,16 +75,15 @@ INPUT_CHANGED_MEMBER(palm_state::pen_check)
UINT8 button = m_io_penb->read();
if(button)
mc68328_set_penirq_line(m_lsi, 1);
m_lsi->set_penirq_line(1);
else
mc68328_set_penirq_line(m_lsi, 0);
m_lsi->set_penirq_line(0);
}
INPUT_CHANGED_MEMBER(palm_state::button_check)
{
UINT8 button_state = m_io_portd->read();
mc68328_set_port_d_lines(m_lsi, button_state, (int)(FPTR)param);
m_lsi->set_port_d_lines(button_state, (int)(FPTR)param);
}
WRITE8_MEMBER(palm_state::palm_port_f_out)
@ -110,20 +111,19 @@ READ16_MEMBER(palm_state::palm_spim_in)
return m_spim_data;
}
static void palm_spim_exchange( device_t *device )
WRITE_LINE_MEMBER(palm_state::palm_spim_exchange)
{
palm_state *state = device->machine().driver_data<palm_state>();
UINT8 x = state->m_io_penx->read();
UINT8 y = state->m_io_peny->read();
UINT8 x = m_io_penx->read();
UINT8 y = m_io_peny->read();
switch( state->m_port_f_latch & 0x0f )
switch (m_port_f_latch & 0x0f)
{
case 0x06:
state->m_spim_data = (0xff - x) * 2;
m_spim_data = (0xff - x) * 2;
break;
case 0x09:
state->m_spim_data = (0xff - y) * 2;
m_spim_data = (0xff - y) * 2;
break;
}
}
@ -159,7 +159,7 @@ void palm_state::machine_reset()
static ADDRESS_MAP_START(palm_map, AS_PROGRAM, 16, palm_state)
AM_RANGE(0xc00000, 0xe07fff) AM_ROM AM_REGION("bios", 0)
AM_RANGE(0xfff000, 0xffffff) AM_DEVREADWRITE_LEGACY(MC68328_TAG, mc68328_r, mc68328_w)
AM_RANGE(0xfff000, 0xffffff) AM_DEVREADWRITE(MC68328_TAG, mc68328_device, read, write)
ADDRESS_MAP_END
@ -176,6 +176,14 @@ WRITE8_MEMBER(palm_state::palm_dac_transition)
/***************************************************************************
MACHINE DRIVERS
***************************************************************************/
/* THIS IS PRETTY MUCH TOTALLY WRONG AND DOESN'T REFLECT THE MC68328'S INTERNAL FUNCTIONALITY AT ALL! */
PALETTE_INIT( palm )
{
palette_set_color_rgb(machine, 0, 0x7b, 0x8c, 0x5a);
palette_set_color_rgb(machine, 1, 0x00, 0x00, 0x00);
}
static MC68328_INTERFACE(palm_dragonball_iface)
{
"maincpu",
@ -206,7 +214,7 @@ static MC68328_INTERFACE(palm_dragonball_iface)
DEVCB_DRIVER_MEMBER16(palm_state,palm_spim_out),
DEVCB_DRIVER_MEMBER16(palm_state,palm_spim_in),
palm_spim_exchange
DEVCB_DRIVER_LINE_MEMBER(palm_state, palm_spim_exchange)
};
@ -219,15 +227,13 @@ static MACHINE_CONFIG_START( palm, palm_state )
MCFG_SCREEN_VBLANK_TIME( ATTOSECONDS_IN_USEC(1260) )
MCFG_QUANTUM_TIME( attotime::from_hz(60) )
/* video hardware */
MCFG_VIDEO_ATTRIBUTES( VIDEO_UPDATE_BEFORE_VBLANK )
MCFG_SCREEN_SIZE( 160, 220 )
MCFG_SCREEN_VISIBLE_AREA( 0, 159, 0, 219 )
MCFG_VIDEO_START( mc68328 )
MCFG_SCREEN_UPDATE_STATIC( mc68328 )
MCFG_SCREEN_UPDATE_DEVICE(MC68328_TAG, mc68328_device, screen_update)
MCFG_PALETTE_LENGTH( 2 )
MCFG_PALETTE_INIT( mc68328 )
MCFG_PALETTE_INIT( palm )
MCFG_DEFAULT_LAYOUT(layout_lcd)
/* audio hardware */
@ -235,7 +241,7 @@ static MACHINE_CONFIG_START( palm, palm_state )
MCFG_SOUND_ADD("dac", DAC, 0)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
MCFG_MC68328_ADD( palm_dragonball_iface ) // lsi device
MCFG_MC68328_ADD( MC68328_TAG, palm_dragonball_iface ) // lsi device
MACHINE_CONFIG_END
static INPUT_PORTS_START( palm )

193
src/mess/includes/mc68328.h
View File

@ -1,193 +0,0 @@
/**********************************************************************
Motorola 68328 ("DragonBall") System-on-a-Chip implementation
By MooglyGuy
contact mooglyguy@gmail.com with licensing and usage questions.
**********************************************************************/
/*****************************************************************************************************************
P P P P P P P P P P P P P P
E E E E E E E J J J J J J J
1 2 3 4 5 6 7 0 1 2 3 4 5 6
D D D D D / / / / / / / / / / / / / /
3 4 5 6 7 ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
/ / / / / ! ! C C C C C C C C C C C C C C C
P V P P P P D D G D D D D T T L U V S S S S S S S S G S S S S S S S
B C B B B B D D 1 1 N 1 1 1 1 M C W W C A A A A B B B B N C C C C D D D
3 C 4 5 6 7 8 9 0 1 D 2 3 4 5 S K E E C 0 1 2 3 0 1 2 3 D 0 1 2 3 0 1 2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
+-------------------------------------------------------------------------------+
| |
| |
| |
| |
| |
D2/PB2--| |--PJ7/!CSD3
D1/PB1--| |--VCC
D0/PB0--| |--PD0/!KBD0/!INT0
TDO--| |--PD1/!KBD1/!INT1
TDI--| |--PD2/!KBD2/!INT2
GND--| |--PD3/!KBD3/!INT3
!OE--| |--PD4/!KBD4/!INT4
!UDS/PC1--| |--PD5/!KBD5/!INT5
!AS--| |--PD6/!KBD6/!INT6
A0--| |--PD7/!KBD7/!INT7
!LDS--| |--GND
R/!W--| |--LD0
!DTACK/PC5--| |--LD1
!RESET--| |--LD2
VCC--| |--LD3
!WE/PC6--| |--LFRM
!JTAGRST--| |--LLP
BBUSW--| MC68328PV |--LCLK
A1--| TOP VIEW |--LACD
A2--| |--VCC
A3--| |--PK0/SPMTXD0
A4--| |--PK1/SPMRXD0
A5--| |--PK2/SPMCLK0
A6--| |--PK3/SPSEN
GND--| |--PK4/SPSRXD1
A7--| |--PK5/SPSCLK1
A8--| |--PK6/!CE2
A9--| |--PK7/!CE1
A10--| |--GND
A11--| |--PM0/!CTS
A12--| |--PM1/!RTS
A13--| |--PM2/!IRQ6
A14--| |--PM3/!IRQ3
VCC--| |--PM4/!IRQ2
A15--| |--PM5/!IRQ1
A16/PA0--| |--PM6/!PENIRQ
| |
| _ |
| (_) |
|\ |
| \ |
+-------------------------------------------------------------------------------+
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
P P P P P G P P P P P P P P V P P P P P P P P G P P P V C G P P P E X P
A A A A A N A A F F F F F F C F F G G G G G G N G G C C L N C M L X T L
1 2 3 4 5 D 6 7 0 1 2 3 4 5 C 6 7 7 6 5 4 3 2 D 1 0 0 C K D 4 7 L T A L
/ / / / / / / / / / / / / / / / / / / / / / / / O / / G A L V
A A A A A A A A A A A A A A A R T ! T ! P R T M ! U N L C
1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 T I T I T W X X O I A D C
7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 C N O N O M D D C R R
O 1 U 2 U O L Q T
T T K 7 G
1 2 P
I
O
Figure 12-1. MC68328 144-Lead Plastic Thin-Quad Flat Pack Pin Assignment
Source: MC68328 (DragonBall)(tm) Integrated Processor User's Manual
*****************************************************************************************************************/
#ifndef __MC68328_H_
#define __MC68328_H_
/***************************************************************************
TYPE DEFINITIONS
***************************************************************************/
struct mc68328_interface
{
const char *m68k_cpu_tag;
devcb_write8 out_port_a_func; /* 8-bit output */
devcb_write8 out_port_b_func; /* 8-bit output */
devcb_write8 out_port_c_func; /* 8-bit output */
devcb_write8 out_port_d_func; /* 8-bit output */
devcb_write8 out_port_e_func; /* 8-bit output */
devcb_write8 out_port_f_func; /* 8-bit output */
devcb_write8 out_port_g_func; /* 8-bit output */
devcb_write8 out_port_j_func; /* 8-bit output */
devcb_write8 out_port_k_func; /* 8-bit output */
devcb_write8 out_port_m_func; /* 8-bit output */
devcb_read8 in_port_a_func; /* 8-bit input */
devcb_read8 in_port_b_func; /* 8-bit input */
devcb_read8 in_port_c_func; /* 8-bit input */
devcb_read8 in_port_d_func; /* 8-bit input */
devcb_read8 in_port_e_func; /* 8-bit input */
devcb_read8 in_port_f_func; /* 8-bit input */
devcb_read8 in_port_g_func; /* 8-bit input */
devcb_read8 in_port_j_func; /* 8-bit input */
devcb_read8 in_port_k_func; /* 8-bit input */
devcb_read8 in_port_m_func; /* 8-bit input */
devcb_write8 out_pwm_func; /* 1-bit output */
devcb_write16 out_spim_func; /* 16-bit output */
devcb_read16 in_spim_func; /* 16-bit input */
void (*spim_xch_trigger)( device_t *device ); /* SPIM exchange trigger */
};
#define MC68328_INTERFACE(name) const mc68328_interface (name)=
#define MC68328_TAG "dragonball"
/***************************************************************************
DEVICE CONFIGURATION MACROS
***************************************************************************/
#define MCFG_MC68328_ADD(_intrf) \
MCFG_DEVICE_ADD("dragonball", MC68328, 0) \
MCFG_DEVICE_CONFIG(_intrf)
/*----------- defined in machine/mc68328.c -----------*/
/***************************************************************************
READ/WRITE HANDLERS
***************************************************************************/
DECLARE_WRITE16_DEVICE_HANDLER( mc68328_w );
DECLARE_READ16_DEVICE_HANDLER( mc68328_r );
/***************************************************************************
EXTERNAL I/O LINES
***************************************************************************/
void mc68328_set_penirq_line(device_t *device, int state);
void mc68328_set_port_d_lines(device_t *device, UINT8 state, int bit);
/***************************************************************************
DEVICE INTERFACE
***************************************************************************/
class mc68328_device : public device_t
{
public:
mc68328_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
~mc68328_device() { global_free(m_token); }
// access to legacy token
void *token() const { assert(m_token != NULL); return m_token; }
protected:
// device-level overrides
virtual void device_config_complete();
virtual void device_start();
virtual void device_reset();
private:
// internal state
void *m_token;
};
extern const device_type MC68328;
/*----------- defined in video/mc68328.c -----------*/
/***************************************************************************
VIDEO INTERFACE
***************************************************************************/
PALETTE_INIT( mc68328 );
VIDEO_START( mc68328 );
SCREEN_UPDATE_IND16( mc68328 );
#endif // __MC68328_H_

2824
src/mess/machine/mc68328.c
View File

File diff suppressed because it is too large Load Diff

647
src/mess/machine/mc68328.h
View File

@ -1,245 +1,95 @@
/**********************************************************************
Motorola 68328 ("DragonBall") System-on-a-Chip implementation
By MooglyGuy
contact mooglyguy@gmail.com with licensing and usage questions.
**********************************************************************/
Motorola 68328 ("DragonBall") System-on-a-Chip private data
/*****************************************************************************************************************
P P P P P P P P P P P P P P
E E E E E E E J J J J J J J
1 2 3 4 5 6 7 0 1 2 3 4 5 6
D D D D D / / / / / / / / / / / / / /
3 4 5 6 7 ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
/ / / / / ! ! C C C C C C C C C C C C C C C
P V P P P P D D G D D D D T T L U V S S S S S S S S G S S S S S S S
B C B B B B D D 1 1 N 1 1 1 1 M C W W C A A A A B B B B N C C C C D D D
3 C 4 5 6 7 8 9 0 1 D 2 3 4 5 S K E E C 0 1 2 3 0 1 2 3 D 0 1 2 3 0 1 2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
+-------------------------------------------------------------------------------+
| |
| |
| |
| |
| |
D2/PB2--| |--PJ7/!CSD3
D1/PB1--| |--VCC
D0/PB0--| |--PD0/!KBD0/!INT0
TDO--| |--PD1/!KBD1/!INT1
TDI--| |--PD2/!KBD2/!INT2
GND--| |--PD3/!KBD3/!INT3
!OE--| |--PD4/!KBD4/!INT4
!UDS/PC1--| |--PD5/!KBD5/!INT5
!AS--| |--PD6/!KBD6/!INT6
A0--| |--PD7/!KBD7/!INT7
!LDS--| |--GND
R/!W--| |--LD0
!DTACK/PC5--| |--LD1
!RESET--| |--LD2
VCC--| |--LD3
!WE/PC6--| |--LFRM
!JTAGRST--| |--LLP
BBUSW--| MC68328PV |--LCLK
A1--| TOP VIEW |--LACD
A2--| |--VCC
A3--| |--PK0/SPMTXD0
A4--| |--PK1/SPMRXD0
A5--| |--PK2/SPMCLK0
A6--| |--PK3/SPSEN
GND--| |--PK4/SPSRXD1
A7--| |--PK5/SPSCLK1
A8--| |--PK6/!CE2
A9--| |--PK7/!CE1
A10--| |--GND
A11--| |--PM0/!CTS
A12--| |--PM1/!RTS
A13--| |--PM2/!IRQ6
A14--| |--PM3/!IRQ3
VCC--| |--PM4/!IRQ2
A15--| |--PM5/!IRQ1
A16/PA0--| |--PM6/!PENIRQ
| |
| _ |
| (_) |
|\ |
| \ |
+-------------------------------------------------------------------------------+
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
P P P P P G P P P P P P P P V P P P P P P P P G P P P V C G P P P E X P
A A A A A N A A F F F F F F C F F G G G G G G N G G C C L N C M L X T L
1 2 3 4 5 D 6 7 0 1 2 3 4 5 C 6 7 7 6 5 4 3 2 D 1 0 0 C K D 4 7 L T A L
/ / / / / / / / / / / / / / / / / / / / / / / / O / / G A L V
A A A A A A A A A A A A A A A R T ! T ! P R T M ! U N L C
1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 T I T I T W X X O I A D C
7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 C N O N O M D D C R R
O 1 U 2 U O L Q T
T T K 7 G
1 2 P
I
O
Figure 12-1. MC68328 144-Lead Plastic Thin-Quad Flat Pack Pin Assignment
Source: MC68328 (DragonBall)(tm) Integrated Processor User's Manual
*****************************************************************************************************************/
By MooglyGuy
contact mooglyguy@gmail.com with licensing and usage questions.
#ifndef __MC68328_H__
#define __MC68328_H__
**********************************************************************/
#ifndef __MC68328_PRIVATE_H_
#define __MC68328_PRIVATE_H_
struct mc68328_regs_t
{
// $(FF)FFF000
UINT8 scr; // System Control Register
UINT8 unused0[255];
// $(FF)FFF100
UINT16 grpbasea; // Chip Select Group A Base Register
UINT16 grpbaseb; // Chip Select Group B Base Register
UINT16 grpbasec; // Chip Select Group C Base Register
UINT16 grpbased; // Chip Select Group D Base Register
UINT16 grpmaska; // Chip Select Group A Mask Register
UINT16 grpmaskb; // Chip Select Group B Mask Register
UINT16 grpmaskc; // Chip Select Group C Mask Register
UINT16 grpmaskd; // Chip Select Group D Mask Register
UINT32 csa0; // Group A Chip Select 0 Register
UINT32 csa1; // Group A Chip Select 1 Register
UINT32 csa2; // Group A Chip Select 2 Register
UINT32 csa3; // Group A Chip Select 3 Register
UINT32 csb0; // Group B Chip Select 0 Register
UINT32 csb1; // Group B Chip Select 1 Register
UINT32 csb2; // Group B Chip Select 2 Register
UINT32 csb3; // Group B Chip Select 3 Register
UINT32 csc0; // Group C Chip Select 0 Register
UINT32 csc1; // Group C Chip Select 1 Register
UINT32 csc2; // Group C Chip Select 2 Register
UINT32 csc3; // Group C Chip Select 3 Register
UINT32 csd0; // Group D Chip Select 0 Register
UINT32 csd1; // Group D Chip Select 1 Register
UINT32 csd2; // Group D Chip Select 2 Register
UINT32 csd3; // Group D Chip Select 3 Register
UINT8 unused1[176];
// $(FF)FFF200
UINT16 pllcr; // PLL Control Register
UINT16 pllfsr; // PLL Frequency Select Register
UINT8 pad2[3];
UINT8 pctlr; // Power Control Register
UINT8 unused3[248];
// $(FF)FFF300
UINT8 ivr; // Interrupt Vector Register
UINT8 unused4[1];
UINT16 icr; // Interrupt Control Register
UINT32 imr; // Interrupt Mask Register
UINT32 iwr; // Interrupt Wakeup Enable Register
UINT32 isr; // Interrupt Status Register
UINT32 ipr; // Interrupt Pending Register
UINT8 unused5[236];
// $(FF)FFF400
UINT8 padir; // Port A Direction Register
UINT8 padata; // Port A Data Register
UINT8 unused6[1];
UINT8 pasel; // Port A Select Register
UINT8 unused7[4];
UINT8 pbdir; // Port B Direction Register
UINT8 pbdata; // Port B Data Register
UINT8 unused8[1];
UINT8 pbsel; // Port B Select Register
UINT8 unused9[4];
UINT8 pcdir; // Port C Direction Register
UINT8 pcdata; // Port C Data Register
UINT8 unused10[1];
UINT8 pcsel; // Port C Select Register
UINT8 unused11[4];
UINT8 pddir; // Port D Direction Register
UINT8 pddata; // Port D Data Register
UINT8 pdpuen; // Port D Pullup Enable Register
UINT8 unused12[1];
UINT8 pdpol; // Port D Polarity Register
UINT8 pdirqen; // Port D IRQ Enable Register
UINT8 pddataedge; // Port D Data Edge Level
UINT8 pdirqedge; // Port D IRQ Edge Register
UINT8 pedir; // Port E Direction Register
UINT8 pedata; // Port E Data Register
UINT8 pepuen; // Port E Pullup Enable Register
UINT8 pesel; // Port E Select Register
UINT8 unused14[4];
UINT8 pfdir; // Port F Direction Register
UINT8 pfdata; // Port F Data Register
UINT8 pfpuen; // Port F Pullup Enable Register
UINT8 pfsel; // Port F Select Register
UINT8 unused15[4];
UINT8 pgdir; // Port G Direction Register
UINT8 pgdata; // Port G Data Register
UINT8 pgpuen; // Port G Pullup Enable Register
UINT8 pgsel; // Port G Select Register
UINT8 unused16[4];
UINT8 pjdir; // Port J Direction Register
UINT8 pjdata; // Port J Data Register
UINT8 unused17[1];
UINT8 pjsel; // Port J Select Register
UINT8 unused18[4];
UINT8 pkdir; // Port K Direction Register
UINT8 pkdata; // Port K Data Register
UINT8 pkpuen; // Port K Pullup Enable Register
UINT8 pksel; // Port K Select Register
UINT8 unused19[4];
UINT8 pmdir; // Port M Direction Register
UINT8 pmdata; // Port M Data Register
UINT8 pmpuen; // Port M Pullup Enable Register
UINT8 pmsel; // Port M Select Register
UINT8 unused20[180];
// $(FF)FFF500
UINT16 pwmc; // PWM Control Register
UINT16 pwmp; // PWM Period Register
UINT16 pwmw; // PWM Width Register
UINT16 pwmcnt; // PWN Counter
UINT8 unused21[248];
// $(FF)FFF600
UINT16 tctl[2]; // Timer Control Register
UINT16 tprer[2]; // Timer Prescaler Register
UINT16 tcmp[2]; // Timer Compare Register
UINT16 tcr[2]; // Timer Capture Register
UINT16 tcn[2]; // Timer Counter
UINT16 tstat[2]; // Timer Status
UINT16 wctlr; // Watchdog Control Register
UINT16 wcmpr; // Watchdog Compare Register
UINT16 wcn; // Watchdog Counter
UINT8 tclear[2]; // Timer Clearable Status
UINT8 unused22[224];
// $(FF)FFF700
UINT16 spisr; // SPIS Register
UINT8 unused23[254];
// $(FF)FFF800
UINT16 spimdata; // SPIM Data Register
UINT16 spimcont; // SPIM Control/Status Register
UINT8 unused24[252];
// $(FF)FFF900
UINT16 ustcnt; // UART Status/Control Register
UINT16 ubaud; // UART Baud Control Register
UINT16 urx; // UART RX Register
UINT16 utx; // UART TX Register
UINT16 umisc; // UART Misc Register
UINT8 unused25[246];
// $(FF)FFFA00
UINT32 lssa; // Screen Starting Address Register
UINT8 unused26[1];
UINT8 lvpw; // Virtual Page Width Register
UINT8 unused27[2];
UINT16 lxmax; // Screen Width Register
UINT16 lymax; // Screen Height Register
UINT8 unused28[12];
UINT16 lcxp; // Cursor X Position
UINT16 lcyp; // Cursor Y Position
UINT16 lcwch; // Cursor Width & Height Register
UINT8 unused29[1];
UINT8 lblkc; // Blink Control Register
UINT8 lpicf; // Panel Interface Config Register
UINT8 lpolcf; // Polarity Config Register
UINT8 unused30[1];
UINT8 lacdrc; // ACD (M) Rate Control Register
UINT8 unused31[1];
UINT8 lpxcd; // Pixel Clock Divider Register
UINT8 unused32[1];
UINT8 lckcon; // Clocking Control Register
UINT8 unused33[1];
UINT8 llbar; // Last Buffer Address Register
UINT8 unused34[1];
UINT8 lotcr; // Octet Terminal Count Register
UINT8 unused35[1];
UINT8 lposr; // Panning Offset Register
UINT8 unused36[3];
UINT8 lfrcm; // Frame Rate Control Modulation Register
UINT16 lgpmr; // Gray Palette Mapping Register
UINT8 unused37[204];
// $(FF)FFFB00
UINT32 hmsr; // RTC Hours Minutes Seconds Register
UINT32 alarm; // RTC Alarm Register
UINT8 unused38[4];
UINT16 rtcctl; // RTC Control Register
UINT16 rtcisr; // RTC Interrupt Status Register
UINT16 rtcienr; // RTC Interrupt Enable Register
UINT16 stpwtch; // Stopwatch Minutes
UINT8 unused42[1260];
};
struct mc68328_t
{
const mc68328_interface* iface;
mc68328_regs_t regs;
emu_timer *gptimer[2];
emu_timer *rtc;
emu_timer *pwm;
devcb_resolved_write8 out_port_a; /* 8-bit output */
devcb_resolved_write8 out_port_b; /* 8-bit output */
devcb_resolved_write8 out_port_c; /* 8-bit output */
devcb_resolved_write8 out_port_d; /* 8-bit output */
devcb_resolved_write8 out_port_e; /* 8-bit output */
devcb_resolved_write8 out_port_f; /* 8-bit output */
devcb_resolved_write8 out_port_g; /* 8-bit output */
devcb_resolved_write8 out_port_j; /* 8-bit output */
devcb_resolved_write8 out_port_k; /* 8-bit output */
devcb_resolved_write8 out_port_m; /* 8-bit output */
devcb_resolved_read8 in_port_a; /* 8-bit input */
devcb_resolved_read8 in_port_b; /* 8-bit input */
devcb_resolved_read8 in_port_c; /* 8-bit input */
devcb_resolved_read8 in_port_d; /* 8-bit input */
devcb_resolved_read8 in_port_e; /* 8-bit input */
devcb_resolved_read8 in_port_f; /* 8-bit input */
devcb_resolved_read8 in_port_g; /* 8-bit input */
devcb_resolved_read8 in_port_j; /* 8-bit input */
devcb_resolved_read8 in_port_k; /* 8-bit input */
devcb_resolved_read8 in_port_m; /* 8-bit input */
devcb_resolved_write8 out_pwm; /* 1-bit output */
devcb_resolved_write16 out_spim; /* 16-bit output */
devcb_resolved_read16 in_spim; /* 16-bit input */
};
#define SCR_BETO 0x80
#define SCR_WPV 0x40
@ -558,11 +408,318 @@ struct mc68328_t
#define PWMC_PWMEN 0x0010
#define PWMC_CLKSEL 0x0007
INLINE mc68328_t* mc68328_get_safe_token( device_t *device )
{
assert( device != NULL );
assert( device->type() == MC68328 );
return (mc68328_t*) downcast<mc68328_device *>(device)->token();
}
#endif // __MC68328_PRIVATE_H_
struct mc68328_interface
{
const char *m68k_cpu_tag;
devcb_write8 m_out_port_a_func; /* 8-bit output */
devcb_write8 m_out_port_b_func; /* 8-bit output */
devcb_write8 m_out_port_c_func; /* 8-bit output */
devcb_write8 m_out_port_d_func; /* 8-bit output */
devcb_write8 m_out_port_e_func; /* 8-bit output */
devcb_write8 m_out_port_f_func; /* 8-bit output */
devcb_write8 m_out_port_g_func; /* 8-bit output */
devcb_write8 m_out_port_j_func; /* 8-bit output */
devcb_write8 m_out_port_k_func; /* 8-bit output */
devcb_write8 m_out_port_m_func; /* 8-bit output */
devcb_read8 m_in_port_a_func; /* 8-bit input */
devcb_read8 m_in_port_b_func; /* 8-bit input */
devcb_read8 m_in_port_c_func; /* 8-bit input */
devcb_read8 m_in_port_d_func; /* 8-bit input */
devcb_read8 m_in_port_e_func; /* 8-bit input */
devcb_read8 m_in_port_f_func; /* 8-bit input */
devcb_read8 m_in_port_g_func; /* 8-bit input */
devcb_read8 m_in_port_j_func; /* 8-bit input */
devcb_read8 m_in_port_k_func; /* 8-bit input */
devcb_read8 m_in_port_m_func; /* 8-bit input */
devcb_write8 m_out_pwm_func; /* 1-bit output */
devcb_write16 m_out_spim_func; /* 16-bit output */
devcb_read16 m_in_spim_func; /* 16-bit input */
devcb_write_line m_spim_xch_trigger_func; /* SPIM exchange trigger */
};
struct mc68328_regs_t
{
// $(FF)FFF000
UINT8 scr; // System Control Register
UINT8 unused0[255];
// $(FF)FFF100
UINT16 grpbasea; // Chip Select Group A Base Register
UINT16 grpbaseb; // Chip Select Group B Base Register
UINT16 grpbasec; // Chip Select Group C Base Register
UINT16 grpbased; // Chip Select Group D Base Register
UINT16 grpmaska; // Chip Select Group A Mask Register
UINT16 grpmaskb; // Chip Select Group B Mask Register
UINT16 grpmaskc; // Chip Select Group C Mask Register
UINT16 grpmaskd; // Chip Select Group D Mask Register
UINT32 csa0; // Group A Chip Select 0 Register
UINT32 csa1; // Group A Chip Select 1 Register
UINT32 csa2; // Group A Chip Select 2 Register
UINT32 csa3; // Group A Chip Select 3 Register
UINT32 csb0; // Group B Chip Select 0 Register
UINT32 csb1; // Group B Chip Select 1 Register
UINT32 csb2; // Group B Chip Select 2 Register
UINT32 csb3; // Group B Chip Select 3 Register
UINT32 csc0; // Group C Chip Select 0 Register
UINT32 csc1; // Group C Chip Select 1 Register
UINT32 csc2; // Group C Chip Select 2 Register
UINT32 csc3; // Group C Chip Select 3 Register
UINT32 csd0; // Group D Chip Select 0 Register
UINT32 csd1; // Group D Chip Select 1 Register
UINT32 csd2; // Group D Chip Select 2 Register
UINT32 csd3; // Group D Chip Select 3 Register
UINT8 unused1[176];
// $(FF)FFF200
UINT16 pllcr; // PLL Control Register
UINT16 pllfsr; // PLL Frequency Select Register
UINT8 pad2[3];
UINT8 pctlr; // Power Control Register
UINT8 unused3[248];
// $(FF)FFF300
UINT8 ivr; // Interrupt Vector Register
UINT8 unused4[1];
UINT16 icr; // Interrupt Control Register
UINT32 imr; // Interrupt Mask Register
UINT32 iwr; // Interrupt Wakeup Enable Register
UINT32 isr; // Interrupt Status Register
UINT32 ipr; // Interrupt Pending Register
UINT8 unused5[236];
// $(FF)FFF400
UINT8 padir; // Port A Direction Register
UINT8 padata; // Port A Data Register
UINT8 unused6[1];
UINT8 pasel; // Port A Select Register
UINT8 unused7[4];
UINT8 pbdir; // Port B Direction Register
UINT8 pbdata; // Port B Data Register
UINT8 unused8[1];
UINT8 pbsel; // Port B Select Register
UINT8 unused9[4];
UINT8 pcdir; // Port C Direction Register
UINT8 pcdata; // Port C Data Register
UINT8 unused10[1];
UINT8 pcsel; // Port C Select Register
UINT8 unused11[4];
UINT8 pddir; // Port D Direction Register
UINT8 pddata; // Port D Data Register
UINT8 pdpuen; // Port D Pullup Enable Register
UINT8 unused12[1];
UINT8 pdpol; // Port D Polarity Register
UINT8 pdirqen; // Port D IRQ Enable Register
UINT8 pddataedge; // Port D Data Edge Level
UINT8 pdirqedge; // Port D IRQ Edge Register
UINT8 pedir; // Port E Direction Register
UINT8 pedata; // Port E Data Register
UINT8 pepuen; // Port E Pullup Enable Register
UINT8 pesel; // Port E Select Register
UINT8 unused14[4];
UINT8 pfdir; // Port F Direction Register
UINT8 pfdata; // Port F Data Register
UINT8 pfpuen; // Port F Pullup Enable Register
UINT8 pfsel; // Port F Select Register
UINT8 unused15[4];
UINT8 pgdir; // Port G Direction Register
UINT8 pgdata; // Port G Data Register
UINT8 pgpuen; // Port G Pullup Enable Register
UINT8 pgsel; // Port G Select Register
UINT8 unused16[4];
UINT8 pjdir; // Port J Direction Register
UINT8 pjdata; // Port J Data Register
UINT8 unused17[1];
UINT8 pjsel; // Port J Select Register
UINT8 unused18[4];
UINT8 pkdir; // Port K Direction Register
UINT8 pkdata; // Port K Data Register
UINT8 pkpuen; // Port K Pullup Enable Register
UINT8 pksel; // Port K Select Register
UINT8 unused19[4];
UINT8 pmdir; // Port M Direction Register
UINT8 pmdata; // Port M Data Register
UINT8 pmpuen; // Port M Pullup Enable Register
UINT8 pmsel; // Port M Select Register
UINT8 unused20[180];
// $(FF)FFF500
UINT16 pwmc; // PWM Control Register
UINT16 pwmp; // PWM Period Register
UINT16 pwmw; // PWM Width Register
UINT16 pwmcnt; // PWN Counter
UINT8 unused21[248];
// $(FF)FFF600
UINT16 tctl[2]; // Timer Control Register
UINT16 tprer[2]; // Timer Prescaler Register
UINT16 tcmp[2]; // Timer Compare Register
UINT16 tcr[2]; // Timer Capture Register
UINT16 tcn[2]; // Timer Counter
UINT16 tstat[2]; // Timer Status
UINT16 wctlr; // Watchdog Control Register
UINT16 wcmpr; // Watchdog Compare Register
UINT16 wcn; // Watchdog Counter
UINT8 tclear[2]; // Timer Clearable Status
UINT8 unused22[224];
// $(FF)FFF700
UINT16 spisr; // SPIS Register
UINT8 unused23[254];
// $(FF)FFF800
UINT16 spimdata; // SPIM Data Register
UINT16 spimcont; // SPIM Control/Status Register
UINT8 unused24[252];
// $(FF)FFF900
UINT16 ustcnt; // UART Status/Control Register
UINT16 ubaud; // UART Baud Control Register
UINT16 urx; // UART RX Register
UINT16 utx; // UART TX Register
UINT16 umisc; // UART Misc Register
UINT8 unused25[246];
// $(FF)FFFA00
UINT32 lssa; // Screen Starting Address Register
UINT8 unused26[1];
UINT8 lvpw; // Virtual Page Width Register
UINT8 unused27[2];
UINT16 lxmax; // Screen Width Register
UINT16 lymax; // Screen Height Register
UINT8 unused28[12];
UINT16 lcxp; // Cursor X Position
UINT16 lcyp; // Cursor Y Position
UINT16 lcwch; // Cursor Width & Height Register
UINT8 unused29[1];
UINT8 lblkc; // Blink Control Register
UINT8 lpicf; // Panel Interface Config Register
UINT8 lpolcf; // Polarity Config Register
UINT8 unused30[1];
UINT8 lacdrc; // ACD (M) Rate Control Register
UINT8 unused31[1];
UINT8 lpxcd; // Pixel Clock Divider Register
UINT8 unused32[1];
UINT8 lckcon; // Clocking Control Register
UINT8 unused33[1];
UINT8 llbar; // Last Buffer Address Register
UINT8 unused34[1];
UINT8 lotcr; // Octet Terminal Count Register
UINT8 unused35[1];
UINT8 lposr; // Panning Offset Register
UINT8 unused36[3];
UINT8 lfrcm; // Frame Rate Control Modulation Register
UINT16 lgpmr; // Gray Palette Mapping Register
UINT8 unused37[204];
// $(FF)FFFB00
UINT32 hmsr; // RTC Hours Minutes Seconds Register
UINT32 alarm; // RTC Alarm Register
UINT8 unused38[4];
UINT16 rtcctl; // RTC Control Register
UINT16 rtcisr; // RTC Interrupt Status Register
UINT16 rtcienr; // RTC Interrupt Enable Register
UINT16 stpwtch; // Stopwatch Minutes
UINT8 unused42[1260];
};
class mc68328_device : public device_t,
public mc68328_interface
{
public:
mc68328_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
~mc68328_device() {}
DECLARE_WRITE16_MEMBER(write);
DECLARE_READ16_MEMBER(read);
DECLARE_WRITE_LINE_MEMBER(set_penirq_line);
void set_port_d_lines(UINT8 state, int bit);
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
protected:
// device-level overrides
virtual void device_config_complete();
virtual void device_start();
virtual void device_reset();
private:
// internal state
void set_interrupt_line(UINT32 line, UINT32 active);
void poll_port_d_interrupts();
UINT32 get_timer_frequency(UINT32 index);
void maybe_start_timer(UINT32 index, UINT32 new_enable);
void timer_compare_event(UINT32 index);
void register_state_save();
TIMER_CALLBACK_MEMBER(timer1_hit);
TIMER_CALLBACK_MEMBER(timer2_hit);
TIMER_CALLBACK_MEMBER(pwm_transition);
TIMER_CALLBACK_MEMBER(rtc_tick);
mc68328_regs_t m_regs;
emu_timer *m_gptimer[2];
emu_timer *m_rtc;
emu_timer *m_pwm;
devcb_resolved_write8 m_out_port_a; /* 8-bit output */
devcb_resolved_write8 m_out_port_b; /* 8-bit output */
devcb_resolved_write8 m_out_port_c; /* 8-bit output */
devcb_resolved_write8 m_out_port_d; /* 8-bit output */
devcb_resolved_write8 m_out_port_e; /* 8-bit output */
devcb_resolved_write8 m_out_port_f; /* 8-bit output */
devcb_resolved_write8 m_out_port_g; /* 8-bit output */
devcb_resolved_write8 m_out_port_j; /* 8-bit output */
devcb_resolved_write8 m_out_port_k; /* 8-bit output */
devcb_resolved_write8 m_out_port_m; /* 8-bit output */
devcb_resolved_read8 m_in_port_a; /* 8-bit input */
devcb_resolved_read8 m_in_port_b; /* 8-bit input */
devcb_resolved_read8 m_in_port_c; /* 8-bit input */
devcb_resolved_read8 m_in_port_d; /* 8-bit input */
devcb_resolved_read8 m_in_port_e; /* 8-bit input */
devcb_resolved_read8 m_in_port_f; /* 8-bit input */
devcb_resolved_read8 m_in_port_g; /* 8-bit input */
devcb_resolved_read8 m_in_port_j; /* 8-bit input */
devcb_resolved_read8 m_in_port_k; /* 8-bit input */
devcb_resolved_read8 m_in_port_m; /* 8-bit input */
devcb_resolved_write8 m_out_pwm; /* 1-bit output */
devcb_resolved_write16 m_out_spim; /* 16-bit output */
devcb_resolved_read16 m_in_spim; /* 16-bit input */
devcb_resolved_write_line m_spim_xch_trigger; // not really a write_line, fix when converting to devcb2!
cpu_device *m_cpu;
};
#define MC68328_INTERFACE(name) const mc68328_interface (name)=
#define MCFG_MC68328_ADD(_tag, _intrf) \
MCFG_DEVICE_ADD(_tag, MC68328, 0) \
MCFG_DEVICE_CONFIG(_intrf)
extern const device_type MC68328;
#endif

1
src/mess/mess.mak
View File

@ -1525,7 +1525,6 @@ $(MESSOBJ)/osi.a: \
$(MESSOBJ)/palm.a: \
$(MESS_DRIVERS)/palm.o \
$(MESS_MACHINE)/mc68328.o \
$(MESS_VIDEO)/mc68328.o \
$(MESS_DRIVERS)/palmz22.o \
$(MESSOBJ)/parker.a: \

66
src/mess/video/mc68328.c
View File

@ -1,66 +0,0 @@
/**********************************************************************
Motorola 68328 ("DragonBall") System-on-a-Chip LCD implementation
By MooglyGuy
contact mooglyguy@gmail.com with licensing and usage questions.
**********************************************************************/
#include "emu.h"
#include "includes/mc68328.h"
#include "machine/mc68328.h"
#include "machine/ram.h"
/* THIS IS PRETTY MUCH TOTALLY WRONG AND DOESN'T REFLECT THE MC68328'S INTERNAL FUNCTIONALITY AT ALL! */
PALETTE_INIT( mc68328 )
{
palette_set_color_rgb(machine, 0, 0x7b, 0x8c, 0x5a);
palette_set_color_rgb(machine, 1, 0x00, 0x00, 0x00);
}
VIDEO_START( mc68328 )
{
}
/* THIS IS PRETTY MUCH TOTALLY WRONG AND DOESN'T REFLECT THE MC68328'S INTERNAL FUNCTIONALITY AT ALL! */
SCREEN_UPDATE_IND16( mc68328 )
{
device_t *mc68328_device = screen.machine().device(MC68328_TAG);
mc68328_t* mc68328 = mc68328_get_safe_token( mc68328_device );
const UINT16 *video_ram = (const UINT16 *)(screen.machine().device<ram_device>(RAM_TAG)->pointer() + (mc68328->regs.lssa & 0x00ffffff));
UINT16 word;
UINT16 *line;
int y, x, b;
if(mc68328->regs.lckcon & LCKCON_LCDC_EN)
{
for (y = 0; y < 160; y++)
{
line = &bitmap.pix16(y);
for (x = 0; x < 160; x += 16)
{
word = *(video_ram++);
for (b = 0; b < 16; b++)
{
line[x + b] = (word >> (15 - b)) & 0x0001;
}
}
}
}
else
{
for (y = 0; y < 160; y++)
{
line = &bitmap.pix16(y);
for (x = 0; x < 160; x++)
{
line[x] = 0;
}
}
}
return 0;
}